This document discusses designing a MOD-5 down counter with active high and low clear inputs. It explains mapping flip flop combinations to determine the next state and minimize the clear logic using a K-map. Initially, all flip flops are reset to 000 and the counter transitions states asynchronously in a ripple fashion on each clock cycle until it rolls over from 000 to 111.
This document discusses designing a MOD-5 down counter with active high and low clear inputs. It explains mapping flip flop combinations to determine the next state and minimize the clear logic using a K-map. Initially, all flip flops are reset to 000 and the counter transitions states asynchronously in a ripple fashion on each clock cycle until it rolls over from 000 to 111.
This document discusses designing a MOD-5 down counter with active high and low clear inputs. It explains mapping flip flop combinations to determine the next state and minimize the clear logic using a K-map. Initially, all flip flops are reset to 000 and the counter transitions states asynchronously in a ripple fashion on each clock cycle until it rolls over from 000 to 111.
3 bit so 3 JKFF, we are drawing excitation table J2K2, J1K1,J0K0, take reference from Original JKFF excitation table
and put values
Way to verify how counter suffers from lock out probelm just map the flipflop combinations with present state and write o/p wrt to that = next state Table for CLR to minimize the Logic for CLR we can draw kmap CLR = Q2' Q0
1.Design MOD-5 down counter,when all FF
are initially reset.
Since initially reset Q2Q1Q0 = 000
To find minterm for clr we are putting 1 for clr Otherwise when 011 occurs Active high clr = Q2' Q1 Active low clr = (Q2' Q1)' Asynchronous means Ripple counter only in that we have binary and non-binary as division 1.Given initially reset to 000 is calculated from initial i/p 000 and Q1 is calculated seeing Q0 transition