S E M I C O N D U C T O R HSP43891

January 1996 Digital Filter

Features Description
• Eight Filter Cells The HSP43891 is a video-speed Digital Filter (DF)
• 0MHz to 30MHz Sample Rate designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
• 9-Bit Coefficients and Signal Data
cascaded internally and a shift and add output stage, all in
• 26-Bit Accumulator per Stage a single integrated circuit. Each filter cell contains a 9x9
• Filter Lengths Over 1000 Taps two’s complement multiplier, three decimation registers and
• Expandable Coefficient Size, Data Size and Filter Length a 26-bit accumulator. The output stage contains an
• Decimation by 2, 3 or 4 additional 26-bit accumulator which can add the contents of
any filter cell accumulator to the output stage accumulator
shifted right by 8-bits. The HSP43891 has a maximum
Applications sample rate of 30MHz. The effective multiply-accumulate
• 1-D and 2-D FIR Filters (mac) rate is 240MHz.
• Radar/Sonar
The HSP43891 DF can be configured to process expanded
• Digital Video coefficient and word sizes. Multiple DFs can be cascaded
• Adaptive Filters for larger filter lengths without degrading the sample rate or
• Echo Cancellation a single DF can process larger filter lengths at less than
• Complex Multiply-Add 30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
• Sample Rate Converters
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
Ordering Information lengths possible. The DF provides for 8-bit unsigned or
9-bit two’s complement arithmetic, independently
PART NUMBER TEMP. RANGE PACKAGE
selectable for coefficients and signal data.
o o
HSP43891VC-20 0 C to +70 C 100 Lead MQFP
Each DF filter cell contains three resampling or decimation
HSP43891VC-25 0oC to +70oC 100 Lead MQFP registers which permit output sample rate reduction at rates
HSP43891VC-30 0oC to +70oC 100 Lead MQFP of 1/2, 1/3 or 1/4 the input sample rate. These registers also
HSP43891JC-20 0oC to +70oC 84 Lead PLCC
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial correlations/convolu-
o o
HSP43891JC-25 0 C to +70 C 84 Lead PLCC tions for image processing applications.
HSP43891JC-30 0oC to +70oC 84 Lead PLCC
o o
HSP43891GC-20 0 C to +70 C 85 Pin CPGA
oC +70oC
HSP43891GC-25 0 to 85 Pin CPGA
HSP43891GC-30 0oC to +70oC 85 Pin CPGA

Block Diagram
VCC VSS DIN0 - DIN8
DIENB 9
CIENB 5
DCM0 - 1
ERASE
DF DF DF DF DF DF DF DF
9 FILTER 9 FILTER 9 FILTER 9 FILTER 9 FILTER 9 FILTER 9 FILTER 9 FILTER 9
CIN0 - 8 CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 COUT0 - 8
RESET 5 5 26 26 26 26 26 26 26 26
CLK COENB
ADRO - 2 3
MUX

RESET ADR0, ADR1, ADR2 26

CLK 2
OUTPUT
SHADD
STAGE
SENBL
SENBH 2 26
SUM0 - 25

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 2785.4
Copyright © Harris Corporation 1995
1
 HSP43891

Pinouts
85 PIN GRID ARRAY (PGA)

1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11

A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9

B VCC COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 K
SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6
ALIGN J
C COUT5 COUT6 PIN DIENB DIN5 DIN4 CIN5 CIN3
VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS

VCC H
D COUT3 COUT4 CIN2
ADR1 ADR0 SUM5 SUM4
G
E COUT1 VSS COUT2 CIN1 CIN0 SENBL
ADR2 DCM0 CLK HSP43891 SUM1 SUM3 SUM2
HSP43891 F
F VSS COUT0 SHADD VCC VSS BOTTOM VIEW
SUM0 VSS COUT0 SHADD
TOP VIEW PINS UP SUM0 VCC VSS

G ADR2 DCM0 CLK

PINS DOWN SUM3 SUM2
E
SUM1
COUT1 VSS COUT2 CIN1 CIN0 SENBL
D
H ADR1 ADR0 SUM5 SUM4 VCC
COUT3 COUT4 CIN2

C
J VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS
COUT5 COUT6 ALIGN DIENB DIN5 DIN4 CIN5 CIN3
PIN
B
K SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6
VCC COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4
A
L DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS

84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

SENBH

SHADD
ADDR0
ADDR1

ADDR2

COUT0
COUT1

COUT2
COUT3
COUT4
COUT5
SUM24

SUM25
DCM1

DCM0

CLK
VCC
VSS

VSS

VSS

VCC

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

SUM23 12 74 COUT6
SUM22 13 73 COUT7
VCC 14 72 VSS
SUM21 15 71 COUT8
SUM20 16 70 COENB
SUM19 17 69 VCC
SUM18 18 68 ERASE
VSS 19 67 RESET
SUM17 20 66 DIENB
SUM16
VCC
21 HSP43891 65 DIN8
22 64 DIN7
SUM15 23 TOP VIEW 63 DIN6
SUM14 24 62 DIN5
SUM13 25 61 DIN4
SUM12 26 60 DIN3
VSS 27 59 DIN2
SUM11 28 58 DIN1
SUM10 29 57 DIN0
SUM9 30 56 CIENB
SUM8 31 55 CIN8
SUM7 32 54 VCC

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
VSS

VCC

VSS

VCC

VSS
SUM6

SUM5
SUM4

SUM3
SUM2
SUM1
SUM0

SENBL
CIN0
CIN1

CIN2
CIN3
CIN4
CIN5

CIN6
CIN7

2
 HSP43891

Pinouts (Continued)
100 LEAD MQFP
TOP VIEW

SHADD
SENBH

ADDR0
ADDR1

ADDR2

COUT0
COUT1

COUT2
COUT3
SUM25

DCM0

CLK
VCC
VCC

VSS
VSS

VSS
VSS
VCC
VCC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DCM1 1 80 COUT4
SUM24 2 79 COUT5
VSS 3 78 VCC
VSS 4 77 VCC
SUM23 5 76 COUT6
SUM22 6 75 COUT7
VCC 7 74 VSS
VCC 8 73 VSS
SUM21 9 72 COUT8
SUM20 10 71 COENB
SUM19 11 70 VCC
SUM18 12 69 VCC
VSS 13 68 ERASE
VSS 14 67 RESET
SUM17 15 66 DIENB
SUM16 16 65 DIN8
VCC 17 64 DIN7
VCC 18 63 DIN6
SUM15 19 62 DIN5
SUM14 20 61 DIN4
SUM13 21 60 DIN3
SUM12 22 59 DIN2
VSS 23 58 DIN1
SUM11 24 57 DIN0
SUM10 25 56 CIENB
SUM9 26 55 CIN8
SUM8 27 54 VCC
SUM7 28 53 CIN7
NC 29 52 CIN6
SUM6 30 51 VSS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SUM5
SUM4

SUM3
SUM2
SUM1
SUM0

SENBL
CIN0
CIN1

CIN2
CIN3
CIN4
CIN5
VSS
VSS

VSS
VSS

VSS
VCC
VCC

3
 HSP43891

Pin Description
PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

VCC B1, J1, A3, K4, +5 power supply input

L7, A10, F10,
D11

VSS A1, F1, E2, K3, Power supply ground input.

K6, L9, A11,
F11, J11

CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

DIN0-8 A5-8, B5-7, I These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded
C6, C7 through these pins to the X register of each filter cell of the DF simultaneously. The DIENB signal
enables loading, which is synchronous on the rising edge of the clock signal.
The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s
complement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical
zero.

DIENB C5 I A low on this input enables the data sample input bus (DIN0-8) to all the filter cells. A rising edge
of the CLK signal occurring while DIENB is low will load the X register of every filter cell with the
9-bit value present on DIN0-8. A high on this input forces all the bits of the data sample input bus
to zero; a rising CLK edge when DIENB is high will load the X register of every filter cell with all
zeros. This signal is latched inside the device, delaying its effect by one clock internal to the device.
Therefore it must be low during the clock cycle immediately preceding presentation of the desired
data on the DIN0-8 inputs. Detailed operation is shown in later timing diagrams.

CIN0-8 A9, B9-11, I These nine inputs are used to input the 9-bit coefficients. The coefficients are synchronously load-
C10, C11, ed into the C register of filter CELL0 if a rising edge of CLK occurs while CIENB is low. The CIENB
D10, E9, E10 signal is delayed by one clock as discussed below.
The coefficients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s com-
plement values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero.

ALIGN PIN C3 Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in
circuit.

CIENB B8 I A low on this input enables the C register of every filter cell and the D (decimation) registers of
every filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occur-
ring while CIENB is low will load the C register and appropriate D registers with the coefficient data
present at their inputs. This provides the mechanism for shifting coefficients from cell to cell
through the device. A high on this input freezes the contents of the C register and the D registers,
ignoring the CLK signal. This signal is latched and delayed by one clock internal to the DF. There-
fore it must be low during the clock cycle immediately preceding presentation of the desired coef-
ficient on the CIN0-8 inputs. Detailed operation is shown in later timing diagrams.

COUT0-8 B2, B3, C1, D1, O These nine three-state outputs are used to output the 9-bit coefficients from filter CELL7. These
E1, C2, D2, F2, outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of
E3 the same DF to recirculate to coefficients, or they may be tied to the CIN0-8 inputs of another DF
to cascade DFs for longer filter lengths.

COENB A2 I A low on the COENB input enables the COUT0-8 outputs. A high on this input places all these
outputs in their high impedance state.

DCM0-1 L1, G2 I These two inputs determine the use of the internal decimation registers as follows:

DCM1 DCM0 DECIMATION FUNCTION

0 0 Decimation registers not used
0 1 One decimation register is used
1 0 Two decimation registers are used
1 1 Three decimation registers are used

The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the device.

4
 HSP43891

Pin Description (Continued)

PIN
SYMBOL NUMBER TYPE NAME AND FUNCTION

SUM0-25 F9, G9-G11, O These 26 three-state outputs are used to output the results of the internal filter cell computations.
H10, H11, J2, Individual filter cell results or the result of the shift and add output stage can be output. If an indi-
J5-J7, J10, K2, vidual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD
K5, K7-K11, signal determines whether the selected filter cell result or the output stage adder result is output.
L2-L6, L8, L10, The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-
L11 25 result respectively. Both SENBH and SENBL may be enabled simultaneously if the system has
a 26-bit or larger bus. However individual enables are provided to facilitate use with a 16-bit bus.

SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.

SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high
impedance state.

ADR0-2 G1, H1, H2 I These three inputs select the one cell whose accumulator will be read through the output bus
(SUM0-25) or added to the output stage accumulator. They also determine which accumulator will
be cleared when ERASE is low. These inputs are latched in the DF and delayed by one clock in-
ternal to the device. If ADR0-2 remains at the same address for more than one clock, the output
at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell.
Only the result available during the first clock, when ADR0-2 selects the cell, will be output. This
does not hinder normal operation since the ADR0-2 lines are changed sequentially. This feature
facilitates the interface with slow memories where the output is required to be fixed for more than
one clock.

SHADD F3 I The SHADD input controls the activation of the shift and add operation in the output stage. This
signal is latched on chip and delayed by one clock internal to the device. Detailed explanation is
given in the DF Output Stage section.

RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators It
can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched
in the DF and delayed by one clock internal to the device.

ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If
RESET is also low simultaneously, all cell accumulators are cleared.

5
 HSP43891
Functional Description
The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each fil-
ter cell contains a multiplier-accumulator and several regis-
ters (Figure 1). Each 9-bit coefficient is multiplied by a 9-bit
data sample, with the result added to the 26-bit accumulator
contents. The coefficient output of each cell is cascaded to
the coefficient input of the next cell to its right.
DF Filter Cell
A 9-bit coefficient (CIN0-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-8. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock fol-
lowing its entrance. When decimation is selected the coeffi-
cient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-8) are connected to the CIN0-8
inputs of the next cell to its right. The COENB input signal
enables the COUT0-8 outputs of the right most cell to the
COUT0-8 pins of the device.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note
that CIENB is latched internally. It enables the register for
loading after the next CLK following the onset of CIENB low.
Actual loading occurs on the second CLK following the onset
of CIENB low. Therefore CIENB must be low during the
clock cycle immediately preceding presentation of the coeffi-
cient on the CIN0-8 inputs. In most basic FIR operations,
CIENB will be low throughout the process, so this latching
and delay sequence is only important during the initialization
phase. When CIENB is high, the coefficients are frozen.
The C and D registers are cleared synchronously under con-
trol of RESET, which is latched and delayed exactly like
CIENB. The output of the C register (C0-8) is one input to
9x9 multiplier.
The other input to the 9 x 9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DIN0-8 discussed above. The
X register is enabled for loading by DIENB. Loading is syn-
chronous with CLK when DIENB is low. Note that DIENB is
latched internally. It enables the register for loading after the
next CLK following the onset of DIENB low. Actual loading
occurs on the second CLK following the onset of DIENB low;
therefore, DIENB must be low during the clock cycle immedi-
ately preceding presentation of the data sample on the
DIN0-8 inputs. In most basic FIR operations, DIENB will be
low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When DIENB is high, the X register is loaded with all zeros.
The multiplier is pipelined and is modeled as a multiplier core
followed by two pipeline registers, MREG0 and MREG1 (Fig-
ure 1). The multiplier output is sign extended and input as one
operand of the 26-bit adder. The other adder operand is the
6
output of the 26-bit accumulator. The adder output is loaded
synchronously into both the accumulator and the TREG.
The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number. The cell select is decoded
from the ADR0-2 signals to generate the TREG load enable.
The cell select is inverted and applied as the load enable to
the TREG. Operation is such that the TREG is loaded when-
ever the cell is not selected. Therefore, TREG is loaded every
clock except the clock following cell selection. The purpose of
the TREG is to hold the result of a sum-of-products calcula-
tion during the clock when the accumulator is cleared to pre-
pare for the next sum-of-products calculation. This allows
continuous accumulation without wasting clocks.
The accumulator is loaded with the adder output every clock
unless it is cleared. It is cleared synchronously in two ways.
When RESET and ERASE are both low, the accumulator is
cleared along with all other registers on the device. Since
ERASE and RESET are latched and delayed one clock
internally, clearing occurs on the second CLK following the
onset of both ERASE and RESET low.
The second accumulator clearing mechanism clears a single
accumulator in a selected cell. The cell select signal, CELLn,
decoded from ADR0-2 and the ERASE signal enable clear-
ing of the accumulator on the next CLK.
The ERASE and RESET signals clear the DF internal regis-
ters and states as follows:
ERASE RESET CLEARING EFFECT
1 1 No clearing occurs, internal state remains
same.
1 0 RESET only active, all registers except ac-
cumulators are cleared, including the inter-
nal pipeline registers.
0 1 ERASE only active, the accumulator
whose address is given by the ADR0-2 in-
puts is cleared.
0 0 Both RESET and ERASE active, all accu-
mulators as well as all other registers are
cleared.
The DF Output Stage
The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driver stage (Figure 2).
The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer. This
result is stored back in the output buffer. This operation
takes place in one clock period. The eight LSBs of the output
buffer are lost. The filter cell accumulator is selected by the
ADR0-2 inputs.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero
mux is controlled by the SHADD input signal and selects
either the output buffer 18 MSBs or all zeros for the adder
input. A low on the SHADD input selects zero. A high on the
SHADD input selects the output buffer MSBs, thus activating
the shift-and-add operation. The SHADD signal is latched
and delayed by one clock internally.
 HSP43891

DCM1.D

DCM0.D

RESET.D
CIENB.D

LD CLR LD CLR LD CLR LD CLR THREE-STATE BUFFERS

ON CELL 7 ONLY
C REG D1 REG D2 REG D3 REG
C0-8 1 1
CIN0-8
MUX MUX
COUT0-8
CLK CLK
D0-8 CLK
0 0
C0-8
RESET.D COENB
DIENB.D

LD CLR
C
X REG X0-8 MULTI-
DIN0-8 X PLIER
CORE
P0-17
CLK

MREG0
RESET.D CLR CLK
LATCHES

DCM1 DCM1.D
DCM0 DCM0.D
RESET RESET.D MREG1

DIENB DIENB.D CLR

CIENB CIENB.D
ADR0 ADR0.D
0-17 SIGN EXTENSION
ADR1 ADR1.D ACC.D0-25
ADR2 ADR2.D
ERASE ERASE.D

ADDER
CLK
ACC0-25

ACC
ERASE.D
CLR CLK

CELLn

ADR0 CELL 0
CELL 1
DE-
ADR1
CODER
ADR2 CELL 7
T REG
CELLn D Q LD
CLK

AOUT0-25

FIGURE 1. HSP43891 DF FILTER CELL

7
 HSP43891

0 1 6 7 This does not hinder normal FIR operation since the ADR0-2
CELL RESULTS lines are changed sequentially. This feature facilitates the
26 26 26 26 interface with slow memories where the output is required to
be fixed for more than one clock.
3 CELL RESULT
ADR0.D - ADR2.D MUX The SUM0-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUM0-15. A
0-18 low on SENBH enables bits SUM16-25. Thus all 26 bits can
18
be output simultaneously if the external system has a 26-bit
SIGN EXT
18-25 8 26 or larger bus. If the external system bus is only 16 bits, the
bits can be enabled in two groups of 16 and 10 bits (sign
18 (LSBs) extended).
RESET.D 0-17 +
26
DF Arithmetic
CLR SHADD.D ZERO
OUTPUT
Both data samples and coefficients can be represented as
Q MUX CLK
D BUFFER either 8-bit unsigned or 9-bit two’s complement numbers.
SHADD 0 1 RESET.D
The 9x9 bit multiplier in each cell expects 9-bit two’s
26 complement operands. The binary format of 8-bit two’s
CLK 18 8-25
0-17 complement is shown below. Note that if the most significant
0’s or sign bit is held at logical zero, the 9-bit two’s complement
26 26
18 MSBs SHIFTED multiplier can multiply 8-bit unsigned operands. Only the
8 BITS TO RIGHT upper (positive) half of the two’s complement binary range is
1 0 used.
OUTPUT
MUX The multiplier output is 18 bits and the accumulator is 26
RESET.D
bits. The accumulator width determines the maximum
26
possible number of terms in the sum of products without
overflow. The maximum number of terms depends also on
CLR 2
Q
SENBL 3-STATE the number system and the distribution of the coefficient and
D BUFFER
SENBH data values. Then maximum numbers of terms in the sum
products are:
26
CLK
MAXIMUM # OF TERMS
SUM0-25

NUMBER SYSTEM 8-BIT 9-BIT

FIGURE 2. HSP43891 DFP OUTPUT STAGE
Two Unsigned Vectors 1032 N/A
The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the SUM0-25 Two Two’s Complement Vectors
bus. The output mux determines whether the cell
• Two Positive Vectors 2080 1032
accumulator selected by ADR0-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD input • Negative Vectors 2047 1024
signal. Control is based on the state of the SHADD during
two successive clocks; in other words, the output mux • One Positive and One Negative 2064 1028
selection contains memory. If SHADD is low during a clock Vector
cycle and was low during the previous clock, the output mux
selects the contents of the filter cell accumulator addressed One Unsigned 8-Bit Vector and One
by ADR0-2. Otherwise the output mux selects the contents Two’s Complement Vector
of the output buffer.
• Positive Two’s Complement Vector 1036 1032
If the ADR0-2 lines remain at the same address for more
than one clock, the output at SUM0-25 will not change to • Negative Two’s Complement Vector 1028 1028
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock For practical FIR filters, the coefficients are never all near
when ADR0-2 selects the cell will be output. maximum value, so even larger vectors are possible in
practice.

8
 HSP43891

Basic FIR Operation

A simple, 30MHz 8-tap filter example serves to illustrate
more clearly the operation of the DF. The sequence table
(Table 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, CN,
enters the DF on the left and moves from left to right through
the cells. The data sample sequence, XN, enters the DF
from the top, with each cell receiving the same sample
simultaneously. Each cell accumulates the sum of products
for one output point. Eight sums of products are calculated
simultaneously, but staggered in time so that a new output is
available every system clock.

TABLE 1. HSP43891 30MHz, 8-TAP FIR FILTER SEQUENCE

X15 . . . X9, X8, X7 . . . X1, X0

C0 . . . C6, C7, C0 . . . C6, C7 HSP43891 . . . Y15, Y14 . . . Y8, Y7

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR
0 C7 x X0 0 0 0 - - - - -
1 +C6 x X1 C7 x X1 0 0 - - - - -
2 +C5 x X2 +C6 x X2 C7 x X2 0 - - - - -
3 +C4 x X3 +C5 x X3 +C6 x X3 C7 x X3 - - - - -
4 +C3 x X4 +C4 x X4 +C5 x X4 +C6 x X4 C7 x X4 - - - -
5 +C2 x X5 +C3 x X5 +C4 x X5 +C5 x X5 +C6 x X5 C7 x X5 - - -
6 +C1 x X6 +C2 x X6 +C3 x X6 +C4 x X6 +C5 x X6 +C6 x X6 C7 x X6 - -
7 +C0 x X7 +C1 x X7 +C2 x X7 +C3 x X7 +C4 x X7 +C5 x X7 +C6 x X7 C7 x X7 Cell 0 (Y7)
8 C7 x X8 +C0 x X8 +C1 x X8 +C2 x X8 +C3 x X8 +C4 x X8 +C5 x X8 +C6 x X8 Cell 1 (Y8)
9 +C6 x X9 C7 x X9 +C0 x X9 +C1 x X9 +C2 x X9 +C3 x X9 +C4 x X9 +C5 x X9 Cell 2 (Y9)
10 +C5 x X10 +C6 x X10 C7 x X10 +C0 x X10 +C1 x X10 +C2 x X10 +C3 x X10 +C4 x X10 Cell 3 (Y10)
11 +C4 x X11 +C5 x X11 +C6 x X11 C7 x X11 +C0 x X11 +C1 x X11 +C2 x X11 +C3 x X11 Cell 4 (Y11)
12 +C3 x X12 +C4 x X12 +C5 x X12 +C6 x X12 C7 x X12 +C0 x X12 +C1 x X12 +C2 x X12 Cell 5 (Y12)
13 +C2 x X13 +C3 x X13 +C4 x X13 +C5 x X13 +C6 x X13 C7 x X13 +C0 x X13 +C1 x X13 Cell 6 (Y13)
14 +C1 x X14 +C2 x X14 +C3 x X14 +C4 x X14 +C5 x X14 +C6 x X14 +C7 x X14 +C0 x X14 Cell 7 (Y14)
15 +C0 x X15 +C1 x X15 +C2 x X15 +C3 x X15 +C4 x X15 +C5 x X15 +C6 x X15 C7 x X15 Cell 0 (Y15)

SAMPLE
DATA IN (XN)

3-BIT
30MHz COUNTER
CLOCK +5V
Y2 Y1 Y0

ADR2 ADR1 ADR0 VCC SHADD SENBH SENBL

9 26
DIN0-8 SUM0-25 SUM
OUT (YN)
DIENB

CLK

A2 A1 A0 HSP43891

D0-D8

9 x 8 COEFF.
RAM/ROM 9 9
CIN0-8 COUT0-8 NC

CIENB DCM1 DCM0 RESET ERASE VSS COENB

SYSTEM
RESET
ERASE

FIGURE 3. HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC

9
 HSP43891

Detailed operation of the DF to perform a basic 8-tap, 9-bit Td = 4, the internal pipeline delay of the DF. After the pipe-
coefficient, 9-bit data, 30MHz FIR filter is best understood by line has filled, a new output sample is available every clock.
observing the schematic (Figure 3) and timing diagram (Fig- The delay to last sample output from last sample input is Td.
ure 4). The internal pipeline length of the DF is four (4) clock The output sums, YN, shown in the timing diagram are
cycles, corresponding to the register levels CREG (or derived from the sum-of-products equation:
XREG), MREG0, MREG1, and TREG (Figures 1 and 2). 7
Therefore the delay from presentation of data and coeffi-
YN = Σ CK XN –K
cients at the DIN0-8 and CIN0-8 inputs to a sum appearing
K = 0
at the SUM0-25 output is: k + Td, where k = filter length and

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLK

RESET

ERASE

DIN0-8 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18

DIENB

CIN0-8 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5

CIENB

ADR0-2 0 1 2 3 4 5 6 7 0

SUM0-25 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14

SHADD

SENBL

SENBH

DCM0-1 0

FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING

SAMPLE
D Q
DATA IN (XN)
C Q
30MHz
CLOCK

+5V +5V

ADR1 ADR2 SHADD SENBL ADR1 ADR2 SHADD SENBL

ADR0 VCC SENBH ADR0 VCC SENBH
9 26 9 26
DIN0-8 SUM0-25 DIN0-8 SUM0-25

DIENB DIENB

CLK HSP43891 CLK HSP43891

DF0 DF1
9x16 COEFF
CLK
RAM/ROM
Y0 A0
D0-D8
4-BIT Y1 A1 9 9 9 NC
CTR Y2 A2 CIN0-8 COUT0-8 CIN0-8 COUT0-8
Y3 A3
DCM1 RESET VSS DCM1 RESET VSS
RESET CIENB DCM0 ERASE COENB CIENB DCM0 ERASE COENB

SUM
OUT
(YN)
SYSTEM
RESET
FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC

10
 HSP43891

Extended FIR Filter Length Filter Cascade Configuration

lengths greater that eight taps can be created by either cas-
cading together multiple DF devices or ‘‘reusing’’ a single
device. Using multiple devices, an FIR filter of over 1000
taps can be constructed to operate at a 30MHz sample rate.
Using a single device clocked at 30MHz, an FIR filter of over
500 taps can be constructed to operate at less than a
30MHz sample rate. Combinations of these two techniques
are also possible.
To design a filter length L>8, L/8 DFs are cascaded by con-
necting the COUT0-8 outputs of the (i)th DF to the CIN0-8
inputs of the (i+1)th DF. The DIN0-8fs inputs and SUM0-25
outputs of all the DFs are also tied together. A specific exam-
ple of two cascaded DFs illustrates the technique (Figure 5).
Timing (Figure 6) is similar to the simple 8-tap FIR, except
the ERASE and SENBL/SENBH signals must be enabled
independently for the two DFs in order to clear the correct
accumulators and enable the SUM0-25 output signals at the
proper times.

TABLE 2.
DATA SEQUENCE INPUT X30 . . . X9, X8, X22 . . . X1, X0

COEFFICIENT SEQUENCE INPUT C0 . . . C14, C15, 0 . . . C0 . . . C14, C15 HSP43891 . . . 0, Y30 . . . Y23, 0. . . 0, Y22 . . . Y15, 0. . . 0

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR
6 C15 x X0 0 0 0 - - - - -
7 +C14 x X1 C15 x X1 0 0 - - - - -
8 +C13 x X2 C15 x X2 0 - - - - -
9 +C12 x X3 C15 x X3 - - - - -
10 +C11 x X4 +C14 x X4 C15 x X4 - - - -
11 +C10 x X5 +C13 x X5 C15 x X5 - - -
12 +C9 x X6 +C12 x X6 C15 x X6 - -
13 +C8 x X7 +C11 x X7 C15 x X7 -
14 +C7 x X8 +C10 x X8 +C14 x X8 -
15 +C6 x X9 +C9 x X9 +C13 x X9 -
16 +C5 x X10 +C8 x X10 +C12 x X10 -
17 +C4 x X11 +C7 x X11 +C11 x X11 -
18 +C3 x X12 +C6 x X12 +C10 x X12 -
19 +C2 x X13 +C5 x X13 +C9 x X13 -
20 +C1 x X14 +C4 x X14 +C8 x X14 -
21 +C0 x X15 +C3 x X15 +C7 x X15 Cell 0 (Y15)
22 0 C0 x X16 +C2 x X16 +C6 x X16 Cell 1 (Y16)
23 0 0 C0 x X17 +C1 x X17 +C5 x X17 Cell 2 (Y17)
24 0 0 0 +C0 x X18 +C4 x X18 Cell 3 (Y18)
25 0 0 0 0 C0 x X19 +C3 x X19 Cell 4 (Y19)
26 0 0 0 0 0 C0 x X20 +C2 x X20 Cell 5 (Y20)
27 0 0 0 0 0 0 C0 x X21 +C1 x X21 Cell 6 (Y21)
28 0 0 0 0 0 0 0 +C0 x X22 Cell 7 (Y22)
29 C15 x X8 0 0 0 0 0 0 0 -
30 +C14 x X9 +C15 x X9 0 0 0 0 0 0 -
31 +C13 x X10 +C15 x X10 0 0 0 0 0 -
32 +C12 x X11 +C15 x X11 0 0 0 0 -
33 +C11 x X12 +C15 x X12 0 0 0 -
34 +C10 x X13 +C15 x X12 0 0 -
35 +C9 x X14 +C15 x X14 0 -
36 +C8 x X15 C15 x X15 -
37 +C7 x X16 +C14 x X16 -
38 +C6 x X17 +C13 x X17 -
39 +C5 x X18 +C12 x X18 -
40 +C4 x X19 +C11 x X19 -
41 +C3 x X20 +C10 x X20 -
42 +C2 x X21 +C9 x X21 -
43 +C1 x X22 +C8 x X22 -
44 +C0 x X23 +C7 x X23 Cell 0 (Y23)
45 0 C0 x X23 +C6 x X24 Cell 1 (Y24)
46 0 0 C0 x X25 +C5 x X25 Cell 2 (Y25)
47 0 0 0 C0 x X26 +C4 x X26 Cell 3 (Y26)
48 0 0 0 0 C0 x X27 +C3 x X27 Cell 4 (Y27)

11
 HSP43891

Single DF Configuration
Using a single DF, a filter of length L>8 can be constructed
by processing in L/8 passes, as illustrated in Table 2, for a
16-tap FIR. Each pass is composed of Tp = 7 + L cycles and
computes eight output samples. In pass i, the sample with
indices i*8 to i*8 +(L-1) enter the DIN0-8 inputs. The coeffi-
cients C0 - CL - 1 enter the CIN0-8 inputs, followed by seven
zeros. As these zeros are entered, the result samples are
output and the accumulators reset. Initial filing of the pipeline
is not shown in this sequence table. Filter outputs can be put
through a FIFO to even out the sample rate.
Extended Coefficient and Data Sample
Word Size
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 9x9 and combine
these partial products by shifting and adding to obtain the
final result. The shifting and adding can be accomplished
with external adders (at full speed) or with the DF’s shift-and-
add mechanism contained in its output stage (at reduced
speed).
Decimation/Resampling
The HSP43891 DF provides a mechanism for decimating by
factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate-by-two
filter illustrates the technique (internal cell pipelining ignored
for simplicity). Detailed timing for a 30MHz input sample
rate, 15MHz output sample rate (i.e., decimate-by-two),
16-tap FIR filter, including pipelining, is shown in Figure 7.
This filter requires only a single HSP43891 DF.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CLK

RESET
DF0
ERASE
DF1
ERASE

DIN0-8 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37

CIN0-8 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10

CIENB

ADR0-2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

DF0
Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y31 Y32 Y33
SUM0-25
DF1
Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30
SUM0-25
SHADD
DF0
SENBL/H
DF1
SENBL/H

DCM0-1 0

15
YN = ∑ CK XN –K
K=0

FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s

12
 HSP43891
TABLE 3. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT
DATA SEQUENCE INPUT . . . X2, X1, X0

COEFFICIENT SEQUENCE INPUT . . . C15, C0 . . . C13, C14, C15 HSP43891 . . . Y19, - ,Y17, - , Y15

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR
6 C15 x X0 0 0 0 0 0 0 0 -
7 +C14 x X1 0 0 0 0 0 0 0 -
8 +C13 x X2 C15 x X2 0 0 0 0 0 0 -
9 +C12 x X3 +C14 x X3 0 0 0 0 0 0 -
10 +C11 x X4 +C13 x X4 C15 x X4 0 0 0 0 0 -
11 +C10 x X5 +C12 x X5 +C14 x X5 0 0 0 0 0 -
12 +C9 x X6 +C11 x X6 +C13 x X6 C15 x X6 0 0 0 0 -
13 +C8 x X7 +C10 x X7 +C12 x X7 +C14 x X7 0 0 0 0 -
14 +C7 x X8 +C9 x X8 +C11 x X8 +C13 x X8 C15 x X8 0 0 0 -
15 +C6 x X9 +C8 x X9 +C10 x X9 +C12 x X9 +C14 x X9 0 0 0 -
16 +C5 x X10 +C7 x X10 +C9 x X10 +C11 x X10 +C13 x X10 C15 x X10 0 0 -
17 +C4 x X11 +C6 x X11 +C8 x X11 +C10 x X11 +C12 x X11 +C14 x X11 0 0 -
18 +C3 x X12 +C5 x X12 +C7 x X12 +C9 x X12 +C11 x X12 +C13 x X12 C15 x X12 0 -
19 +C2 x X13 +C4 x X13 +C6 x X13 +C8 x X13 +C10 x X13 +C12 x X13 +C14 x X13 0 -
20 +C1 x X14 +C3 x X14 +C5 x X14 +C7 x X14 +C9 x X14 +C11 x X14 +C13 x X14 C15 x X14 -
21 +C0 x X15 +C2 x X15 +C4 x X15 +C6 x X15 +C8 x X15 +C10 x X15 +C12 x X15 +C14 x X15 Cell0 (Y15)
22 C15 x X16 +C1 x X16 +C3 x X16 +C5 x X16 +C7 x X16 +C9 x X16 +C11 x X16 +C13 x X16 -
23 +C14 x X17 +C0 x X17 +C2 x X17 +C4 x X17 +C6 x X17 +C8 x X17 +C10 x X17 +C12 x X17 Cell1 (Y17)
24 +C13 x X18 C15 x X18 +C1 x X18 +C3 x X18 +C5 x X18 +C7 x X18 +C9 x X18 +C11 x X18 -
25 +C12 x X19 +C14 x X19 +C0 x X19 +C2 x X19 +C4 x X19 +C6 x X19 +C8 x X19 +C10 x X19 Cell2 (Y19)
26 +C11 x X20 +C13 x X20 C15 x X20 +C1 x X20 +C3 x X20 +C5 x X20 +C7 x X20 +C9 x X20 -
27 +C10 x X21 +C12 x X21 +C14 x X21 +C0 x X21 +C2 x X21 +C4 x X21 +C6 x X21 +C8 x X21 Cell3 (Y21)
28 +C9 x X22 +C11 x X22 +C13 x X22 C15 x X22 +C1 x X22 +C3 x X22 +C5 x X22 +C7 x X22 -
29 +C8 x X23 +C10 x X23 +C12 x X23 +C14 x X23 +C0 x X23 +C2 x X23 +C4 x X23 +C6 x X23 Cell4 (Y23)
30 +C7 x X24 +C9 x X24 +C11 x X24 +C13 x X24 +C15 x X24 +C1 x X24 +C3 x X24 +C5 x X24 -
31 +C6 x X25 +C8 x X25 +C10 x X25 +C12 x X25 +C14 x X25 +C0 x X25 +C2 x X25 +C4 x X25 Cell5 (Y25)
32 +C5 x X26 +C7 x X26 +C9 x X26 +C11 x X26 +C13 x X26 +C15 x X26 +C1 x X26 +C3 x X26 -
33 +C4 x X27 +C6 x X27 +C8 x X27 +C10 x X27 +C12 x X27 +C14 x X27 +C0 x X27 +C2 x X27 Cell6 (Y27)
34 +C3 x X28 +C5 x X28 +C7 x X28 +C9 x X28 +C11 x X28 +C13 x X28 +C15 x X28 +C1 x X28 -
35 +C2 x X29 +C4 x X29 +C6 x X29 +C8 x X29 +C10 x X29 +C12 x X29 +C14 x X29 +C0 x X29 Cell7 (Y29)
36 +C1 x X30 +C3 x X30 +C5 x X30 +C7 x X30 +C9 x X30 +C11 x X30 +C13 x X30 C15 x X30 -
37 +C0 x X31 +C2 x X31 +C4 x X31 +C6 x X31 +C8 x X31 +C10 x X31 +C12 x X31 +C14 x X31 Cell8 (Y31)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CLK

RESET

ERASE

DIN0-8 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37

DIENB

CIN0-8 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10

CIENB

ADR0-2 0 1 2 3 4 5 6 7 0 1

DF0
Y15 Y17 Y19 Y21 Y23 Y25 Y27 Y29 Y31 Y33
SUM0-25

SHADD

SENBL

SENBH

DCM0-1 1

FIGURE 7. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT

13
 Specifications HSP43891

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) θJA θJC
Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to VCC +0.5V MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 47oC/W N/A
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37oC/W N/A
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.66oC/W 7.78oC/W
Junction Temperature Typical Package Power Dissipation at +70oC
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7W
CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2W
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.88W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17763
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to +70oC

DC Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Power Supply Current ICCOP VCC = Max, CLK Frequency 20MHz (Notes 1, 3) - 140 mA

Standby Power Supply Current ICCSB VCC = Max (Note 3) - 500 µA

Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 µA

Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 µA

Logical One Input Voltage VIH VCC = Max 2.0 - V

Logical Zero Input Voltage VIL VCC = Min - 0.8 V

Logical One Output Voltage VOH IOH = -400µA, VCC = Min 2.6 - V

Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.4 V

Clock Input High VIHC VCC = Max 3.0 - V

Clock Input Low VILC VCC = Min - 0.8 V

Input Capacitance PLCC CIN CLK Frequency 1MHz - 10 pF

All measurements referenced to GND, TA = 25oC
CPGA (Note 2) - 15 pF

Output Capacitance PLCC COUT - 10 pF

CPGA - 15 pF

NOTES:
1. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz.
2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
design changes.
3. Output load per test load circuit and CL = 40pF.

14
 Specifications HSP43891

AC Electrical Specifications VCC = 5V 5%, TA = 0oC to +70oC

-20 (20MHz) -25 (25.6MHz) -30 (30MHz)

TEST
PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX UNITS

Clock Period TCP 50 - 39 - 33 - ns

Clock Low TCL 20 - 16 - 13 - ns

Clock High TCH 20 - 16 - 13 - ns

Input Setup TIS 16 - 14 - 13 - ns

Input Hold TIH 0 - 0 - 0 - ns

CLK to Coefficient Output Delay TODC - 24 - 20 - 18 ns

Output Enable Delay TOED - 20 - 15 - 15 ns

Output Disable Delay TODD Note 1 - 20 - 15 - 15 ns

CLK to SUM Output Delay TODS - 27 - 25 - 21 ns

Output Rise TOR Note 1 - 6 - 6 - 6 ns

Output Fall TOF Note 1 - 6 - 6 - 6 ns

NOTE:
1. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or
design changes.

Test Load Circuit

S1
DUT

† CL

IOH ± 1.5V IOL

† INCLUDES STRAY AND

JIG CAPACITANCE
EQUIVALENT CIRCUIT

Switch S1 Open for ICCSB and ICCOP Tests

15
 HSP43891

Waveforms
4.0V
2.0V
CLK 0.0V
TCP TIS TIH
TCH TCL
3.0V
INPUT† 1.5V 1.5V
2.0V 2.0V 2.0V 0.0V
CLK

† Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET,

DCM0-1, ADR0-1, TCS, TCCI, SHADD

FIGURE 8. CLOCK AC PARAMETERS FIGURE 9. INPUT SETUP AND HOLD

2.0V
CLK 2.0
TODC, TODS 0.8
SUM0-25 TOF
TOR
COUT0-8 1.5V
OUTPUT

FIGURE 10. SUM0-25, COUT0-8, OUTPUT DELAYS FIGURE 11. RISE AND FALL TIMES

ENABLE 1.5V 1.5V

3.0V DEVICE
INPUT 1.5V UNDER 1.5V
TOED 0.0V TEST
TODD
1.7V
OUTPUT 1.5V AC Testing: Inputs are driven at 3.0V for a Logic “1” and 0.0V for a
1.3V Logic “0”. Input and output timing measurements are made at 1.5V
for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and mea-
sured at 2.0V.

FIGURE 12. OUTPUT ENABLE, DISABLE TIMING FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM

16
 HSP43891

Ceramic Pin Grid Array Packages (CPGA)

–A–
G85.A MIL-STD-1835 CMGA3-P85C (P-AC)
D 85 LEAD CERAMIC PIN GRID ARRAY PACKAGE
S1 D1 INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A 0.215 0.345 5.46 8.76 -
A1 0.070 0.145 1.78 3.68 3
b 0.016 0.0215 0.41 0.55 8
–B– b1 0.016 0.020 0.41 0.51 -
b2 0.042 0.058 1.07 1.47 4
S
C - 0.080 - 2.03 -
E1 E D 1.140 1.180 28.96 29.97 -
D1 1.000 BSC 25.4 BSC -
E 1.140 1.180 28.96 29.97 -
E1 1.000 BSC 25.4 BSC -
e 0.100 BSC 2.54 BSC 6
k 0.008 REF 0.20 REF -
L 0.120 0.140 3.05 3.56 -
Q 0.040 0.060 1.02 1.52 5
C
S S 0.000 BSC 0.00 BSC 10
INDEX CORNER b1
SEE NOTE 9 S1 0.003 - 0.08 - -
M 11 11 1
SEE
N - 121 - 121 2
NOTE 7
b Rev. 1 6/21/95
A SECTION B-B
0.008 C NOTES:
–C– SEATING PLANE 1. “M” represents the maximum pin matrix size.
AT STANDOFF
B 2. “N” represents the maximum allowable number of pins. Number
k
of pins and location of pins within the matrix is shown on the
B
A1
pinout listing in this data sheet.
3. Dimension “A1” includes the package body and Lid for both cav-
L ity-up and cavity-down configurations. This package is cavity up.
e b2 Dimension “A1” does not include heatsinks or other attached
features.
4. Standoffs are intrinsic and shall be located on the pin matrix di-
agonals. The seating plane is defined by the standoffs at dimen-
sions Q.
5. Dimension “Q” applies to cavity-up configurations only.
Q 6. All pins shall be on the 0.100 inch grid.
SECTION A-A 7. Datum C is the plane of pin to package interface for both cavity
b up and down configurations.
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
A A Ø0.030 M C A M B M
have a radius or chamfer.
Ø0.010 M C
9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique.
10. Dimension “S” is measured with respect to datums A and B.
L
11. Dimensioning and tolerancing per ANSI Y14.5M-1982.
A1
12. Controlling dimension: INCH.
Q

17
 HSP43891

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)
0.048 (1.22)
0.042 (1.07) N84.1.15 (JEDEC MS-018AF ISSUE A)
0.056 (1.42) 0.004 (0.10) C
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.050 (1.27) TP 0.025 (0.64)
R INCHES MILLIMETERS
C 0.045 (1.14)
L SYMBOL MIN MAX MIN MAX NOTES
A 0.165 0.180 4.20 4.57 -
A1 0.090 0.120 2.29 3.04 -
D2/E2
D 1.185 1.195 30.10 30.35 -
C
L
E1 E D1 1.150 1.158 29.21 29.41 3
D2 0.541 0.569 13.75 14.45 4, 5
D2/E2
E 1.185 1.195 30.10 30.35 -
VIEW “A”
E1 1.150 1.158 29.21 29.41 3

0.020 (0.51) E2 0.541 0.569 13.75 14.45 4, 5

D1
MIN N 84 84 6
A1
D A Rev. 1 3/95
0.020 (0.51) MAX -C- SEATING
PLANE
3 PLCS 0.026 (0.66)
0.032 (0.81) 0.013 (0.33)
0.021 (0.53)

0.025 (0.64)
0.045 (1.14) MIN
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allow-
able mold protrusion is 0.010 inch (0.25mm) per side.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.

18
 HSP43891

Metric Plastic Quad Flatpack Packages (MQFP)

Q100.14x20 (JEDEC MO-108CC-1 ISSUE A)
D 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
INCHES MILLIMETERS
-D-
SYMBOL MIN MAX MIN MAX NOTES
A - 0.134 - 3.40 -
A1 0.010 - 0.25 - -
A2 0.100 0.120 2.55 3.05 -

-A- -B- B 0.009 0.015 0.22 0.38 6

B1 0.009 0.013 0.22 0.33 -
E E1
D 0.904 0.923 22.95 23.45 3
D1 0.783 0.791 19.90 20.10 4, 5
E 0.667 0.687 16.95 17.45 3
E1 0.547 0.555 13.90 14.10 4, 5
e L 0.026 0.037 0.65 0.95 -
N 100 100 7
PIN 1 e 0.026 BSC 0.65 BSC -
ND 30 30 -
SEATING
-H- PLANE NE 20 20 -
A
Rev. 0 1/94
0.10
0.004 NOTES:
-C-
5o-16o 1. Controlling dimension: MILLIMETER. Converted inch
0.40 0.12 dimensions are not necessarily exact.
0.016 MIN 0.005 M C
A-B S D S
2. All dimensions and tolerances per ANSI Y14.5M-1982.
0o MIN B
A2 A1
3. Dimensions D and E to be determined at seating plane -C- .
B1 4. Dimensions D1 and E1 to be determined at datum plane -H- .
0o-7o
5. Dimensions D1 and E1 do not include mold protrusion.
0.13/0.17
Allowable protrusion is 0.25mm (0.010 inch) per side.
5o-16o 0.005/0.007
L 6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
BASE METAL
WITH PLATING 7. “N” is the number of terminal positions.
0.13/0.23
0.005/0.009

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