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Codigos - Prac 1 - Diseño - Logico
Codigos - Prac 1 - Diseño - Logico
Codigos - Prac 1 - Diseño - Logico
entity comp_and is
f: out bit);
end comp_and;
Para la arquitectura
is Begin
F<= a and b;
end comp_and_arch;
entity comp_or is
f: out bit);
end comp_or;
Para la arquitectura
begin
F<= a or b;
end comp_or_arch;
entity comp_not is
f: out bit);
end comp_not;
Para la arquitectura
begin
F<= not a ;
end comp_not_arch;
entity comp_buffer is
f: out bit);
end comp_buffer;
Para la arquitectura
begin
F<= a ;
end comp_buffer_arch;
ii) Empleando el postulado when – else, diseñe en VHDL las compuertas derivadas
(NAND, NOR, XOR y XNOR).
entity comp_nand is
f: out bit);
end comp_and;
Para la arquitectura
begin
end comp_nand_arch;
entity comp_nor is
f: out bit);
end comp_nor;
Para la arquitectura
begin
end comp_nor_arch;
entity comp_xor is
port (a, b: in bit;
f: out bit);
end comp_and;
Para la arquitectura
begin
end comp_xor_arch;
entity comp_xnor is
f: out bit);
end comp_xnor;
Para la arquitectura
begin
end comp_xnor_arch;
entity comp_xor is
f: out bit);
end comp_xor;
Para la
arquitectura
architecture
comp_xor_arch of
comp_xor is begin
comp_xor_arch;
entity comp_xnor is
n
b
end comp_xnor;
Para la arquitectura
architecture comp_xnor_arch
of comp_xnor is begin
F<= (A and B) or
(not A and not B); end
comp_xnor_arch;
Bibliografía
EcuRed. (s. f.). Electrónica digital - EcuRed. Recuperado 22 de julio de 2022, de
https://www.ecured.cu/Electr%C3%B3nica_digital
Las Compuertas Lógicas y sus Operaciones Lógicas (AND, OR, NOT, NAND, NOR,
XOR, XNOR). (s. f.). Logicbus S.A. de C.V. Recuperado 22 de julio de 2022, de
https://www.logicbus.com.mx/compuertas-logicas.php