Adithyan J | Résumé

Ernakulam – Kerala,India
H +917025961866 • B adithyanj642@gmail.com

Summary
A person with an objective to gain knowledge , enhance career and to gain professionalism within the
VLSI industry by executing challenging duties continuously by learning new skills, and by debugging
the issues that are critical in the project. Also I love this job and like to learn new things each day.

Core Competency
{ Independent execution of block level and top level physical design and signoff.
{ Two years of enriched experience in Physical Design in latest technology node of 3nm with
multi-million gate design tape outs.
{ Excellent hands-on Experience and complete understanding in various aspects of ASIC Design
flow.
{ Experience in Static Timing Analysis in Primetime and worked on 7 tapeouts with timing closure.
{ Experience in Synthesis in DC Compiler, Fusion Compiler, Genus tools.
{ Strong debug and problem solving skills for Timing closures, EMIR, Low power verifications ,LEC,
Electrostatic discharge analysis , LVS, DRC and layout issues.
{ Well versed in TCL scripting with good understanding of Verilog Programming. Have worked
along with RTL design team in Spyglass in one of the project.
{ Good hands-on experience on tools such as Synopsis IC-Compiler II, Fusion compiler, Innovus
, Synopsis FEV ,PrimeTime, Cadence Conformal, Design Compiler, Library Compiler, Library
Manager, Cadence Virtuoso, Synopsis VC LP, Synopsis RV, Synopsis RVSC , PERC , Calibre,
Intel Caliber.

Key Achievements
{ Worked in 7 tape-out production chips from netlist handoff to GDS tape out including place and
route, clock tree synthesis, timing closure and signoff checks.
{ With exceptional scripting skills worked as a part of Intel team for providing scripts based on
Project Requirements and has given scripts to other programs as an advisory.

Work Experience
{ 2 years of work experience as Physical Design Engineer at Tech Mahindra Cerium Limited in
Kochi , Kerala .
{ 1 year experience as EMIR engineer at Tech Mahindra Cerium Limited in Kochi , Kerala.
{ 6 months parallel experience as Analog Design Engineer at Tech Mahindra Cerium Limited in
Kochi , Kerala
{ 8 months parallel experience as RTL Design Engineer at Tech Mahindra Cerium Limited in
Kochi , Kerala

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Education
Grade 11,12
Amrita Vidyalayam, 2015–2017
Distinction
Bachelor of Technology in Electronics and Communication
Mar Athanasius College of Engineering, 2017–2021
Distinction
BSC in Computer Application
Government School,
Distinction, Part time 2022
Course in Solar Panel Installation and Design
ASAP Kerala Govt, 2021
Distinction, Part time

Projects
{ Project 1 - Project Name : Dual Tone Multi Frequency (DTMF)
Responsible for the PNR with synoff of 28nm block where DFT was inserted.

Technology : 28nm with 9 routing layers

Roles/Responsibilities:
- Operated logical physical synthesis upon both DFT inserted and non - DFT inserted RTL.
- Several iterations conducted and examined with macro placement by following floorplan
guidelines
- Developed a power distribution structure and ring around specific macros
- Implemented standard cell placement , blockage creation and analyzed congestion, cell density
pin density
- Single point CTS has performed by properly following NDR’s
- On evaluating the congestion map, multiple partial routing blockages had been introduced to
reduce the congestion on specific metal layers
- Performed CTS and optimized it to meet timing skew requirements
- The partition was critical with respect to transition capacitance violations, some trials were
carried out to fix those issues
- In sign off stage, some manual fixes were tried out for better timing closure
- DRC fixes done by manual routing, macro relocation and removing via overlapping

{ Project 2 - PNR flow of a 28nm block

Description: Assisted PNR flows and signoff such as low power verification and timing closure.
Done signal routing with shielding,

Tools:
Fusion Compiler,VC LP, PrimeTime.

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{ Project 3 - ECO closure and manual routing of a 7nm block
Description: Done manual routing for 3 blocks using manual method and also using scripts (45
degree routing ,90 degree routing , step routing). Responsible for EMIR,Logical Equivalent Check
(LEC),Low Power Verification signoff in this project

Tools:
Fusion Compiler, PrimeTime.

Roles/Challenges:
- Block Internal IR fixing by using different methods such as spreading clustered group of cells,
downsizing cells, cell moments, via insertions. Block Internal EM fixing by NDR, routing in
higher metal layers and by breaking the nets.
- Cleared all the DRV’s and DRC’s, Timing, Shorts and opens in the design.
- Responsible for the manual routing of three blocks and has cleared the shorts and opens of the
blocks.

{ Project 4 - Ownership of Low power Verification ,LEC ,EMIR closure of a 3nm block and the top
level VCLP , FEV ,EMIR.
Handled the PNR of a 3nm block. DRC fixes of two blocks

Description: For a block with 2 Macros, 18 metal layers , responsible for block level ECO
closure and for a block with 1 macro and 18 metal layer , Done the PNR for the block. In the
top level with 3 macro and hpml as c4 have done the VCLP,FEV,EMIR closure.

Tools: Fusion Compiler, VCLP,Formality, RedHawk SC.

Roles/Challenges:

- The Challenges faced in this block was with congestion, Huge DRV’s and congestion.
- There was no resource available for EMIR in RVSC tool since it is a new high advanced tool.

{ Project 5 - Advisory to a 7nm project

Given advice to a project while waiting for the new project. Worked here for 1month. Helped the
team and took ownership for setting up the environment of signoffs and ran EMIR for the first
time in the project after writing pgmap ,plocs for 8 blocks and the top level.

Roles/Challenges:
- For a block with clock frequency 2Ghz ,5 macros, 811 ports , act as an advisory for reducing
congestion floorplanning and setting up the flow issues.
- For top level was responsible for EMIR runs, cleared the violation and was the owner of the top
level and block level EMIR

{ Project 6 - PnR to ECO closure of a 3nm full chip design.

Roles:Top level PNR, BUMP planning ,design planning, RDL routing and also curently working in

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 designing 8 custom blocks with its signoff’s

Working as RTL Design Engineer in this project and analysing the code using SpyGlass.

Description:

For the top level with 25 Macros, 18 metal layers and 32157 IO ports, 2.6 Ghz clock fre-
quency, responsible for full chip synthesis to signoff. Worked in generating library from netlist
using the Silicon Smart tool.

Tools:
Fusion Compiler, Virtuoso, Innovus, PrimeTime, Library Manager, Library Compiler, Spyglass,
Calibre, Design Compiler,Silicon Smart, Formality, Duet, FIELD.

Roles/Challenges:
- Responsible for converging the top level design from Netlist to GDS.
- Wrote the UPF
- Responsible for developing SDC from scratch for top level.
- Responsible for creating many flow files since the cheetah flow crashed in the project.
- Responsible for closure of all the signoff checks such as DRC’s, DRV’s, timing, sanity checks
and low power checks.
- With minimal supervision was responsible to analyze and generate timing fixes for all the
partitions based on the top level primetime runs.

{ Project 7 - EMIR advisory in 7nm project, clock frequency 2Ghz, 24 blocks.

Roles: Analysing the Dynamic IR, Rescheck, Static IR, Tide, Sigem, Pgem, Post thermal
power,Post thermal signal,Thermal. So currently in two projects.

Tools:Redhawk, Totem, Redhawk SC,Fusion Compiler, Innovus.

SCRIPTING PROJECTS:
Part of Client team for providing scripts based on Project requirements. Few of them are:
- Script for placing BUMPS
- Script which edits the Cheetah flow of the Client.
- Script to place 32157ports in the full chip design according to the design specification
- Script for port up of the Bumps.
- Script for doing the manual routing with shielding
- Script for making the library which was not having timing models.
- Script for dumping ndm’s from lef,lib, converting lib to db on large scales.

Hobbies
Plays Chess
Trinity grade 5 certified Keyboard Player.
Love to gain new informations each day by reading books, watching videos.

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