Logic Design

Chap – 07: Latches and Flip-Flops

Dr. Muhammad Hanif

Combinational vs Sequential Circuit
• Combinational:
• Time independent
• Output depends only on current input status
• No feedback required
• Faster and better in performance
• Elementary building blocks are logic gates
• Used for arithmetic and Boolean operations.
• Sequential:
• Output depends on present as well as past inputs (sequence )
• Output of previous input is transferred as feedback with input for next output
generation.
• Comparatively slower and has low performance
• Building blocks are flip flops
• Mainly used for data storing
Sequential Circuits
• Sequential logic circuits can be divided into three main categories:
• 1. Event Driven – asynchronous circuits that change state
immediately when enabled.
• 2. Clock Driven – synchronous circuits that are synchronised to a
specific clock signal.
• 3. Pulse Driven – which is a combination of the two that responds to
triggering pulses.
Memory Elements
• A memory stores data – usually one bit per element
• A snapshot of the memory is called the state
• A one bit memory is often called a bistable, i.e., it has 2 stable
internal states
• Flip-flops and latches are particular implementations of bistables
Memory Elements
• Latches and flip-flops are the basic elements for storing information.
• One latch or flip-flop can store one bit of information.
• Latches change output when inputs change, depends on enable
signal
• Flip-flops change the output either at rising or falling clock edge.
• There are basically four main types of latches and flip-flops:
• SR, D, JK, and T.
• The major differences in these flip-flop types are the number of
inputs they have and how they change state
Sequential Circuits: Latches
A latch is a temporary storage device that has two stable states (bistable).
It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type.
It can be constructed from NOR gates or NAND gates.
With NOR gates, the latch responds to active-HIGH inputs; with NAND gates, it responds to
active-LOW inputs.
SR Latches
• An active low SR latch is a type of latch which is SET when S = 0(LOW).
• An active low SR latch is typically designed by using NAND gates.
• The logical circuit for a SR latch is shown below.
SR Latches
• Active Low:
SR Latches
• Active High:
• An active high SR latch is a type of latch which is SET when S = 1(HIGH).
• An active high SR latch is typically designed by using NOR gates.
• The logical circuit for a SR latch is shown below.
SR Latches
SR Latches
• Active High:
Time Signal
• Until now: we have essentially ignored the issue of time

• We have assumed that our digital logic circuits perform their

computations instantaneously

• Our digital logic circuits have been “stateless”

– Once you present a new input, they forget everything about
previous inputs
Time Signal
• In reality, time is an important issue:

• Even our logic gates induce a small amount of delay (on the order of a
few nanoseconds)

For much of what we do – we actually want our circuits to have some

form of memory
Time Signal
Time Signal
Latches
SR Latches
• Example:
Case-1: S’=R’=1 (S=R=0)
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.
Case-2: S’=0, R’=1 (S=1, R=0)
As S’=0, the output of 1st NAND gate, Q = 1 (SET state).
In 2nd NAND gate, as Q and R’ inputs are 1, Q’=0.
Case-3: S’= 1, R’= 0 (S=0, R=1)
As R’=0, the output of 2nd NAND gate, Q’ = 1.
In 1st NAND gate, as Q and S’ inputs are 1, Q=0 (RESET state).
Case-4: S’= R’= 0 (S=R=1)
When S=R=1, both Q and Q’ becomes 1 which is not allowed.
So, the input condition is prohibited.
SR Latches
SR Latches
• NOR Gate representation: Active High
SR Latches
• Clear-Set Flip Flop:
SR Latch :Time Signal
SR Latch :Time Signal
SR Latch :Time Signal
SR Latch :Time Signal
SR Latch :Time Signal
SR Latch: System Clock
• For the RS latch, the output state change directly in response to
changes in the inputs.
This is called asynchronous operation
• Sequential circuits currently employ the notion of synchronous
operation, the output is constrained to change only at a time
specified by an enabling signal.
• This signal is generally known as the system clock
SR Latch: System Clock
• The Clock:
– Typically it is a square wave signal at a particular frequency
– It imposes order on the state changes
– Allows lots of states to update simultaneously

• How can we modify an asynchronous circuit to act synchronously,

i.e., in synchronism with a clock signal?
SR Latch: System Clock
• The RS Latch with output state only permitted to change when a valid
enable signal is present
• This is achieved by introducing a couple of AND gates in cascade with
the R and S inputs that are controlled by an additional input known as
the enable (EN) input.
Gated Latch

A gated latch is a variation on the basic latch.

The gated latch has an additional

input, called enable (EN) that must
be HIGH in order for the latch to
respond to the S and R inputs.
Gated Latch
D-latch
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:

D Q
Q

EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.
D-Latch

The truth table for the D latch summarizes its operation.

If EN is LOW, then there is no change in the output and it
is latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
D-Latch

Determine the Q output for the D latch, given the Q

inputs shown.

D
Q
EN

Notice that the Enable is not active during these times, so

the output is latched.
Flip-Flops
• Flip-flops are synchronous bistable devices  output changes state
only at a specified point (leading or trailing edge) on the triggering
input called the clock (CLK)
• Flip-flops are edge-triggered or edge-sensitive whereas gated
latches are level-sensitive.
Flip-Flops
Flip-flops
A flip-flop differs from a latch in the manner it changes states.
A flip-flop is a clocked device, in which only the clock edge determines when a
new bit is entered.
The active edge can be positive or negative.
D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
D-Flip Flop
• D flip flop very popular with digital electronics.
• They are commonly used for counters and shift-registers and input
synchronisation.
• The output can be only changed at the clock edge, and if the input
changes at other times, the output will be unaffected.
D Flip-flops

The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you
that it is sensitive to its D input only on the rising edge of the clock; otherwise it is
latched.
The truth table for a negative-edge triggered D flip-flop is identical except for the
direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

J-K Flip-flops
• The J-K flip-flop is more versatile than the D flip flop.
In addition to the clock input, it has two inputs,
labeled J and K. When both J and K = 1, the output
changes states (toggles) on the active clock edge (in
this case, the rising edge).

• The two control

inputs are labeled J
and K in honor of
Jack Kilby, who
invented the
integrated circuit.
J-K Flip-flops

Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle
JK Flip Flop