This document provides an overview of the CS2323: Computer Architecture course offered from Aug-Nov 2023. The course will be taught by Rajesh Kedia and include topics like instruction set architecture, processor design, caches/memory systems, and emerging trends. Students will complete assembly programming and C/C++ lab exercises. Evaluation will include quizzes, assignments, exams and participation. The course will meet for 3 hours per week and additional support will be provided through the instructor's contact hours and an online discussion forum. Suggested textbooks are also listed.
This document provides an overview of the CS2323: Computer Architecture course offered from Aug-Nov 2023. The course will be taught by Rajesh Kedia and include topics like instruction set architecture, processor design, caches/memory systems, and emerging trends. Students will complete assembly programming and C/C++ lab exercises. Evaluation will include quizzes, assignments, exams and participation. The course will meet for 3 hours per week and additional support will be provided through the instructor's contact hours and an online discussion forum. Suggested textbooks are also listed.
This document provides an overview of the CS2323: Computer Architecture course offered from Aug-Nov 2023. The course will be taught by Rajesh Kedia and include topics like instruction set architecture, processor design, caches/memory systems, and emerging trends. Students will complete assembly programming and C/C++ lab exercises. Evaluation will include quizzes, assignments, exams and participation. The course will meet for 3 hours per week and additional support will be provided through the instructor's contact hours and an online discussion forum. Suggested textbooks are also listed.
Pre-requisites • Introduction to programming (ID1063/ID1303) • Digital systems (concept of multiplexers, decoders, registers, etc.) • Introduction to Data Structures (CS1353)
Rajesh Kedia, CSE IITH, 2023
Course Outline • Introduction to computer architecture, overall system components, OS and compilers, multiprocessors, trends, design objectives, etc. • Instruction set architecture, assembly program, translation from C to assembly • Processor design – Basic processor components, instruction encoding, building a processor, improving performance through pipelining and other techniques • Caches and memory systems – cache hierarchy, various cache configurations, etc. • Interfacing I/O devices • Computer arithmetic – addition, multiplication, division, etc. • Emerging research trends
Rajesh Kedia, CSE IITH, 2023
Lab Exercises • Assembly language coding in a simulator: • Understanding various instructions • Assembly code development for common mathematical functions • Might involve using a real hardware board
Evaluation (tentative and can change) • In-class short quizzes (about 5): 12 • Homework: 5 • Lab assignments: 20 • Lab exam/quiz: 13 • Exam-1 (just before semester break): 15 • Exam-2 (in the last week of Nov): 30 • Class participation (including forum discussions and attendance): 5 • Total: 100
Rajesh Kedia, CSE IITH, 2023
Administrivia • Course credits: 3 • Instructor: Rajesh Kedia • Course webpage: Check link on https://people.iith.ac.in/rkedia • Lecture schedule: 3 hours a week, P slot (Mon 2.30-3.55 pm, Thu 4.00-5.25 pm), A-LH2 • Instructor contact hours: Just after the lectures or by appointment • Lab venue: B524. Schedule: To be announced • Learn yourself and help others: discussion forum • Only selected slides will be shared. Encouraged to read textbook • Moodle: Self-marking attendance, quizzes, assignment submission, discussion forum, etc. • Academic honesty MUST be followed
Rajesh Kedia, CSE IITH, 2023
References • Computer Organization and Design, The Hardware/Software Interface (RISC-V edition) by David A. Patterson and John L. Hennessy • The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213 • Digital Design and Computer Architecture (RISC-V edition), By David Harris and Sarah Harris • Basic Computer Architecture (also available as Computer organization and architecture), version 2.1, By Smruti Ranjan Sarangi