Professional Documents
Culture Documents
04 Compaction
04 Compaction
Layout Compaction
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 1
Design Rules
http://en.wikipedia.org/wiki/Design_rule_checking
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 2
1
Design Rules
Design rules: restrictions on Patterns and design rules are
the mask patterns to increase expressed in either nanometers
the probability of successful or integer multiples of ‘gridsize’
fabrication. λ. The types of the most common
Compromise between design rules:
Density minimum-width rules (a)
Yield minimum-separation rules (b, c, d)
Ease of use minimum-overlap rules (e)
(a)
(c)
(b) (d)
(e)
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 3
3
1
5
Illustration only
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 4
2
More DR Examples (Intra-layer)
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 5
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 6
3
Symbolic Layout
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 7
Metal 3
metal 2
metal 1
poly
n-diff
p-diff
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 8
4
Invertor Schematic, Stick Diagram, Layout.
VDD
VDD
VDD
in
In Out In Out
out
VSS
VSS
VSS
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 9
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 10
5
Aspects of Compaction
Dimension:
1-dimensional (1D): layout elements only move or
shrink in one dimension (x or y). Often sequentially
performed first in the x-dimension and then in the
y-dimension (or vice versa).
2-dimensional (2D): layout elements move and
shrink simultaneously in two dimensions.
Complexity:
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 11
1D Compaction: X Followed by Y
C B A C B A C
D D D A
I H I H I H
E F G E F G E F G
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 12
6
1D Compaction: X Followed by Y
C B A
D C A C A
B B
I H D H D H
I I
E F G E F G E F G
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 13
2D Compaction
C B A
D C B A
I H D I H
E F G E F G
(a) (f)
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 14
7
Comparison C
C B A
B
D D A
I H
I H
F E F G
E G x then y
orig
(a) (c)
C B A
C A
B
D I H
D H
I
E F G
E F G y then x 2D
(e) (f)
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 15
x5 x6 x3 x4
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 16
8
The Constraint Graph
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 17
0
x1 x2 v1 a v2 b a
v0 0 v5 v3 v4
v6 b
a
x5 x6 x3 x4
Example rules
All widths ≥ a
All spacings ≥ b
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 18
9
Maximum-Distance Constraints
xj − xi ≤ cij
⇔
xi − xj ≥ − cij.
Consequence for the
constraint graph: backward
edge
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 19
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 20
10
Longest-Path Algorithm for DAGs
longest-path(G) main ()
for (i 1; i n; i i 1) for (i 0; i n; i i 1)
pi "in-degree of i "; xi 0;
Q 0 ; longest-path(G);
while (Q )
i "any element from Q";
Q Q i ;
for each j "such that" i j E // for each outgoing edge
xj max x j xi di j ; // set max distance for xj
pj p j 1;
if (p j 0) // if all incoming edges have been processed
Q Q j ; // can process its outgoing edges
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 21
v3
1
v2
1
5
2
v4
v0
1
4
v1
2 v5
Q p1 p2 p3 p4 p5 x1 x2 x3 x4 x5
"notinitialized" 1 2 1 2 1 0 0 0 0 0
0 0 1 1 2 1 1 5 0 0 0
1 0 0 1 2 0 1 5 0 0 3
2 5 0 0 0 1 0 1 5 6 6 3
3 5 0 0 0 1 0 1 5 6 6 3
5 0 0 0 0 0 1 5 6 7 3
4 0 0 0 0 0 1 5 6 7 3
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 22
11
Longest-Path Algorithm for DAGs
longest-path(G) main ()
for (i 1; i n; i i 1) for (i 0; i n; i i 1)
pi "in-degree of i "; xi 0;
Q 0 ; longest-path(G);
while (Q )
i "any element from Q";
Q Q i ;
for each j "such that" i j E
xj max x j xi di j ;
pj p j 1;
if (p j 0) Q: What is the worst-case time
Q Q complexity of this algorithm?
j ;
A: O(|E|)
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 23
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 24
12
The Liao-Wong Algorithm (1)
Main ideas:
Split the edge set E of the constraint graph into two subsets:
forward edges Ef :related to minimum-distance constraints,
backward edges Eb:related to maximum-distance constraints.
The graph G(V, Ef) is acyclic; the minimum distance for each
vertex can be computed with the procedure ‘‘longest-path’’.
Repeat until convergence:
update minimum distances by processing the edges from Eb.
call ‘‘longest-path’’ for G(V, Ef).
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 25
do flag 0;
longest-path( G f );
for each i j Eb
if (x j x i di j )
xj xi di j ; // backward edge reduces distance
flag 1; // not yet converged
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 26
13
The Liao-Wong Algorithm (3).
v3
v2 1 Step x1 x2 x3 x4 x5
-1 Initialize
1
5
Forward1 1 5 6 7 3
2 v4 Backward1 2 5 6 7 3
v0 -3
1 Forward2 2 5 6 8 4
4 -4 Backward2 2 5 7 8 4
v1
2 Forward3 2 5 7 8 4
v5 Backward3 2 5 7 8 4
S1 S2 ;
// swap wavefront
S2 ;
count count + 1; // counter to detect positive loops
if (count n)
error("positi ve cycle");
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 28
14
v3
v2 1
-1
1
5
2 v4
v0 -3
1
4 -4
v1
2
v5 x1 x2 + (-3)
S1 x1 x2 x3 x4 x5
"notinitialized"
0 1 5
1 2 2 5 6 6 3
1 3 4 5 2 5 6 7 4
4 5 2 5 6 8 4
4 2 5 7 8 4
3 2 5 7 8 4
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 29
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 30
15
Longest and Shortest Paths
Longest paths become shortest paths and vice versa
when edge weights are multiplied by –1.
Situation in DAGs: both the longest and shortest path
problems can be solved in linear time.
Situation in cyclic directed graphs:
+ All weights are positive: shortest-path problem in P
(Dijkstra), longest-path problem is NP-complete.
+ All weights are negative: longest-path problem in P
(Dijkstra), shortest-path problem is NP-complete.
+ No positive cycles: longest-path problem is in P
+ No negative cycles: shortest-path problem is in P.
+ Otherwise: problem is NP-complete.
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 31
Remarks Constraint-Graph
Compaction
The algorithms mentioned only compute the left-most
position for each layout element. All elements outside
the critical paths also have a right-most position. It is
interesting to find the best position within this interval
with respect to some cost function.
(a) (b)
A method to reduce complexity is hierarchical compaction.
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 32
16
Constraint Generation
The constraint graph is not directly available after
layout design. It must be computed.
The set of constraints should be irredundant (why?)
and generated efficiently.
B
C
Redundant constraint
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 33
Features:
1D method.
All layout elements are associated to horizontal and vertical
grid lines.
Initially the distance between grid lines is unspecified.
The distance between two subsequent grid lines is
computed by taking the maximum separation imposed by
pairs of elements on different grid lines.
Disadvantage: rigid as elements initially located on one line
always remain aligned.
ET 4255 - Electronic Design Automation 2009 © Nick van der Meijs 3/6/2009 34
17