This document provides a quick reference for VHDL concepts including:
1. It describes the basic structure of a VHDL design using entities, architectures, and libraries to define modular blocks.
2. It explains that an entity defines the input/output of a design block, while an architecture provides the implementation using RTL code or structural code.
3. It outlines that a structural architecture connects lower level components using component declarations, signal declarations, and component instances to define connectivity.
This document provides a quick reference for VHDL concepts including:
1. It describes the basic structure of a VHDL design using entities, architectures, and libraries to define modular blocks.
2. It explains that an entity defines the input/output of a design block, while an architecture provides the implementation using RTL code or structural code.
3. It outlines that a structural architecture connects lower level components using component declarations, signal declarations, and component instances to define connectivity.
This document provides a quick reference for VHDL concepts including:
1. It describes the basic structure of a VHDL design using entities, architectures, and libraries to define modular blocks.
2. It explains that an entity defines the input/output of a design block, while an architecture provides the implementation using RTL code or structural code.
3. It outlines that a structural architecture connects lower level components using component declarations, signal declarations, and component instances to define connectivity.
This document provides a quick reference for VHDL concepts including:
1. It describes the basic structure of a VHDL design using entities, architectures, and libraries to define modular blocks.
2. It explains that an entity defines the input/output of a design block, while an architecture provides the implementation using RTL code or structural code.
3. It outlines that a structural architecture connects lower level components using component declarations, signal declarations, and component instances to define connectivity.
Structural code connects lower levels of a design. Structural code has three pieces: component 6. Common Synthesizable Types Type / Abbreviation std_logic / sl Value UX01ZWLH - Package 1164 VHDL Training Experts declarations, signal declarations, and component std_logic_vector / slv array of std_logic 1164 instances (creates the connectivity). signed / sv array of std_logic ns, sla architecture Structural of MuxReg is unsigned / uv array of std_logic ns, sla VHDL Quick Reference -- Component Declarations boolean / bool integer / int (False, True) 31 31 -(2 - 1) to 2 - 1 std std component Mux8x2 port ( natural / int0+ 0 to 231 - 1 std 1. VHDL Designs Sel : In std_logic ; line access string textio A design is partitioned in to a modular blocks. Each I0, I1 : In unsigned(7 downto 0); Enumerated type StateType is (S0, S1, S2, S3) ; block in the design is created with an entity and Y : Out unsigned(7 downto 0) ); 7. Assigning Values architecture. Each block is coded in a separate file. end component ; A_sl <= '1' ; -- Character literal Each entity and architecture is compiled into a library. component Reg8 B_slv <= "1111" ; -- string literal Entity names within a library must be unique. The port ( C_slv <= X"F"; -- hex. 4 bits per character architecture statement repeats the entity name, so the Clk : In std_logic ; E_slv <= (others => '1') ; -- aggregate architecture name typically indicates the type of code it D : In unsigned(7 downto 0); L_int <= 15 ; -- universal integer contains: RTL, structural, or testbench. Q : Out unsigned(7 downto 0) M_int <= 16#F# ; -- base literal (16 = base) ); N_bool <= TRUE ; -- boolean only true or false 2. Entity = IO of a Design end component ; 8. VHDL Operators library ieee ; -- Signal Declarations Logic and, or, nand, nor, xor, xnor use ieee.std_logic_1164.all ; signal Mux : unsigned(7 downto 0); Comp =, /=, <, <=, >, >= entity MuxReg is begin Shift sll, srl, sla, sra, rol, ror port ( -- Component Instantiations Add +, - Clk : In std_logic ; -- Named Association Sign +, - Sel : In std_logic ; Mux8x2_1 : Mux8x2 Mult *, /, mod, rem A : In std_logic_vector(7 downto 0); port map ( Misc **, abs, not, and, or, nand, nor, xor, xnor B : In std_logic_vector(7 downto 0); Sel => Sel, Y : Out std_logic_vector(7 downto 0) I0 => A, Precedence increases from logic to misc. Underlined ); I1 => B, items are VHDL-2008. end MuxReg ; Y => Mux 9. Concurrent Statements ); Concurrent statements are coded in the architecture. 3. RTL Architecture = Implementation -- Positional Association RTL code creates hardware and/or logic. RTL code Reg8_1 : Reg8 9.1 Signal Assignments contains assignments and process statements. Expression is evaluated immediately. Value is assigned port map (Clk, Mux, Y); architecture RTL of MuxReg is one delta cycle later. end Structural ; -- Declarations 9.2 Simple Assignment =logic and/or wires signal Mux: 5. Common Packages Z <= AddReg ; std_logic_vector(7 downto 0); Usage Abbr. Source Sel <= SelA and SelB ; use std.standard.all ; -- * std IEEE YL <= A(6 downto 0) & '0'; --Shift Lt begin YR <= '0' & A(7 downto 1); --Shift Rt ieee.std_logic_1164.all ; 1164 IEEE -- Code use ieee.numeric_std.all ; ns IEEE SR <= SI_sl & A(7 downto 1); --Shift In Mux <= A when (Sel = '0') else B ; use ieee.numeric_std_unsigned.all; nsu IEEE 9.3 Conditional Assignment use ieee.std_logic_arith.all ; sla Shareware RegisterProc : process (Clk) Mux2 <= use ieee.std_logic_unsigned.all ; slu Shareware begin A when (Sel1 = '1' and Sel2 = '1') use std.textio.all ; textio IEEE if rising_edge(Clk) then else B or C ; use ieee.std_logic_textio.all ; - Shareware Y <= Mux ; ZeroDet <= '1' when Cnt = 0 else '0'; end if ; VHDL-2008 adds packages for fixed and floating point. end process ; The conditional expression must be boolean. Also see libraries work and std are implicitly referenced the if statement. end RTL ; * package std.standard is implicitly referenced