Fall 1999 EE 8223 Analog IC Design Page 52

Matching Errors in MOSFET Current Mirrors

Good layout design is essential for circuits needed matched devices.
Layout techniques are effectively used to minimize first-order mismatch
errors due to variations in these process parameters: gate-oxide thickness,
lateral diffusion, oxide encroachment, and oxide charge density.
Considering only the effects of threshold voltage mismatch within the
simple current mirror, its current ratio is described by
( )
( )
( )
( )
2
2
2
2
1
2
1
2
1
5 . 0
5 . 0
1
]
1

+
1
]
1

THN GS
THN
THN GS
THN
THN THN GS
THN THN GS
D
o
V V
V
V V
V
V V V
V V V
I
I

( )
THN GS
THN
D
o
V V
V
I
I

2
1
1
for SI saturation operation if a symmetric distribution in threshold voltage
across the circuit is assumed (i.e., V
THN1
= V
THN
0.5V
THN
and V
THN2
= V
THN
+ 0.5V
THN
). Note the dependence on V
GS
. A reduction in V
GS
increases the
input/output error in current mirrors induced by threshold voltage mismatch.
Considering only transconductance parameter mismatch,
n
n
D
o
KP
KP
I
I
+ 1
1
where the value of KP
n
is the average transconductance parameter between
the two transistors within the simple current mirror.
Considering only V
DS
and effects,
( )
( )
1
1
2
2
1
1
1
DS m c
DS m c
D
o
V
V
I
I


+ +
+ +
[SI sat.]
Fall 1999 EE 8223 Analog IC Design Page 53
These, too, can be a significant source of error (e.g., 11%! if V
DS1
= 2V, V
DS2
= 4V, (
c
+
m
)
1
= 0.05V
-1
, and (
c
+
m
)
1
= 0.04V
-1
).
Good layout practices for analog circuits include the following:
1) Use gate lengths several times larger than the technologys minimum
gate length if all possible. This helps reduces effects while
improving matching.
2) Use multiple source/drain contacts along the width of the transistor to
reduce parasitic resistance and provides evenly distributed current
through the device.
3) Interdigitize large aspect ratio devices to reduce source/drain
depletion capacitance. Using an even number (n) of gate fingers can
reduce C
db
, C
sb
by one-half or (n + 2)/2n depending on source/drain
designation. Typically it is preferred to reduce drain capacitance
more so than source capacitance. Also use dummy poly strips to
minimize mismatch induced by etch undercutting during fab.
Fall 1999 EE 8223 Analog IC Design Page 54
4) Matched devices should have identical orientation. An example of
what not to do is shown below.
5) Interdigitization can be used in a multiple transistor circuit layout to
distribute process gradients across the circuit. This improves
matching.
6) Use common-centroid structures.
Fall 1999 EE 8223 Analog IC Design Page 55
Other Current Sources/Sinks or Mirrors
Negative feedback is an effective technique for providing enhanced output
impedance for current sources and sinks. Two circuits that demonstrate this
are the Wilson current mirror and the regulated cascode.
Negative feedback action within the Wilson current sink Suppose V
o
increases while I
D1
is constant. Then I
D4
would increase causing V
GS3
(=
V
GS2
) to increase which in turn tries to force I
D2
to increase. But if I
D1
is
constant, then the voltage at node A must decrease since I
D2
= I
D1
(V
DS2
must
decrease to accommodate increasing V
GS2
while under constant current
conditions). As a result, V
GS4
would decrease, thus stabilizing I
D4
.
The Wilson current sinks output resistance is given by
( ) ( )
1
1
]
1

,
_

,
_

+
1
1
]
1

,
_

+
3
3
4 3
3 4 2 1 2
3
3 4 4
1
||
1 1
|| || 1
1
|| 1
m
o
o m
o mb o o m
m
o m o
t
t
out
g
r
r g
r g r r g
g
r g r
i
v
R
( )
1
1
]
1

,
_

+ +
3 4 3
4 2 1 2 4
1 1
|| 1
m o m
mb o o m o out
g r g
g r r g r R

,
_

+
2
2
2
o
m o out
r
g r R
The small-signal analysis for obtaining this result included the application of
Ohms Law (Eq. 20.42), KVL (Eq. 20.43), and KCL (Eq. 20.44).
Fall 1999 EE 8223 Analog IC Design Page 56
The output voltage requirements for the Wilson current sink is described by
4 4 3 , 4 3 min , THN GS GS sat DS GS o
V V V V V V + +
Alternately, in terms of output current,
4
3
3
min ,
2 2

o
THN
o
o
I
V
I
V + +
Hence, increasing I
o
causes V
o,min
to increase by twice the square root of I
o
if

3
=
4
. This is an unattractive characteristic of the Wilson current sink.
The regulated cascode current sinks negative feedback is as follows.
Observe that V
SG1
and V
GS3
are constant (DC bias voltages). If I
o
attempts to
increase, the voltage at node A will rise, inducing an increase in I
D2
. Then
the voltage at node B must decrease since I
D1
is constant. This reduction in
V
GS4
counters any increase in I
o
. Subsequently, I
o
is stabilized.
The regulated cascode current sinks output resistance is given by
( ) ( )
1
]
1

+ + + +
4
3
3 4 2 1 2 3 4 4
|| 1 1
o
o
o mb o o m o m o
t
t
out
r
r
r g r r g r g r
i
v
R
( )
2
||
3 2
4 3 2 1 4 2
o m
o o o o m m out
r g
r r r r g g R
10s of G to 100s of G of output resistance can be readily achieved!
Fall 1999 EE 8223 Analog IC Design Page 57
The output voltage requirement of the regulated cascode to maintain
maximum output resistance is given by
( )
4
, 2 min , sat DS GS o
V V V +
An example of a simple regulated cascode current mirror is shown below.
Unfortunately, this implementation does not provide V
DS1
= V
DS3
, resulting in
current mismatch.
The implementation shown below, however, provides improved current
matching since (by design) V
DS1
= V
DS3
(when all the transistors are
matched).
Fall 1999 EE 8223 Analog IC Design Page 58
The wide-swing cascode current mirror provides an output resistance of
approximately g
m
r
o
2
and an output voltage requirement of only 2V
DS,sat
(2V).
A practical implementation of this current mirror is shown below.