3T-1R Analog Write and Digital Read of MRAM for RNG and Low
Power Memory Application
Thomas Egler1,2, Hans Dittmann1,2 , Sunanda Thunder1and Artur Useinov1*
1National Chiao Tung University, 1001 University Rd., Hsinchu 30010, Taiwan, ∗Email: artu@nctu.edu.tw
2Reutlingen University, 50 Oferdinger Str., Reutlingen 72768, Germany
Abstract — This work represents integration of MTJ with 30nm
FinFET for low voltage analog write operations and readout
optimization for the p-bit or true random number generator
(TRNG), where the induced p-bit, the probabilistic state of the
magnetic tunnel junction (MTJ), is detected within only a single
computational period. The period contains two sub-cycles: write
and joined read & reset cycles. The operation with MTJ
becomes stochastic, independent after calibrating at the desired
working point against the factors, which can induce the signal
deviations, e.g. temperature, material degradation or external
magnetic field.
Index Terms — FinFET, magnetic tunnel junctions, stochastic
switching, true random number generators, p-bit, spin logic, IoT
device.
I. INTRODUCTION
In the present work, we improve and reconsider the
approaches for READ and WRITE operations, suggested in
[1]–[5],[7], using MATLAB and SPICE simulations. A novel
write technique has been realized here with 3 FinFET
structure using a single word line and read operation with a
single read line. The developed approach considers the
general case of asymmetric MTJ [6]. In this paper, we have
shown the Spice simulation result of MTJ for optimizing the
peripheral devices and have the effects of peripheral devices
on the MTJ operations.
II. WRITE OPERATION
The write circuit and the pulses has been depicted in Fig 1
has been explained in the Fig 2. The word line is connected to
an inverter circuit as shown in the Fig.1. The suggested
writing scheme is it contains only one line, as the main
advantage, which makes it suitable for crossbar memory
array implementation. We have adopted the BSIM-CMG [8]
and ASU MRAM model [7] to predict the switching features
with varying gate length (Lg) and width (TFin). Fig 3 and Fig 4
represent AP to P switching where, we found the best
combination is TFin=10nm and Lg=20nm. The switching delay
and ION, IOFF ratio in Fig 5 proves our conclusion. The
propagation delay in ‘0’ to ‘1’ bit state is 3.5ns, while it takes
3ns for the reverse operation, where the delay in [7] was 5ns
and 7ns. Fig 5 and Fig 8 shows switching performance of
MTJ with varying dimensions of the FinFET. Here we have
tried to optimize the peripheral device dimensions for MTJ
and found that FinFET with dimensions T Fin=10nm and
Lg=20nm are the most viable combination in terms of power
consumptions and delay.
III. READ OPERATION
To produce a random binary code a full cycle of the switching
can be reduced down to two sub-cycles, Fig 10. The MTJ starts
at AP state (a) and can be switched or not at (b); at phase (c)
the signal becomes detected after the write cycle with the
probability P ≈ 0.5. During the read and reset cycle a reverse
current is applied, which causes the state either to switch back
from P to AP or let it stay in AP. In the end of the cycle the
state will be reset to AP for the next write cycle, phase (d) in
Fig 9. Along the read and reset sub-cycles, the voltage of the
represented voltage divider of the MTJ-cell with “Read and
Reset” FINFETs is determined at a measuring point by the full
bridge, Fig 9. The measured voltage (Vm) depends on the state
of the MTJ at the sensing pin.. In case of the MTJ is pinned at
the read and reset cycle from P to AP, a voltage reduction at
the measuring point is observed and detected in similar way as
in [3]. This voltage deviation is amplified by an inverting
comparator. The signal output of the comparator is detected by
the delay flip-flop (DFF): P to AP switching can be indicated
as digital ”1”, otherwise, the output of the DFF determined as
digital ”0”.
IV. CONCLUSION
As a result, in this work, the concept of TRNG with two sub-
cycles per period have been developed. The optimized MTJ-
based model of TRNG includes four FinFETs connected as a
full bridge via MTJ cell. Calibration procedure is suggested
to tune the amplitude of the current pulse, which have to
provide the equal probability for both MTJ states taking into
account the MTJ asymmetry or signal deviations within
lifetime. The model can be used in applications for a
computational memory concepts, providing longer electronic
lifetime. One of the benefits of the developed technique is the
increased amount of true random numbers per time by the
cause of restricted number of logical cycles.
REFERENCES
[1] “Implementing p-bits with embedded MTJ,” S.Dutta et al.
[2] “A novel circuit design of true random number generator using
magnetic tun- nel junction,”Y.Wang et al.
[3] Y. Qu et al “A true random number generator based on parallel
STT-MTJs,”
[4] “A magnetic tunnel junction based true random number gen-
erator with conditional perturb and real-time output probability
tracking,” W. Ho Choi et al.
[5] I. Chakraborty, A. Agrawal, K. Roy, “Design of a low-voltage
analog- to-digital converter using voltage-controlled stochastic
switching of low barrier nanomagnets,” IEEE Magn. Lett., vol.
9, 3103905, May 2018.
[6] A. Useinov, and J. Kosel, “Spin asymmetry calculations of the
TMR- V curves in single and double-barrier magnetic tunnel
junctions,” IEEE Trans. on Magn., vol. 47, no. 10, pp.
2724-2727, Oct. 2011.
[7] Z. Xu, C. Yang, M. Mao, K. B. Sutaria, C. Chakrabarti, Y. Cao,
“Compact modeling of STT-MTJ devices,” Solid-State
Electronics, vol. 102, pp. 76-81, December 2014.
[8] “A Multi-Gate CMOS compact model-BSIM-MG” Darsen Lu et al.
 TFin = 10nm TFin = 40nm
2.0 L=20nm
2.0
L=30nm

MTJ Current (mA) Resistance (k)

1.8 1.8 L=40nm

1.6 1.6
Increasing switching speed
1.4 1.4
Increasing switching speed
1.2 1.2

1.0 1.0
0.0 0.2 0.4 0.0 0.2 0.4
(a) (b)
0.20 0.20

0.15 0.15
IOFF Increase in ION /IOFF
0.10 0.10

0.05 0.05 IOFF

Increase in ION /IOFF
0.00 0.00
0.0 0.2 0.4 0.0 0.2 0.4
(c) Time (ns) (d)

Fig 1: Write Circuit for MTJ Fig 2: Simulation Setup Fig 3: Anti-Parallel to Parallel Transition-I
(Switching dynamics variation with Lg)

2.0
L = 20nm L = 40nm T=40nm
2.0 L = 20nm L = 40nm
Switching Time (ns)

T=10nm
Resistance (k)

1.8
1.8 0.7 2.0 2.0

Resistance (K)
1.6
0.6 Increasing
1.8 switching 1.8 Increasing
Increasing 1.6 Increasing
0.5 switching
Switching Speed 1.6 speed 1.6
1.4 Switching Speed 1.4 0.4 speed
1.4 1.4
1.2 1.2 0.3
0.2 1.2 1.2
1.0
1.0 0.1 1.0 1.0
0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5
(b) 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
(a) 20 25 30 35 40
0.20 0.10 (a) (b) TFin=10nm
MTJ Current (mA)

4
Tfin=10nm 1.8x10 -0.2
TFin=20nm

MTJ Current (mA)

0.08 -0.2 TFin=30nm
Tfin=20nm
0.15 -0.4
ION / IOFF

Increase in ION / IOFF Tfin=30nm -0.4 TFin=40nm

0.06 4 -0.6
Tfin=40nm 1.2x10 -0.6
0.10 -0.8
0.04 IOFF -1.0 -0.8
0.05 IOFF 6.0x10
3
-1.2 -1.0
0.02 -1.4 -1.2
Almost same ION -1.6
0.00 0.00 0.0 -1.4
0.0 0.1 0.2 0.3 0.4 0.5 -1.8
0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8
20 25 30 35 40 0.0 0.2 0.4 0.6 0.8
(c) (d) (c) (d)
Time (ns) Gate Length (nm) Time (ns)

Fig 4: Anti-Parallel to Parallel Transition-II Fig 5: Delay and ION/IOFF vs Lg Fig 6: Parallel to Anti-Parallel Transition-I
(Switching dynamics variation with TFin) (Switching dynamics variation with TFin)

TFin = 10nm TFin = 40nm

T=40nm
2.0 2.0 Increasing
Resistance (K)

T=10nm
1.8 1.8 switching
speed 0.08
1.6 Increasing 1.6 L=20nm
Switching Time (ps)

switching L=30nm
1.4 speed 1.4 0.07
L=40nm
1.2 1.2
1.0 1.0 0.06
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
(a) (b)
-0.2 0.05
MTJ Current (mA)

-0.2
-0.4
-0.4
-0.6
-0.6 -0.8 0.04
-0.8 -1.0
-1.2
-1.0 0.03
-1.4
-1.2 -1.6
-1.4 -1.8 20 25 30 35 40
0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6
(c) (d)
Time (ns) Gate Length (nm)

Fig 7: Parallel to Anti-Parallel Transition-II Fig 8: Delay vs Lg Fig 9: Read Circuit: MTJ based model of
(Switching dynamics variation with Lg) the computational block of TRNG. The signal
direction is taken from right to left. DFF signal
represents the output which generate p-bits.

Fig 10: Current through the MTJ during the whole period.