A Low-power Capacitance Measurement Circuit with
High Resolution and High Degree of Linearity
M. R. Haider+, M. R. Mahfouz, S. K. Islam, S. A. Eliza, W. Qu and E. Pritchard
The University of Tennessee, Knoxville, TN 37996-2100, USA
E-mail: +mhaider@utk.edu
Abstract— This paper has presented a low-power capacitance
read-out circuit which could be used for biomedical sensor
applications. The differential structure of the system eliminates
even order distortion. The entire system manifests two current
sense amplifiers, two diode rectifiers and one instrumentation
amplifier. The circuit has been realized using TSMC 0.35 μm
bulk CMOS process. The circuit operates with a 3 V power
supply and consumes 5.384 mW of power. Simulation results
show that the circuit has a sensitivity of 1.32 mV for 1 fF
capacitance change. Measurement results for different
capacitance variations demonstrate a change of 10.8 mV for 8.8
fF variation.
Key-words— low-power, capacitance measurement, read-out circuit
I. INTRODUCTION
Recent technological advances in integrated circuit
technologies and micro- and nano- fabrication processes have
led to the development of miniature, light weight and cost
effective sensors for various applications. Each sensor element
produces a change which could be easily converted to a
current or voltage signal. Any change in electrical signal
depends upon the variation of environmental quantity. Usually
sensors are classified depending upon the changes they made
based on any external variations. Among the various types of
sensors, capacitive sensors are getting more and more
attention because of their high resolution and better noise
immunity. Differential capacitance transducers are widely
used for detecting numerous physical quantities such as
pressure difference, linear displacement, rotational angles, etc.
Since capacitive sensors are becoming more and more
popular, many methods have been developed for the detection
of capacitance changes such as switched-capacitor (SC),
analog-to-digital (A/D) [1], capacitance-to-frequency (C/F)
[2] and capacitance-to-phase conversion 0. Switched-
capacitor structures are best suited for CMOS realization but
they are not capable of handling capacitance changes with
frequencies higher than 10 Hz [4] and they suffer seriously
from clock feed-through. Because of this clock feed-through,
the attainable resolution is estimated to be 1 fF [5]. Again,
instead of charge sensing across the capacitive transducer,
sensing the current flowing through the sensors or transducers
978-1-4244-2167-1/08/$25.00 ©2008 IEEE
provides the high speed and dynamic measurement of
transducer data [5],[6].
High resolution capacitance measurement requires the
precise circuit design and careful layout of the system. Most
of the time, track capacitances are in the range of aF or fF and
they can easily overwhelm the circuit performance. Leakage
current is another problem whenever designing a circuit using
bulk CMOS process. In this work, we have used N-well
shield to isolate the noisy substrate from the sensitive input
signal tracks. Bottom plates of each capacitor are also
shielded to eliminate any noise coupling from the substrate.
Finally, we have used our custom designed high gain Op-
Amp and instrumentation amplifier to achieve high sensitivity
of the circuit.
In this paper, we have demonstrated a low-power
capacitance read-out circuit with high resolution and high
degree of linearity. The circuit consists of two current sense
amplifiers, two diode rectifiers and one instrumentation
amplifier. The differential structure of the system eliminates
even order distortion. An excitation signal is provided at the
common terminal of the differential sensor structure.
Depending upon the sensor variation, different currents flow
through the sensor elements. This flow of charge is then
detected and amplified by the use of current sense amplifier.
The signal is then filtered through the diode rectifier to make
it a DC signal and finally the differential signal is fed to the
input of an instrumentation amplifier. The gain control
resistor of the instrumentation amplifier provides the option
of dynamic range extension.
II. CAPACITANCE READ-OUT CIRCUIT
The entire system manifests two current sense amplifiers,
two diode rectifiers and one instrumentation amplifier.
Fig 1 shows the schematic of the developed system. The
working principle of the system is explained in the
following paragraphs.
261
 Figure 1: Schematic of Sensor Read-out Circuit

A. Working Principle
The capacitance read-out circuit is designed for
differential measurement of any capacitance variation from
any capacitive transducer whose nominal value is in the range
of 5 pF. For single-ended measurement, an additional
capacitor of nominal value 5 pF as a reference. Thus two
capacitors (one ‘sensing’ capacitor and the other ‘reference’
capacitor) are arranged in a manner that one of their plates
becomes a common terminal for both the capacitors (Fig 2).
The other two terminals (terminal ‘1’ and terminal ‘2’ in Fig Figure 2: Differential Structure of Capacitive Transducer.
2) are connected to the inverting terminals of two Op-Amps
as shown in Fig 1. The non-inverting terminals of both the The generated currents are then fed to two current sense
Op-Amos are shorted and connected to a reference voltage amplifiers. Each amplifier consists of one Op-Amp and one
which is almost at the middle point of the input common feed-back capacitor C f . The resistor R f is used in parallel
mode range (ICMR) of the two Op-Amps.
with C f to set the bias point of the output of each current
An excitation signal V = Vamp ⋅ cos(ωt + ϕ ) is injected sense amplifier (Fig 3).
at the common terminal of two capacitors. Based on the
capacitance variation, two different current signals are 1
generated. If the nominal value of reference and sensing
If the frequency of excitation ω >> then the
Cf Rf
capacitors is expressed as C, then the currents flowing
through the reference and sensing capacitors can be written as transfer function of the current sense amplifier can be
follows expressed as [7]

dVamp C1
ir = C ⋅ (1) H (ω ) ≈ − (3)
dt Cf
dVamp
i s = (C ± ΔC ) ⋅ (2) where C1 and C f are the input and feed-back capacitors
dt
of the current sense amplifier.
where v is the amplitude of the excitation signal and
ΔC is the variation of sensing capacitor.

262
 Figure 3: Schematic of Current Sense Amplifier
Now using equation (3), the output voltages due to Figure 4: Schematic of Instrumentation Amplifier
reference capacitor and sensing capacitor can be denoted as
⎛ 2R ⎞
C Vout = ⎜1 + ⎟ ⋅ Vdiff (8)
Vout , r =− ⋅V (4) ⎜ R ⎟
Cf ⎝ g ⎠

and
Now, inserting the value of Vdiff from equation (7) into
Vout , s = −
(C ± ΔC ) ⋅ V (5) equation (8), we get the final output of the read-out circuit
Cf
⎛ 2 R ⎞ ⎛ ΔC ⎞
From equation (4) and (5), it is obvious that the Vout = ⎜1 + ⎟⋅⎜∓ ⋅ α ⋅ Vamp ⎟ (9)
⎜ R g ⎟⎠ ⎜⎝ C f ⎟
capacitance variation modulates the amplitude of the ⎝ ⎠
excitation signal. These two output signals are then passed
through a diode rectifier. Here, a PMOS diode is used From equation (9), it is evident that the gain of the
because of its lower flicker noise compared to the NMOS instrumentation amplifier and hence the sensitivity of the
counterpart. The values R1 and C1 are chosen in such a way system can be increased by decreasing the value of Rg. The
sensitivity of the circuit can also be increased by decreasing
that the time-constant τ = R1C1 satisfy the following the value of feed-back capacitor Cf , but in that case we need
condition to increase the frequency of excitation signal to satisfy the
condition for equation (3). Again, too small value of Cf may
1 1 be affected by the parasitic capacitances of capacitor plates.
<τ < (6)
f exc fs
III. LAYOUT, SIMULATION AND TEST RESULTS
The entire system has been designed, simulated and
where f exc and f s are the frequency of excitation signal and fabricated using TSMC 0.35 μm 2-poly 4-metal bulk CMOS
the frequency of variation of sensing capacitor, respectively. process. The circuit consumes only (1 mm X 1 mm) 1mm2 of
The differential output of these two diode rectifiers therefore area without pad. Fig 5 shows the microphotograph of the
can be expressed as fabricated chip.
ΔC The entire system has been designed and simulated using
Vdiff = ∓ ⋅ α ⋅ Vamp (7)
Cf

where α is the attenuation factor due to the diode rectifier.

The outputs of the two diode rectifiers are then fed into an
instrumentation amplifier which senses the differential
change of these two outputs as expressed in equation (7).

The instrumentation amplifier consists of three op-amps,

six fixed resistors and one variable resistor or gain control
resistor as shown in Fig. 4. The transfer function of the
instrumentation amplifier can be expressed as Figure 5: Microphotograph of Fabricated Chip

263
 DC_Value Linear (DC_Value)

1.35
1.3

DC Output (Volt)
1.25
1.2 R2 = 0.9982

1.15
1.1
0 1E-12 2E-12 3E-12 4E-12
Capacitance Variation (F)

Figure 6: DC Output for Different Capacitance Values Figure 8: Measured DC Output for Different Capacitance Variation

Cadence SpectreTM simulator. The designed Op-Amp used in

the current sense amplifier and in the instrumentation
amplifier, has a gain of 83 dB and operates with a 3 V power
supply. The excitation was chosen to be a sinusoidal signal of
amplitude 400 mV (p-p) and of frequency 400 KHz. The
entire read-out circuit consumes 5.384 mW of power when
operated with a 3 V supply.
Fig 6 shows the simulated DC output of the developed
system for different capacitance values. Fig 7 represents the
sensitivity of the system. From fig 7, it is expected that the
read-out circuit is capable of generating 1.32 mV for 1 fF
variation and the system has highly linear performance with
corresponding R-squared value close to unity. For calibration
of the read-out circuit, different known values surface mount
capacitors are arranged on a PCB and the corresponding DC
output is measured from the designed circuit. Fig 8 shows the
measured DC value for different capacitance variation. The
best fit linear curve has also been shown in fig 8 with
corresponding R-squared value of 0.9982. The slope of the
linear curve represents a sensitivity of 10.8 mV for 8.8 fF
variation that closely matches the simulated one.
1.265
R2 = 0.9999
1.26
1.255
DC Output (Volt )
IV. CONCLUSION AND FUTURE WORK
In this paper, we have demonstrated a low-power
capacitance measurement circuit with high sensitivity and
high degree of linearity. The entire circuit consumes 5.384
mW of power and shows high degree of linearity with R-
squared value equal to 0.9982. Simulation result indicates that
the capacitance read-out circuit can generate 1 mV DC output
for 1 fF capacitance variation. Future work includes
integrating the capacitance measurement circuit with a
capacitive transducer and validates the performance of the
system with real-world data.
REFERENCES
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1.25
[5] K. Mochizuki, T. Masuda, and K. Watanabe, “An interface circuit for
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Figure 7: Simulated Sensitivity of the Read-out Circuit

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