A B C D E

1 1

2 Compal Confidential 2

Schematic Document
Cantiga + ICH9
2008 / 12 / 10 Rev:1.0
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 1 of 45
hexainf@hotmail.com A B C D E
GRATIS - FOR FREE
 A B C D E

Compal confidential
File Name : LA-4841P
MLK 14
ZZZ1

Thermal Sensor Penryn -4MB (Socket P)

PCB
1
ADT7421ARMZ 1

P.4 uFCPGA-478 CPU

P.4,5,6 CK505 TSSOP-64
Clock Generator
Fan conn ICS9LPRS397AKLFT
P.4 H_A#(3..35)
CRT FSB
H_D#(0..63) 667/800MHz 1.05V
P.17 P.15
DDR2 667/800MHz 1.8V DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 P.13,14

LVDS Panel Interface Intel Cantiga MCH

Dual Channel
P.16 MXM II VGA/B 1329pin BGA
NB9M-GS 512M
P.33 P.7,8,9,10,11,12
USB conn x 4
P.30
2 2

CardBus Controller PCI DMI X4 C-Link

O2MICRO OZH24
P.26
USB2.0

Intel ICH9-M Azalia

BT Conn
1394 Media Card P.30

PCI-E BUS 676pin BGA SATA Master

SATA Slave
P.18,19,20,21 Camera
P.30

10/100/1000 LAN Mini-CardX1 Mini-CardX1 Express Card Express Card

REALTEK P.22 (WLAN)
P.27
P.27
RTL8111C-GR P.24 P.24
3 3
Mini-Card-3 P.23

RJ45/11 CONN
LPC BUS

Audio CODEC AMP & Audio Jack

ALC272 P.25 P.25
ENE KB926
P.28
SATA HDD Connector
P.23
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT.
P.29 P.29 P.28
CDROM Conn.
4
P.23 4

DC/DC Interface CKT. RTC CKT.

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/1/15 2008/1/15 Title
Power Circuit DC/DC Power OK CKT. Issued Date Deciphered Date
Block diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 2 of 45
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

Symbol Note :
+5VS
+3VS
+1.5VS
: means Digital Ground
power
plane +0.9V
+VCCP
+5VALW +1.8V +CPU_CORE : means Analog Ground
+B
+3VALW +VGA_CORE
@ : means just reserve , no build
DEBUG@ : means just reserve for debug.
+2.5VS
State +1.8VS
+1.2VS
+0.9VGA

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
V V V
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X X
V
LCD_CLK
LCD_DAT Cantiga
X X X X X X X

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
hexainf@hotmail.com Date: Monday, December 15, 2008 Sheet 3 of 45
A

GRATIS - FOR FREE

 5 4 3 2 1

No need in check list +3VS

XDP_DBRESET# 1 2 1K_0402_5%
@ R51
+VCCP

XDP_TDI R5 1 2 54.9_0402_1%

XDP_TMS R4 1 2 54.9_0402_1%
D D

XDP_TRST# R11 1 2 54.9_0402_1%

XDP_TCK R35 1 2 54.9_0402_1%

CONN@ This shall place near CPU

7 H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 7

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# 19
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# 7 C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# +3VS
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4 Thermal Sensor EMC1402-1-ACZL-TR
XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1

0.1U_0402_16V4Z
H_A#25 T5 AC5 XDP_TCK 1
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 C13
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 XDP_TRST# 2
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# U2
A[30]# DBR# XDP_DBRESET# 20
H_A#31 V4 1 8 EC_SMB_CK2 EC_SMB_CK2 29,33
H_A#32 A[31]# VDD SCLK
W3 A[32]#
H_A#33 AA4 THERMAL H_THERMDA 2 7 EC_SMB_DA2
A[33]# D+ SDATA EC_SMB_DA2 29,33
H_A#34 AB2 H_PROCHOT# R146 2 1 56_0402_5% +VCCP C5
H_A#35 A[34]# H_THERMDC
AA3 A[35]# PROCHOT# D21 1 2 3 D- ALERT# 6
H_ADSTB#1 V1 A24 H_THERMDA_R R57 1 2 100_0402_5% H_THERMDA 2200P_0402_50V7K
7 H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R53 1 2 100_0402_5% H_THERMDC L_THERM# 4 5
H_A20M# THERMDC THERM# GND
19 H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# R16

19 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 7,19
H_IGNNE# C4 +3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P
19 H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together, 10K_0402_5%
19 H_STPCLK#
H_STPCLK# D5 STPCLK#
Address:100_1100
19 H_INTR
H_INTR C6 H CLK Trace width / Spacing = 10 / 10 mil
H_NMI LINT0 CLK_CPU_BCLK
19 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 15
H_SMI# A3 A21 CLK_CPU_BCLK#
19 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15
C76
M4
N5
RSVD[01] FAN Control circuit 10U_1206_16V4Z~N
2 1
RSVD[02] +5VS
T2 RSVD[03]
B C88 B
V3 RSVD[04]
RESERVED

B2 1000P_0402_50V7K~N 1 2
RSVD[05] C77 10U_1206_16V4Z~N
D2 RSVD[06] 2 1
D22 RSVD[07]
D3 U3
RSVD[08]
F6 RSVD[09] 1 VEN GND 8
2 VIN GND 7
FAN1_POWER 3 6
EN_DFAN1 VO GND
29 EN_DFAN1 4 VSET GND 5

Penryn +3VS RT9027BPS SO 8P

1
JFAN1
R61
40mil
1 1
+VCCP 10K_0402_5% 2 2
3 3

2
29 FAN_SPEED1 4 GND
1

@ 2 5
R17 GND
56_0402_5% C94 ACES_85205-03001
0.01U_0402_16V7K CONN@
1
2 2

FAN1
B
E

H_PROCHOT# 3 1 OCP#
OCP# 20
C

@ Q2
MMBT3904_SOT23

+VCCP
A A
2

R18
56_0402_5%
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
7 H_D#[0..15] CONN@ CONN@
H_D#[32..47] 7
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
7 H_DSTBN#1
H_DSTBN#1
H_DSTBP#1
L26
M26
DSTBN[1]# DSTBN[3]# AE25
AF24
H_DSTBN#3
H_DSTBP#3
H_DSTBN#3 7 E15
E17
VCC[038] VCCP[04] K6
M6
1 Check 220u?
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] + C10
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R7
V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R52 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6 0814 Change to 220uF
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6 0819 Change to C_D2E
T3 TEST4 VCC[046] VCCP[12]
No need in T4
TEST5 AF1 TEST5 DPRSTP# E5 H_DPRSTP#
H_DPRSTP# 7,19,43
R23 R24 R25 R26 F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
check list T5 TEST6 DPSLP# H_DPSLP# 19 VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
15 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 19 VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
15 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
15 CPU_BSEL2 BSEL[2] PSI# H_PSI# 43 VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]
To IMVP

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 43
AA15 VCC[056] VID[1] AF5 CPU_VID1 43 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 43
AA18 AF4 C12 C11
VCC[058] VID[3] CPU_VID3 43
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU AA20 VCC[059] VID[4] AE3 CPU_VID4 43 2 2
Resistor placed within AB9 VCC[060] VID[5] AF3 CPU_VID5 43
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 43
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE 43
AB15 VCC[065] Near pin B26
toggling signal. AB17 VCC[066] No stuff 27.4 pull down near IMVP for testing
AB18 AE7 VSSSENSE
COMP[0,2] trace width is VCC[067] VSSSENSE VSSSENSE 43
166 0 1 1
B 18 mils. COMP[1,3] trace Penryn B

width is 4 For 8 layer condition

.

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
For 6 layer
+CPU_CORE
1K_0402_1%
Z=27.4 ohm
2

V_CPU_GTLREF
VCCSENSE, VSSSENSE/ 14mils (MS), R28 1 2 100_0402_1% VCCSENSE
16mils (SL) width, 7mils space, 25mils
1

space to other signals Mismatch =25mils.

R29 R30 1 2 100_0402_1% VSSSENSE
2K_0402_1%
2

Close to CPU pin AD26

Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 5 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.

+CPU_CORE Place these caps inside

the CPU socket.
D Place these caps inside D
1 1 1 1 1 1 1 1 1 ( Left side on Top ).
CONN@
JCPU1D
the CPU socket cavity. C202 C529 C232 C255 C505 C504 C254 C257 C214
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A4 VSS[001] VSS[082] P6 ( Left side on Top ). 2 2 2 2 2 2 2 2 2
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
B6
B8
VSS[009] VSS[090] T4
T23
+CPU_CORE Place these caps inside
VSS[010] VSS[091]
B11 VSS[011] VSS[092] T26 the CPU socket.
B13 VSS[012] VSS[093] U3 Place these caps inside
B16 VSS[013] VSS[094] U6 1 1 1 1 1 1 1 1 1 1 ( Right side on Top ).
B19 VSS[014] VSS[095] U21 the CPU socket cavity. C162 C197 C252 C190 C203 C200 C161 C199 C208 C226
B21 VSS[015] VSS[096] U24
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B24 VSS[016] VSS[097] V2 ( Right side on Top side). 2 2 2 2 2 2 2 2 2 2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
+CPU_CORE
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4
D8
VSS[027] VSS[108] Y24
AA2
Place these caps inside 1 1 1 1 1 1
VSS[028] VSS[109]
C
D11 VSS[029] VSS[110] AA5 the CPU socket cavity. C501
10U_0805_6.3V6M
C508
10U_0805_6.3V6M
C514
10U_0805_6.3V6M
C519
10U_0805_6.3V6M
C522
10U_0805_6.3V6M
C533
10U_0805_6.3V6M C
D13 VSS[030] VSS[111] AA8
2 2 2 2 2 2
D16 VSS[031] VSS[112] AA11 ( Left side on Bottom ).
D19 VSS[032] VSS[113] AA14
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
+CPU_CORE
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21
E24
VSS[042] VSS[123] AB16
AB19
Place these caps inside 1 1 1 1 1 1
VSS[043] VSS[124]
F5 VSS[044] VSS[125] AB23 the CPU socket cavity. C502
10U_0805_6.3V6M
C510
10U_0805_6.3V6M
C515
10U_0805_6.3V6M
C520
10U_0805_6.3V6M
C526
10U_0805_6.3V6M
C532
10U_0805_6.3V6M
F8 VSS[045] VSS[126] AB26
2 2 2 2 2 2
F11 VSS[046] VSS[127] AC3 ( Right side on Bottom ).
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
+CPU_CORE
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
H6 AD11
VSS[058] VSS[139]
ESR <= 1.5m ohm
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
H21
H24
VSS[059] VSS[140] AD13
AD16
Place these caps inside 1 1 1 1
Place these caps inside
VSS[060] VSS[141]
J2 VSS[061] VSS[142] AD19 the CPU socket. the CPU socket.
C196

C198

C258

C250
B
J5 AD22 + + + + B
J22
J25
VSS[062]
VSS[063]
VSS[143]
VSS[144] AD25
AE1
( Left side on Top ). ( Right side on Top side). Capacitor > 880 uF
VSS[064] VSS[145] 2 2 2 2
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13 Place these inside
N4 VSS[078] VSS[159] AF16 socket cavity on L8
N23 VSS[079] VSS[160] AF19 (North side
N26 VSS[080] VSS[161] AF21
P3 A25
Secondary)
VSS[081] VSS[162]
VSS[163] AF25
+VCCP
Penryn
.

1 1 1 1 1 1
C213 C209 C212 C185 C183 C184

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4 U4B
5 H_D#[0..63] U4A
A14 H_A#3 M36
H_A#_3 T7 RSVD1
H_D#0 H_A#4 M_CLK_DDR0

DDR CLK/ CONTROL/COMPENSATION

F2 H_D#_0 H_A#_4 C15 T11 N36 RSVD2 SA_CK_0 AP24 M_CLK_DDR0 13

0.01U_0402_25V7K
H_D#1 H_A#5 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 T12 R33 RSVD3 SA_CK_1 AT21 M_CLK_DDR1 13
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 14
H_D#_2 H_A#_6 +1.8V T13 RSVD4 SB_CK_0
H_D#3 E6 C18 H_A#7 AH9 AU20 M_CLK_DDR3 M_CLK_DDR3 14
H_D#_3 H_A#_7 T14 RSVD5 SB_CK_1
H_D#4 G2 M16 H_A#8 AH10
H_D#_4 H_A#_8 T15 RSVD6
H_D#5 H6 J13 H_A#9 1 1 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 T16 RSVD7 SA_CK#_0 M_CLK_DDR#0 13

1
C398

C400
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 T17 RSVD8 SA_CK#_1 M_CLK_DDR#1 13
H_D#7 F6 R16 H_A#11 R331 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 T18 RSVD9 SB_CK#_0 M_CLK_DDR#2 14
H_D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 T19 RSVD10 SB_CK#_1 M_CLK_DDR#3 14
H_D#9 H3 M13 H_A#13 AK34
H_D#_9 H_A#_13 T20 RSVD11
H_D#10 M9 E17 H_A#14 AN35 BC28 DDR_CKE0_DIMMA
T21 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 T22 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA 13
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB 14

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 14

RSVD
H_D#14 N12 B19 H_A#18 R332 B31
H_D#_14 H_A#_18 T25 RSVD15
H_D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR_CS0_DIMMA#
H_D#_15 H_A#_19 T26 RSVD16 SA_CS#_0 DDR_CS0_DIMMA# 13
H_D#16 P2 E20 H_A#20 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 T27 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 L2 H16 H_A#21 NA lead free AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# 14
H_D#19 N9 L17 H_A#23 AY21
H_D#_19 H_A#_23 T28 RSVD20

1
0.01U_0402_25V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 H_D#_20 H_A#_24 A17 SA_ODT_0 BD17 M_ODT0 13
H_D#21 M5 B17 H_A#25 1 1 R333 AY17 M_ODT1 M_ODT1 13
H_D#22 H_D#_21 H_A#_25 H_A#26 1K_0402_1% SA_ODT_1 M_ODT2 +1.8V
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 14

C403

C404
H_D#23 N2 C21 H_A#27 BG23 AY13 M_ODT3 M_ODT3 14
H_D#_23 H_A#_27 T41 RSVD22 SB_ODT_1
H_D#24 R1 J17 H_A#28 BF23
T44

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R328
N5 H_D#_25 H_A#_29 H20 T73 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R329 1 2 80.6_0402_1%
H_D#_26 H_A#_30 T74 RSVD25 SM_RCOMP#
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32 SMRCOMP_VOH
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 SMRCOMP_VOL
H_D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35 AV42 V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 +3VS SM_VREF R39
Y3 H_D#_32 SM_PWROK AR36 1 2 10K_0402_1%
H_D#33 AD14 H12 H_ADS# R82 BF17 SM_REXT R40 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# 4 SM_REXT
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36 TP_SM_DRAMRST# T29 PAD
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 SM_DRAMRST#
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 DPLL_REF_CLK CLK_MCH_DREFCLK 15
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# 4 DPLL_REF_CLK# CLK_MCH_DREFCLK# 15
H_D#38 Y7 HOST G12 H_BR0# R83 E41 MCH_SSCDREFCLK
H_D#_38 H_BREQ# H_BR0# 4 DPLL_REF_SSCLK MCH_SSCDREFCLK 15
H_D#39 W2 E9 H_DEFER# PM_EXTTS#1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# 4 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 15
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 CLK_MCH_BCLK 10K_0402_5% CLK_MCH_3GPLL

CLK
Y9 H_D#_41 HPLL_CLK AH7 CLK_MCH_BCLK 15 PEG_CLK F43 CLK_MCH_3GPLL 15
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 15 PEG_CLK# CLK_MCH_3GPLL# 15
H_D#43 AA9 J11 H_DPWR#
C H_D#_43 H_DPWR# H_DPWR# 5 C
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12 H_HITM# AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 20
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 20
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 20
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 20
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_TXP0 20
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_TXP1
H_D#_52 15 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 20
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 5 15 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 20
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 5 15 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 20
H_D#55 AE14 Y13 H_DINV#2 PAD T8 P20
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AF3 Y1 H_DINV#3 PAD T9 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_RXN0 20
H_D#57 AC1 CFG5 C25 AE43 DMI_RXN1
H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 20
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_RXN2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 9 CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 20
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 20
H_D#60 AE11 AA5 H_DSTBN#2 PAD T37 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 20
H_D#62 AG2 PAD T65 C24 AE44 DMI_RXP1
H_D#_62 CFG_10 DMI_TXP_1 DMI_RXP1 20
H_D#63 AD6 L9 H_DSTBP#0 PAD T40 N21 AF46 DMI_RXP2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5 CFG_11 DMI_TXP_2 DMI_RXP2 20
M8 H_DSTBP#1 PAD T67 CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 5 CFG_12 DMI_TXP_3 DMI_RXP3 20
AA6 H_DSTBP#2 PAD T47 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 5 CFG_13
H_SWNG C5 AE5 H_DSTBP#3 PAD T10 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 5 CFG_14
H_RCOMP E3 PAD T66 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 4 9 CFG16 L21 CFG_16
K13 H_REQ#1 PAD T68 H21
H_REQ#_1 H_REQ#1 4 CFG_17
H_REQ#2

GRAPHICS VID
H_REQ#_2 F13 H_REQ#2 4 PAD T39 P29 CFG_18
B13 H_REQ#3 CFG19 R28
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20 GFX_VID_0 T30
5 H_CPUSLP# H_CPUSLP# E11 B32
H_CPUSLP# GFX_VID_1 T31
B6 H_RS#0 H_RS#0 4 G33
H_RS#_0 GFX_VID_2 T32
F12 H_RS#1 H_RS#1 4 F33
B H_RS#_1 GFX_VID_3 T33 B
C8 H_RS#2 H_RS#2 4 20 PM_BMBUSY# PM_BMBUSY# R29 E33
H_RS#_2 PM_SYNC# GFX_VID_4 T34
H_VREF A11 H_DPRSTP# B7
H_AVREF 5,19,43 H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
14 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA_1p0 PM_PWROK_R AT40 C34
PWROK GFX_VR_EN T35 +VCCP
PLT_RST# 1 2 PLT_RST#_NB AT11
18,22,24,28,29,33 PLT_RST# RSTIN#
H_RCOMP Dual core 24.9 ohm_1% pull down 4,19 H_THERMTRIP# 1 2 R523 100_0402_5% THERMTRIP# T20
R56 0_0402_5% DPRSLPVR THERMTRIP#
Quad core 16.9 ohm_1% pull down 20,43 DPRSLPVR R32 DPRSLPVR

1
H_SWNG Dual core 100 ohm_1% pull down AH37 CL_CLK0 R100
CL_CLK CL_CLK0 20
Quad core 75 ohm_1% pull down 1 2 PM_PWROK_R AH36 CL_DATA0 1K_0402_1%
20,29 ICH_PWROK CL_DATA CL_DATA0 20
R408 0_0402_5% H_DPRSTP# BG48 AN36 M_PWROK
NC_1 CL_PWROK M_PWROK 20
1 2 BF48 AJ35 CL_RST#
20,29,43 VGATE CL_RST# 20

2
NC_2 CL_RST#

ME
@ R407 0_0402_5% BD48 AH34 CL_VREF CL_VREF
NC_3 CL_VREF
Layout Note: 1 1 BC48 NC_4

1
0913 Delete V_DDR_MCH_REF from POWER circuit C55 @ C53 @ BH47 1
H_RCOMP / H_VREF / H_SWNG BG47
NC_5 C181 R99
NC_6
trace width and spacing is 10/20 +1.8V 2
10P_0402_50V8J
2 10P_0402_50V8J
BE47 NC_7 DDPC_CTRLCLK N28 T36
0.1U_0402_16V4Z 511_0402_1%
Layout Note: BH46 NC_8 DDPC_CTRLDATA M28 T48 2
V_DDR_MCH_REF BF46 G36 T63

2
+VCCP NC_9 SDVO_CTRLCLK

NC
BG45 E36 T64
trace width and NC_10 SDVO_CTRLDATA
1

+VCCP BH44 K36 CLKREQ#_7

NC_11 CLKREQ# CLKREQ#_7 15
spacing is 20/20. R42 BH43 NC_12 ICH_SYNC# H36 MCH_ICH_SYNC#
MCH_ICH_SYNC# 20
221_0603_1%
1K_0402_1%

1K_0402_1% BH6

MISC
NC_13
1

BH5 NC_14
R45 R322 BG4 B12 TSATN#
TSATN#
2

V_DDR_MCH_REF NC_15 TSATN#

13,14 V_DDR_MCH_REF BH3 NC_16
BF3 NC_17
1
0.1U_0402_16V4Z

BH2 2 1 +VCCP
2

H_VREF H_RCOMP H_SWNG R43 NC_18 R521 56_0402_5%

1 BG2 NC_19 HDA_BCLK B28 T99
C121 1K_0402_1% BE2 B30 0814 Add pull up R
NC_20 HDA_RST# T100
24.9_0402_1%

0.1U_0402_16V4Z

BG1 NC_21 HDA_SDI B29 T101

1

1
100_0402_1%

A A
0.1U_0402_16V4Z

1 1 BF1 C29 T102

2

2 NC_22 HDA_SDO
2K_0402_1%

HDA
R46 C391 R324 R323 C386 BD1 A28
NC_23 HDA_SYNC T103
BC1 NC_24
2 2
F1 NC_25 0905 Add test point
A47
2

NC_26
CANTIGA_1p0
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 7 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U4D U4E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 13 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# 13 SB_DQ_5 SB_RAS# DDR_B_RAS# 14
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# 13 DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# 14
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# 14
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] 13 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] 14
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 SA_DQ_19 DDR_A_DQS[0..7] 13 BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] 14
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48

MEMORY
DDR_A_D23 BC40 BC37 DDR_A_DQS3 DDR_B_D23 BF41 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 AY37 AW12 DDR_A_DQS4 DDR_B_D24 BG38 BG37 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] 13 BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] 14 C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] 13 SB_DQ_35 SB_DQS#_6

DDR_A_D36 DDR_B_D36 DDR_B_DQS#7

SYSTEM
AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] 14
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 SA_DQ_38 SA_MA_1 BC24 BF8 SB_DQ_38 SB_MA_0 AV17
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 SA_DQ_40 SA_MA_3 BH24 BC5 SB_DQ_40 SB_MA_2 BC25
DDR_A_D41 BA9 BG25 DDR_A_MA4 DDR_B_D41 BC6 AU25 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 SA_DQ_44 SA_MA_7 BG27 BF6 SB_DQ_44 SB_MA_6 AU28
DDR_A_D45 BD9 BF25 DDR_A_MA8 DDR_B_D45 BF5 AW28 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 SA_DQ_46 SA_MA_9 AW24 BA1 SB_DQ_46 SB_MA_8 AT33
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

U4C
R56 within 500 mils from
pin T37,T36 PEGCOMP trace width Strap Pin Table
BIA_PWM R95 +VCC_PEG and spacing is 20/25 mils.
16 BIA_PWM L32 L_BKLT_CTRL 000 = FSB 1066MHz
16 GMCH_ENBKL GMCH_ENBKL G32 T37 1 2 CFG[2:0] FSB Freq select
R81 1 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 2 10K_0402_5% UMA@ CTRL_CLK M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%

R80
1 2 10K_0402_5% UMA@ CTRL_DATA M33
011 = FSB 667MHz
GMCH_EDID_CLK_LCD L_CTRL_DATA PEG_NRX_GTX_N0
16 GMCH_EDID_CLK_LCD K33 L_DDC_CLK PEG_RX#_0 H44 Others = Reserved
GMCH_EDID_DAT_LCD J33 J46 PEG_NRX_GTX_N1
16 GMCH_EDID_DAT_LCD L_DDC_DATA PEG_RX#_1
L44 PEG_NRX_GTX_N2
PEG_RX#_2
GMCH_LVDDEN
2.4K for check
M29
list PEG_RX#_3 L40
N41
PEG_NRX_GTX_N3
PEG_NRX_GTX_N4
CFG[4:3] Reserved
16 GMCH_LVDDEN L_VDD_EN PEG_RX#_4
1 2 C44 P48 PEG_NRX_GTX_N5 PEG_NRX_GTX_N[0..15] 0 = DMI x 2
LVDS_IBG PEG_RX#_5 PEG_NRX_GTX_N[0..15] 33
R94 2.37K_0402_1%~D B43 N44 PEG_NRX_GTX_N6 CFG5 (DMI select)
LVDS_VBG PEG_RX#_6 1 = DMI x 4
E37
E38
LVDS_VREFH PEG_RX#_7 T43
U43
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8 *
0 = The iTPM Host Interface is enable
D
For Cantiga:2.37kohm LVDS_VREFL PEG_RX#_8
* D

LVDS
16 GMCH_LVDSAC- GMCH_LVDSAC- C41 Y43 PEG_NRX_GTX_N9 CFG6
GMCH_LVDSAC+ LVDSA_CLK# PEG_RX#_9 PEG_NRX_GTX_N10
For Crestline:2.4kohm 16 GMCH_LVDSAC+ C40 LVDSA_CLK PEG_RX#_10 Y48 1 = The iTPM Host Interface is disable
B37 Y36 PEG_NRX_GTX_N11
LVDSB_CLK# PEG_RX#_11
For Calero: 1.5Kohm A37 LVDSB_CLK PEG_RX#_12 AA43 PEG_NRX_GTX_N12 0 =(TLS)chiper suite with no confidentiality
AD37 PEG_NRX_GTX_N13 CFG7 (Intel Management
GMCH_LVDSA0- PEG_RX#_13 PEG_NRX_GTX_N14
H47 AC47 1 =(TLS)chiper suite with confidentiality
16 GMCH_LVDSA0-
16 GMCH_LVDSA1-
16 GMCH_LVDSA2-
GMCH_LVDSA1-
GMCH_LVDSA2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39 PEG_NRX_GTX_N15 Engine Crypto strap) *
GMCH_LVDSA3- LVDSA_DATA#_2 PEG_NRX_GTX_P0
T38 A40 H43

GRAPHICS
LVDSA_DATA#_3 PEG_RX_0 PEG_NRX_GTX_P1
PEG_RX_1 J44 CFG8 Reserved
16 GMCH_LVDSA0+ GMCH_LVDSA0+ H48 L43 PEG_NRX_GTX_P2
GMCH_LVDSA1+ LVDSA_DATA_0 PEG_RX_2 PEG_NRX_GTX_P3 PEG_NRX_GTX_P[0..15]
16 GMCH_LVDSA1+ D45 LVDSA_DATA_1 PEG_RX_3 L41 PEG_NRX_GTX_P[0..15] 33
16 GMCH_LVDSA2+ GMCH_LVDSA2+ F40 N40 PEG_NRX_GTX_P4 CFG9 0 = Reverse Lane,15->0, 14->1
GMCH_LVDSA3+ LVDSA_DATA_2 PEG_RX_4 PEG_NRX_GTX_P5
T46 B40 LVDSA_DATA_3 PEG_RX_5 P47
N43 PEG_NRX_GTX_P6 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
PEG_RX_6 PEG_NRX_GTX_P7
A41 T42
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9 0 = Enable
*
LVDSB_DATA#_2 PEG_RX_9 PEG_NRX_GTX_P10
J37 LVDSB_DATA#_3 PEG_RX_10 W47 CFG10 (PCIE Lookback enable)
Y37 PEG_NRX_GTX_P11 1 = Disable
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13 CFG11 Reserved
*
LVDSB_DATA_1 PEG_RX_13 PEG_NRX_GTX_P14
F37 LVDSB_DATA_2 PEG_RX_14 AC48 PEG_NTX_GRX_N[0..15] 33

PCI-EXPRESS
K37 AD40 PEG_NRX_GTX_P15 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDSB_DATA_3 PEG_RX_15
01 = XOR Mode Enabled
J41 PEG_TXN0 C568 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N0 10 = All Z Mode Enabled
PEG_TX#_0 PEG_TXN1 C537 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N1
M46 1 2 11 = Normal Operation(Default)
GMCH_TV_COMPS
GMCH_TV_LUMA
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40
PEG_TXN2
PEG_TXN3
C538
C539
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3 CFG[15:14] Reserved
*
GMCH_TV_CRMA TVB_DAC PEG_TX#_3 PEG_TXN4 C540 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N4
UMA place 75 ohm K25 M42 1 2
TVC_DAC PEG_TX#_4

TV
R48 PEG_TXN5 C541 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N5
PEG_TX#_5
2

H24 N38 PEG_TXN6 C542 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N6 CFG16 (FSB Dynamic ODT) 0 = Disabled
TV_RTN PEG_TX#_6 PEG_TXN7 C543 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N7
0_0402_5% 0_0402_5% 0_0402_5% PEG_TX#_7 T40 1 2
U37 PEG_TXN8 C544 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N8 1 = Enabled
R142 R143 R144
C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
PEG_TXN9
PEG_TXN10
C545
C546
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
*
1

TV_DCONSEL_0 PEG_TX#_10 PEG_TXN11 C547 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N11

C E32 TV_DCONSEL_1 PEG_TX#_11 AA46 1 2 CFG[18:17] Reserved C
AA37 PEG_TXN12 C548 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N12
CRT_B PEG_TX#_12 PEG_TXN13 C549 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N13
17 CRT_B PEG_TX#_13 AA40 1 2
CRT_G AD43 PEG_TXN14 C550 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N14 CFG19 (DMI Lane Reversal) 0 = Normal Operation
17
17
CRT_G
CRT_R CRT_R PEG_TX#_14
PEG_TX#_15 AC46 PEG_TXN15 C551 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N15
PEG_NTX_GRX_P[0..15] 33

(Lane number in Order)

*
2

2
150_0402_1%

150_0402_1%

150_0402_1%

E28 J42 PEG_TXP0 C552 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P0

CRT_BLUE PEG_TX_0 PEG_TXP1 C553 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P1
PEG_TX_1 L46 1 2 1 = Reverse Lane
UMA@

UMA@

UMA@
R74

R76

R75

G28 M48 PEG_TXP2 C554 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P2

CRT_GREEN PEG_TX_2 PEG_TXP3 C555 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P3
M39 1 2
J28
PEG_TX_3
M43 PEG_TXP4 C556 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P4 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
1

CRT_RED PEG_TX_4

VGA
R47 PEG_TXP5 C557 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P5
PEG_TX_5 PEG_TXP6 C558 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P6
G29 CRT_IRTN PEG_TX_6 N37 1 2 1 = PCIE/SDVO are operating simu.
T39 PEG_TXP7 C559 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P7
3VDDCCL PEG_TX_7 PEG_TXP8 C560 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P8
17 3VDDCCL H32 CRT_DDC_CLK PEG_TX_8 U36 1 2
3VDDCDA J32 U39 PEG_TXP9 C561 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P9
17 3VDDCDA CRT_DDC_DATA PEG_TX_9
17 CRT_HSYNC CRT_HSYNC J29 Y39 PEG_TXP10 C562 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P10 @ R66 1 2 2.21K_0402_1%~D
CRT_HSYNC PEG_TX_10 7 CFG5
E29 Y46 PEG_TXP11 C563 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P11
CRT_VSYNC CRT_TVO_IREF PEG_TX_11 PEG_TXP12 C564 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P12 @ R58
17 CRT_VSYNC L29 CRT_VSYNC PEG_TX_12 AA36 1 2 7 CFG6 1 2 2.21K_0402_1%~D
AA39 PEG_TXP13 C565 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P13
PEG_TX_13 PEG_TXP14 C566 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P14 @ R59
PEG_TX_14 AD42 1 2 7 CFG7 1 2 2.21K_0402_1%~D
2

AD46 PEG_TXP15 C567 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P15

PEG_TX_15 @ R55
0_0402_5% 7 CFG9 1 2 2.21K_0402_1%~D
2

0_0402_5%
R676 R675 R334 CANTIGA_1p0 @ R70 1 2 2.21K_0402_1%~D
7 CFG16
VGA@ VGA@ 1.02K_0402_1%
1

UMA@
+3VS UMA@ CFG[5:16] have internal pullup
1

R483 2.2K_0402_5%
1 2 GMCH_EDID_CLK_LCD
UMA@
R484 2.2K_0402_5%
1 2 GMCH_EDID_DAT_LCD +3VS

@ R72 1 2 2.21K_0402_1%~D
7 CFG19
R334 @ R73 1 2 2.21K_0402_1%~D
7 CFG20
B B
R74 R75
CFG[19:20] have internal pulldown

0_0402_5%
VGA@
0_0402_5% 0_0402_5%
VGA@ VGA@

R76

0_0402_5%
VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
hexainf@hotmail.com Date: Monday, December 15, 2008 Sheet 9 of 45
GRATIS - FOR FREE 5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_CRT +3VS
L11 UMA@ +1.05VS_DPLLA
1 2
BLM18PG181SN1D_0603 +VCCP +VCCP
+VCCP

0.01U_0402_25V7K~N

0.1U_0402_16V4Z
+V1.05VS_AXF

C407 UMA@

C411 UMA@
1 1 U4H 1 2 R101
852mA L13 1 2

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
U13 1 10U_FLC-453232-100K_0.25A_10% 0_0603_5%
VTT_1

4.7U_0805_10V4Z

220U_D2_4VY_R15M

C173

C182
73mA T13 1 1 1 UMA@
2 2 VTT_2

220U_D2_4VY_R15M
B27 U12 +
VCCA_CRT_DAC_1 VTT_3 1 1 1

C384

C191

C113

C69
A26 T12 +
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4

C370
VTT_5 U11
2.68mA 2 2 2
VTT_6 T11
2 2 UMA@ 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7
B25 VSSA_DAC_BG VTT_8 T10
D U9 UMA@ UMA@ D
+3VS_DAC_BG +3VS_DAC_CRT VTT_9
VTT_10 T9
VTT_11 U8
R836 1 2 0_0402_5%~D +1.05VS_DPLLA 64.8mA F47 T8
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
UMA@ U7

VTT
VTT_13 +1.8V_SM_CK
0.01U_0402_25V7K~N

0.1U_0402_16V4Z
+1.05VS_DPLLB 64.8mA L48 T7 1 1 1 +1.8V
VCCA_DPLLB VTT_14 +1.05VS_DPLLB +VCCP
C405 UMA@

C408 UMA@
1 1 U6 R102
VTT_15

0.1U_0402_16V4Z
C383

C373

C56
24mA AD1 T6 L14 1 2

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16

10U_0805_10V4Z

10U_0805_10V4Z
U5 1 2 0_0805_5%
VTT_17 2 2 2

0.1U_0402_16V4Z
+1.05VS_MPLL 139.2mA AE1 T5 10U_FLC-453232-100K_0.25A_10% 1 1 1
2 2 VCCA_MPLL VTT_18

C174

C178

10U_0805_10V4Z

C96

C102
VTT_19 V3
U3 1 1 UMA@ @
VTT_20

C87
+1.8V_TXLVDS 13.2mA J48 V2
VCCA_LVDS VTT_21 2 2 2
1 U2

A LVDS
C413 UMA@ VTT_22 UMA@ UMA@
J47 VSSA_LVDS VTT_23 T2
V1 2 2
1000P_0402_50V7K VTT_24
VTT_25 U1
2 414uA
+1.5VS_PEG_BG AD48 VCCA_PEG_BG
R97
1 2

A PEG
+1.5VS +1.05VS_HPLL +VCCP +1.5VS_TVDAC +1.5VS
0_0603_5% 50mA
1 +1.05VS_PEGPLL AA48 L29 R64
C175 VCCA_PEG_PLL
1 2 1 2

0.022U_0402_16V7K

UMA@

0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5% UMA@

UMA@ C115
0.1U_0402_16V4Z 720mA AR20
2 VCCA_SM_1

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 VCCA_SM_2 1 1 1 1

C388

C387
AN20 VCCA_SM_3
POWER

C114
AR17 VCCA_SM_4
AP17 VCCA_SM_5
+VCCP 2 2 2 2
+1.05VS_A_SM AN17 VCCA_SM_6
AT16 VCCA_SM_7
R50 AR16

A SM
VCCA_SM_8
C
1 2 AP16 VCCA_SM_9 C
10U_0805_10V4Z

1 0_0805_5%
220U_D2_4VY_R15M

1 1 1
C82

+ C83 C72
+VCC_PEG +VCCP
C68

4.7U_0805_10V4Z
2 2 2 2 +1.05VS_MPLL +VCCP R109
1U_0603_10V4Z 26mA AP28 321.35mA L9 1 2
VCCA_SM_CK_1 0_0805_5%
AN28 B22 +V1.05VS_AXF 1 2

10U_0805_10V4Z
VCCA_SM_CK_2 VCC_AXF_1 MBK2012121YZF_0805
AP25 B21 1

AXF
R71 +1.05VS_A_SM_CK VCCA_SM_CK_3 VCC_AXF_2
AN25 VCCA_SM_CK_4 VCC_AXF_3 A21 2
1 2 AN24 +
VCCA_SM_CK_5 1 1
1U_0603_10V4Z

0.1U_0402_16V4Z

C95

220U_D2_4VY_R15M
0_0603_5% 124mA C63 C62

C117
AM28 VCCA_SM_CK_NCTF_1
10U_0805_10V4Z

AM26

A CK
VCCA_SM_CK_NCTF_2 0.1U_0402_16V4Z 10U_0805_10V4Z 2 1
1 1 1 1 AM25 VCCA_SM_CK_NCTF_3 2 2
C104

C122

C123

C103 AL25 BF21 +1.8V_SM_CK

+3VS_DAC_CRT VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
AM24 BH20

SM CK
1U_0603_10V4Z VCCA_SM_CK_NCTF_5 VCC_SM_CK_2
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2 2 2
AM23 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 BF20
AL23 VCCA_SM_CK_NCTF_8
TVA 24.15mA 118.8mA
TVB 39.48mA +1.05VS_DMI
K47 +1.05VS_PEGPLL +VCCP +VCC_PEG
TVX 24.15mA VCC_TX_LVDS +1.8V_TXLVDS
B24 L12 R112
VCCA_TV_DAC_1 +3VS_HV
+3VS_DAC_CRT A24 VCCA_TV_DAC_2 VCC_HV_1 C35 1 2 1 2
TV
B35 105.3mA BLM18PG121SN1D_0603 0_0603_5%
VCC_HV_2

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z

10U_0805_10V4Z
A35

HV
VCC_HV_3
1 1

0.1U_0402_16V4Z

C176

C179
HDMI disable connected to GND 50mA A32 1 1 1
VCC_HDA
0.01U_0402_25V7K~N

0.1U_0402_16V4Z

C116
HDA

C66
C204
V48 1732mA +VCC_PEG 1
VCC_PEG_1
C401 UMA@

C402 UMA@

C410
1 1 VCC_PEG_2 U48
V47 2 2
PEG VCC_PEG_3
VCC_PEG_4 U47
2
2 2 2
D TV/CRT

+1.5VS_TVDAC 58.67mA M25 U46

2 2 VCCD_TVDAC VCC_PEG_5
B +1.5VS_QDAC 48.363mA L28 B
VCCD_QDAC
VCC_DMI_1 AH48 456mA +1.05VS_DMI
+1.05VS_HPLL 157.2mA AF1 AF48
VCCD_HPLL VCC_DMI_2 +1.5VS_QDAC +1.5VS
AH47
DMI

50mA VCC_DMI_3
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47
R69 +VCCP_D
1 2
60.31mA M38 20mils 100_0603_1%
VCCD_LVDS_1

0.01U_0402_25V7K~N

0.1U_0402_16V4Z
LVDS

+1.8V_LVDS L37 A8 @ D3 @ R113 R114

VCCD_LVDS_2 VTTLF1

C97

C98
VTTLF2 L1 1 1 +VCCP 2 1 1 2 1 2 +3VS_HV
VTTLF

AB2 10_0402_5% 0_0402_5%

VTTLF3 CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K
2 2 +3VS
1 1 1
C382

C385

C65
CANTIGA_1p0

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
C401 C405 C413 C174 U4 40 mils
R110 UMA@ R350
1 2 +1.8V 1 2 +1.8V

10U_0805_10V4Z

1000P_0402_50V7K
0_0603_5% 0_0603_5%

10U_0805_10V4Z
1 UMA@ 1 UMA@

C187

C186

1U_0603_10V4Z

C414
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% CRESTLINE_1p0 UMA@ 1 1

C418
VGA@ VGA@ VGA@ VGA@ VGA@
2 2
2 UMA@ 2 UMA@
A A
C407 C173 C115 C186

0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5%

VGA@ VGA@ VGA@ VGA@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

U4G +VCCP
Extnal Graphic: 1210.34mA 3000mA
integrated Graphic: 1930.4mA AP33 W28
VCC_SM_1 VCC_AXG_NCTF_1
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28
+1.8V BH32 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
VCC_SM_3 VCC_AXG_NCTF_3

330U_V_2.5VM
U4F BG32 V26
+VCCP VCC_SM_4 VCC_AXG_NCTF_4

0.01U_0402_16V7K
BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25 1 1 1

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 V25 C99 C86 C101
VCC_SM_6 VCC_AXG_NCTF_6 VGA@ VGA@ VGA@
1 1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24

C165

C147

C164
D
AG34 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8 2 2 2
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 VCC_3 AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23
AA34 C148 2 2 2 1
AW32 AM21 0.22U_0402_10V4Z
VCC_4 VCC_SM_11 VCC_AXG_NCTF_11
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 VCC_10 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
10U_0805_10V4Z

1 AF33 VCC_12 BG31 VCC_SM_19 VCC_AXG_NCTF_19 W20

220U_D2_4VY_R15M

1 1 1 1 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20

C118

C143

C119

C120
+ AE33 BG30 AM19
VCC_13 VCC_SM_21 VCC_AXG_NCTF_21
C374

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AA33 VCC_15 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
2 2 2 2 2
Y33 VCC_16 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
W33 VCC_17 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19

VCC SM
V33 VCC_18 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
U33 VCC_19 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
AH28 VCC_20 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
AF28 VCC_21 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 VCC_22 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AA28 VCC_23 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 VCC_25 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_29 BA36 VCC_SM_36/NC VCC_AXG_NCTF_37 AH17
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_31 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
C
AJ23 +VCCP BB21 AE17 C
VCC_32 VCC_SM_39/NC VCC_AXG_NCTF_40
AH23 VCC_33 AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17

POWER
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
VCC_NCTF_1 AM32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 6326.84mA V17

VCC GFX NCTF

VCC_NCTF_3 VCC_AXG_NCTF_45
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_7 AE32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
AC32 +VCCP AA25 AH16
VCC_NCTF_8 VCC_AXG_4 VCC_AXG_NCTF_50
VCC_NCTF_9 AA32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
Y32 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 AF16
VCC_NCTF_10 VCC_AXG_6 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_13 AM30 1 1 1 1 1 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
AL30 C78 C57 C100 C79 C80 AC23 AA16
VCC_NCTF_14 + VCC_AXG_10 VCC_AXG_NCTF_56
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
AH30 1U_0603_10V4Z VGA@ VGA@ VGA@ VGA@ VGA@ AA23 W16
VCC_NCTF_16 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
2
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
AE30 10U_0805_10V4Z AE21
VCC_NCTF_19 330U_V_2.5VM VCC_AXG_15
VCC_NCTF_20 AC30 AC21 VCC_AXG_16
VCC_NCTF_21 AB30 AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21

VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C70

C71

C67

C81

C146

C145

C163
1 1 1 1 1 1 1

PAD T42 AJ14 VCC_AXG_SENSE

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PAD T43 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 11 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

U4J
U4I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

Close to VREF pins of SO-DIMM

+1.8V
8 DDR_A_DQS#[0..7] V_DDR_MCH_REF 7,14

8 DDR_A_D[0..63] JDIM2

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D5 1 1
8 DDR_A_DM[0..7] VSS DQ4

C201

C220
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
8 DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
DDR_A_D3 DQ2 VSS DDR_A_D13
19 DQ3 DQ12 20
D DDR_A_D12 D
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D9 DQ8 VSS DDR_A_DM1
Layout Note: 25 DQ9 DM1 26
27 VSS VSS 28
Place near JDIM1 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 7
33 VSS VSS 34
DDR_A_D14 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C105

C124

C149

C166

C169

C154

C131

C130

C108

C84
+ 53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
@ DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
Layout Note: DDR_CKE0_DIMMA
77 VSS VSS 78
DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
C Place one cap close to every 2 pullup 81 82 C
VDD VDD
resistors terminated to +0.9V 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
8 DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 8
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
+0.9VS 8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_A_V DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D32
DDR_A_D36 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C106

C125

C126

C127

C150

C151

C167

C107

C128

C129

C152

C153

C168

133 134 DDR_A_D39

DDR_A_D35 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D34 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D47
DDR_A_D44 DQ40 DQ45
143 DQ41 VSS 144
B DDR_A_DQS#5 B
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D43
DDR_A_D46 DQ42 DQ46 DDR_A_D42
Layout Note: 153 DQ43 DQ47 154
Place these resistor 155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
closely JP41,all DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
trace length Max=1.5" 161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 7
165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 172
DDR_A_V

DDR_A_D54 VSS VSS DDR_A_D51

173 DQ50 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
RP14 RP22 56_0404_4P2R_5% DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
DDR_A_MA5 1 4 4 1 DDR_CKE0_DIMMA 183 184
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_A_MA12 DDR_A_DM7 185 DM7 DQS7# 186 DDR_A_DQS#7
187 188 DDR_A_DQS7
RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D58 191 192 DDR_A_D62
DDR_A_MA3 DQ59 DQ62
2 3 3 2 DDR_A_MA6 193 VSS DQ63 194 DDR_A_D63
CLK_SMBDATA 195 196
14,15,20,24 ICH_SM_DA SDA VSS
RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5% CLK_SMBCLK 197 198
14,15,20,24 ICH_SM_CLK SCL SA0
DDR_A_RAS# 1 4 4 1 DDR_A_MA9 199 200
+3VS VDDSPD SA1
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_BS#2

1
10K_0402_5%

10K_0402_5%
1 1
RP6 56_0404_4P2R_5% RP16 56_0404_4P2R_5% C58 C59 P-TWO_A5652C-A0G16

R31

R32
DDR_A_BS#0 1 4 4 1 DDR_A_MA4
A DDR_A_MA10 2 3 3 2 DDR_A_MA2 0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM A A

REVERSE

2
RP5 56_0404_4P2R_5% RP8 56_0404_4P2R_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0
DDR_A_WE# 2 3 3 2 DDR_A_BS#1
Bottom side
RP1 56_0404_4P2R_5% RP2 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 M_ODT0
M_ODT1 1 4 3 2 DDR_A_MA13
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
56_0404_4P2R_5% RP23 56_0404_4P2R_5%
DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM I
R96 56_0402_5% 3 2 DDR_A_MA11 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 13 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

8 DDR_B_DQS#[0..7] Close to VREF pins of SO-DIMM

+1.8V
8 DDR_B_D[0..63]
+DDR_MCH_REF1
V_DDR_MCH_REF 7,13
8 DDR_B_DM[0..7] JDIM1

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6

C221

C222
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
D DDR_B_D3 DQ2 VSS DDR_B_D12 D
Layout Note: 19 DQ3 DQ12 20
DDR_B_D13
21 VSS DQ13 22
Place near JDIM2 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 7
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U 2.5V Y D2
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C112

C139

C160

C138

C177

C109

C132

C133

C155

C189
+ 47 48
DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
@ DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D29
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
Layout Note: DDR_B_D30
71 VSS VSS 72
DDR_B_D26
73 DQ26 DQ30 74
Place one cap close to every 2 pullup DDR_B_D31 75 76 DDR_B_D27
DQ27 DQ31
C
resistors terminated to +0.9VS DDR_CKE2_DIMMB
77 VSS VSS 78
DDR_CKE3_DIMMB C
7 DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS#2 85 86 DDR_B_MA14
8 DDR_B_BS#2 BA2 NC/A14 DDR_B_MA14 8
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
+0.9VS A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
DDR_B_V 111 112
DDR_B_CAS# VDD VDD M_ODT2
8 DDR_B_CAS# 113 CAS# ODT0 114 M_ODT2 7
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z 7 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# 115 NC/S1# NC/A13 116 DDR_B_MA13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C110

C134

C135

C156

C157

C170

C171

C111

C136

C158

C137

C172

C159

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
B DDR_B_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
Layout Note: 147 DM5 DQS5 148
Place these resistor 149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
closely JP42,all DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
trace length Max=1.5" 155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 7
165 166 M_CLK_DDR#3
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#3 7
167 168
DDR_B_V

DDR_B_DQS6 DQS6# VSS DDR_B_DM6

169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP18 RP24 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_MA3 1 4 4 1 DDR_B_MA12 177 178
DDR_B_MA1 DDR_B_MA9 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA10 1 4 4 1 DDR_B_MA14 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#0 DDR_B_MA11 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_MA0 1 4 4 1 DDR_B_MA8 193 194 DDR_B_D63
DDR_B_BS#1 DDR_B_MA5 CLK_SMBDATA VSS DQ63
2 3 3 2 13,15,20,24 ICH_SM_DA 195 SDA VSS 196
CLK_SMBCLK 197 198 R33
13,15,20,24 ICH_SM_CLK SCL SAO
RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_CS2_DIMMB# 1 4 4 1 DDR_B_MA7

1
10K_0402_5%
DDR_B_RAS# 2 3 3 2 DDR_B_MA6 1 1 10K_0402_5%

R34
C61 C60 P-TWO_A5692A-A0G16-N
A RP9 56_0404_4P2R_5% RP20 56_0404_4P2R_5% A
DDR_B_CAS#
DDR_B_WE#
1 4 4 1 DDR_B_MA4
DDR_B_MA2
0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM B
2 3 3 2
REVERSE

2
RP3
56_0404_4P2R_5% RP4 56_0404_4P2R_5%
M_ODT3 2 3 4 1 DDR_B_MA13 Bottom side
DDR_CS3_DIMMB# 1 4 3 2 M_ODT2

56_0404_4P2R_5% RP25 Security Classification Compal Secret Data Compal Electronics, Inc.
4 1 DDR_B_BS#2 2007/1/15 2008/1/15 Title
DDR_CKE3_DIMMB 1 DDR_CKE2_DIMMB
Issued Date Deciphered Date
2 3 2
R335 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM II
56_0404_4P2R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 14 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505

FSC FSB FSA CPU SRC PCI REF DOT_96 USB Routing the trace at least 10mil R971
1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT 0_0805_5% 1
C1189
1
C1190
1
C1191
1
C1192
1
C1193
1
C1194
1
C1195
CLK_XTAL_IN
0 0 0 266 100 33.3 14.318 96.0 48.0 2
10U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P

Y7 0905 Connect to +VCCP
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U55
D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2 R972 D
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
C1196 C1197 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 22P_0402_50V8J
1 1
22P_0402_50V8J C1198 C1199 C1200 C1201 C1202 C1203 C1204

+1.05VS_CK505 2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 0 400 100 33.3 14.318 96.0 48.0

+3VS_CK505
1 1 1 Reserved
@ R973
1 2 +VCCP
56_0402_5%

R976 1 2 0_0402_5% R_MCH_BCLK# R_CLKREQ#_EXPCARD R977 1 2 0_0402_5%

7 CLK_MCH_BCLK# EXPCARD_REQ#16 28
NB R978 1 2 0_0402_5% R_MCH_BCLK R_PCIE_EXPR R979 1 2 0_0402_5% Express Card
7 CLK_MCH_BCLK CLK_PCIE_EXPR 28
R980 2 1 0_0402_5% R_CPU_BCLK# R_PCIE_EXPR# R981 1 2 0_0402_5%
4 CLK_CPU_BCLK# CLK_PCIE_EXPR# 28
R983 CPU R982 2 1 0_0402_5% R_CPU_BCLK
4 CLK_CPU_BCLK
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 7
2.2K_0402_5% R984
R985 1K_0402_5%

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
5 CPU_BSEL0 1 2
0_0402_5% U55
+1.05VS_CK505
1

+3VS_CK505

SRC_8/CPU_ITP
GND
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO

VSS_SRC

VDD_SRC
CPU_0

CPU_1

CLKREQ_7#

SRC_6#
SRC_8#/CPU_ITP#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
@
R986
1K_0402_5%
C C
2

R987 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#

20 CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# 20
FSB 2 53 H_STP_CPU# CPU_STP
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 20
3 VSS_REF VDD_SRC_IO 52
+VCCP CLK_XTAL_OUT 4 51 R_CLK_Rob# R988 1 2 0_0402_5%
XTAL_OUT SRC_10# CLK_PCIE_Rob# 24
CLK_XTAL_IN 5 50 R_CLK_Rob R989 1 2 0_0402_5% MiniCard_Roboson
XTAL_IN SRC_10 CLK_PCIE_Rob 24
6 49 R_CLKREQ#_ROB R990 1 2 0_0402_5%
VDD_REF CLKREQ_10# ROBSON_REQ#10
2

@ R991 1 2 33_0402_1% FSC 7 48 R_PCIE_SATA R992 1 2 0_0402_5%

20 CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_SATA 19
R993 PAD T120 8 47 R_PCIE_SATA# R994 1 2 0_0402_5% ICH_SATA
REF_1 SRC_11# CLK_PCIE_SATA# 19
1K_0402_5% CLK_SMBDATA 9 46 R_CLKSATAREQ# R995 1 2 0_0402_5%
SDA CLKREQ_11# CLKSATAREQ# 20
CLK_SMBCLK 10 45 R_CLK_PCIE_LAN# R996 1 2 0_0402_5%
SCL SRC_9# CLK_PCIE_LAN# 22
11 44 R_CLK_PCIE_LAN R997 1 2 0_0402_5% GLAN
CLK_PCIE_LAN 22
1

FSB NC SRC_9 R_CLKREQ#_GLAN R999 0_0402_5%

1 2 MCH_CLKSEL1 7 12 VDD_PCI CLKREQ_9# 43 1 2 GLAN_REQ#9 22
R998 27 CLK_PCI_CB R1000 1 2 33_0402_5% R_CLK_PCI_CB 13 42
R1003 1K_0402_5% R1001 33_0402_1% PCI2_TME PCI_1 VSS_SRC R1002 1
1 2 14 PCI_2 CLKREQ_4# 41 2 0_0402_5% WLAN_REQ#4 24
24 CLK_DEBUG_PORT R1004 33_0402_1% R_CLK_PCI_EC R_CLK_PCIE_MCARD# R1005 1
5 CPU_BSEL1 1 2 1 2 15 PCI_3 SRC_4# 40 2 0_0402_5% CLK_PCIE_MCARD# 24
0_0402_5% 29 CLK_PCI_EC R1006 33_0402_5% 27_SEL R_CLK_PCIE_MCARD R1007 1
CLK_PCI_TPM 1 2 16 PCI_4/SEL_LCDCL SRC_4 39 2 0_0402_5% CLK_PCIE_MCARD 24 MiniCard_WLAN
1

USB_1/CLKREQ_A#
R1008 1 2 33_0402_1% ITP_EN 17 38
18 PCI_CLK

LCDCLK#/27M_SS
PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
@ 18 37
VSS_PCI CLKREQ_3#

SRC_0/DOT_96
R1009 0905 Connect PCI_CLK

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
0_0402_5%

VDD_PLL3

VSS_PLL3

VSS_SRC
2

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
+VCCP
S IC ICS9LPRS397AKLFT MLF 72P CLK GEN

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CK505
1

@ R_PCIE_ICH# R1010 1 2 0_0402_5%

CLK_PCIE_ICH# 20
R1011 R_PCIE_ICH R1012 1 2 0_0402_5% ICH
1K_0402_5% CLK_PCIE_ICH 20
R1013 1 2 33_0402_1% FSA
20 CLK_48M_ICH
B R1016 R1014 1 B
7 CLKREQ#_7 2 0_0402_5% R_CLKREQ#_7 R_MCH_3GPLL# R1015 1 2 0_0402_5%
CLK_MCH_3GPLL# 7
2

FSC 1 2 1 2 +1.05VS_CK505 R_MCH_3GPLL R1018 1 2 0_0402_5% NB_3GPLL

MCH_CLKSEL2 7 CLK_MCH_3GPLL 7
10K_0402_5% R1017 +1.05VS_CK505
R1020 1K_0402_5% R1019 UMA@2 1 0_0402_5% R_MCH_DREFCLK
7 CLK_MCH_DREFCLK
1 2 NB (UMA) R1021 UMA@2 1 0_0402_5% R_MCH_DREFCLK# SSCDREFCLK# UMA@ R1022 1 2 0_0402_5%
5 CPU_BSEL2 7 CLK_MCH_DREFCLK# MCH_SSCDREFCLK# 7
0_0402_5% SSCDREFCLK UMA@ R1023 1 2 0_0402_5%
MCH_SSCDREFCLK 7 NB_SSC (UMA)
1

R1024 VGA@2 1 0_0402_5%

33 CLK_PCIE_VGA
@ VGA (Discrete) R1026 VGA@2 1 0_0402_5% VGA@ R1067 1 2 0_0402_5%
33 CLK_PCIE_VGA# CLK_NVSS_27M 33
R1025 VGA@ R1195 1 2 0_0402_5%
CLK_NV_27M 33 VGA_27M (DIS)
0_0402_5%
2

+3VS
0 = SRC8/SRC8#
ITP_EN
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
27_SEL
1 = Enable SRC0 & 27MHz(DIS) EXPCARD_REQ#16 1 2
R90 10K_0402_5%
0 = Overclocking of CPU and SRC Allowed ROBSON_REQ#10 1 2
PCI2_TME R89 10K_0402_5%
1 = Overclocking of CPU and SRC NOT allowed CLKSATAREQ# 1 2
R88 10K_0402_5%
GLAN_REQ#9 1 2
+3VS_CK505 +3VS_CK505 +3VS_CK505 1 2 CLK_SMBDATA R87 10K_0402_5%
13,14,20,24 ICH_SM_DA
R1112 WLAN_REQ#4 1 2
0_0402_5% R85 10K_0402_5%
1

VGA@ SB, MINI PCI CLKREQ#_7 1 2

@ R1029 R1030 R1031 R60 10K_0402_5%
A 10K_0402_5% 10K_0402_5% A
10K_0402_5%
13,14,20,24 ICH_SM_CLK 1 2 CLK_SMBCLK
R1132 0_0402_5%
2

ITP_EN 27_SEL PCI2_TME

1

UMA@
R1032
10K_0402_5%
R1033
10K_0402_5%
R1034 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
@
Clock Generator CK505
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 15 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 A B C D E

1 1

JEPICO Conn.

2 2

+LCDVDD +5VALW LVDSAC+ UMA@ R508 0_0402_5% GMCH_LVDSAC+

W=60mils 1 2
LCD +3VS +3VS
LVDSAC- UMA@ R510 1 2 0_0402_5% GMCH_LVDSAC- GMCH_LVDSAC+ 9
GMCH_LVDSAC- 9
2

2
100_0603_1%

47K_0402_5%

LVDSA0+ UMA@ R1196 1 2 0_0402_5% GMCH_LVDSA0+

GMCH_LVDSA0+ 9
R137

R135

EC_ENBKL LVDSA0- UMA@ R570 1 2 0_0402_5% GMCH_LVDSA0-

29 EC_ENBKL

1
GMCH_LVDSA0- 9
R21 LVDSA1+ UMA@ R595 1 2 0_0402_5% GMCH_LVDSA1+
LVDSA1- UMA@ R596 1 2 0_0402_5% GMCH_LVDSA1- GMCH_LVDSA1+ 9
1 1

D26 4.7K_0402_5% GMCH_LVDSA1- 9

3

D S
SI2301BDS-T1-E3 1P SOT23 CH751H-40_SC76 LVDSA2+ UMA@ R597 0_0402_5% GMCH_LVDSA2+
1 2

2
GMCH_LVDSA2+ 9
G
Q7 2 2 1 2 Q6 BKOFF# 1 2 DISPOFF# LVDSA2- UMA@ R598 1 2 0_0402_5% GMCH_LVDSA2-
29 BKOFF# GMCH_LVDSA2- 9
2N7002LT1G_SOT23 G R136 1K_0402_5% W=60mils D25 R652
S @ CH751H-40_SC76
3

Q9 1 +LCDVDD 2 R655 1 EC_ENBKL 1 2

D 7.3 9 GMCH_ENBKL
UMA@ 0_0402_5%
1

BSS138_NL_SOT23 C46 +LCDVDD

1

D9 D
GMCH_LVDDEN 2 2
9 GMCH_LVDDEN 1 2 1 1 33 VGA_ENBKL 2 R651 1 R652 100K_0402_5%
CH751H-40PT_SOD323-2 UMA@ G C43 C41 VGA@ 0_0402_5% 2.2K_0402_5% UMA@
1

D8 S 0.047U_0402_16V7K VGA@
3
10K_0402_5%

33 VGA_LVDDEN VGA_LVDDEN 2 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z

2 2
R138

CH751H-40PT_SOD323-2
VGA@
29 LCD_VCC_TEST_EN LCD_VCC_TEST_EN 2 R662 1 @
2

3 0_0402_5% 3

EDID_CLK_LCD UMA@ R599 1 2 0_0402_5% GMCH_EDID_CLK_LCD

GMCH_EDID_CLK_LCD 9
EDID_DAT_LCD UMA@ R600 1 2 0_0402_5% GMCH_EDID_DAT_LCD
GMCH_EDID_DAT_LCD 9

LCD/PANEL BD. Conn.

Routing Diagram R41
+3VS 1 2 47K_0402_5%

JLVDS1
MXMII Conn. 29 LCD_DET# LCD_DET# 1 2 BIST
1 2 BIST 29
3 3 4 4
LVDS Bus LVDSA0-
5 5 6 6
LVDSA1-
LVDS R NB LVDSA0+
7 7 8 8
LVDSA1+
9 9 10 10
11 11 12 12
13 14 LVDSA2-
13 14 LVDSA2+
15 15 16 16
17 17 18 18
Use Daisy chain to route 19 20 LVDSAC-
19 20
60 MIL 21 21 22 22 LVDSAC+ 33 VGA_LVDSAC+ VGA_LVDSAC+ R630 1 2 0_0402_5% VGA@ LVDSAC+
L55 23 24 33 VGA_LVDSAC- VGA_LVDSAC- R633 1 2 0_0402_5% VGA@ LVDSAC-
+LCDVDD_L 23 24 EDID_DAT_LCD
+LCDVDD 2 1 25 25 26 26
9 BIA_PWM BIA_PWM 2 1 INVT_PWM 0_0805_5% 27 28 EDID_CLK_LCD VGA_LVDSA0+ R634 1 2 0_0402_5% VGA@LVDSA0+
@ R20 10_0402_5% 27 28 33 VGA_LVDSA0+ VGA_LVDSA0- R635 0_0402_5% VGA@ LVDSA0-
+3VS 29 29 30 30 +3VS 1 2
33 VGA_LVDSA0-
1 1 1
C796 31 C797 VGA_LVDSA1+ R601 1 2 0_0402_5% VGA@ LVDSA1+
C36 GND1 33 VGA_LVDSA1+ VGA_LVDSA1- R602 0_0402_5% VGA@ LVDSA1-
32 GND2 1 2
@ 1U_0603_10V4Z 220P_0402_50V7K 220P_0402_50V7K 33 VGA_LVDSA1-
2 2 ACES_88242-3001 2 VGA_LVDSA2+ R603 0_0402_5% VGA@ LVDSA2+
1 2
CONN@ 33 VGA_LVDSA2+ VGA_LVDSA2- R604 1 2 0_0402_5% VGA@ LVDSA2-
33 VGA_LVDSA2-
Follow HEL80's pin definition
4
R19 Except pin 29
0208 Add C796 , C797 for EMI 4

INVERTER Conn. JIVT1

INVPWR_B+ 1
0_0805_5%
2 B+
VGA_CLK_LCD R644 1 0_0402_5% VGA@ EDID_CLK_LCD
33 VGA_CLK_LCD 2
DAC_BRIG 1 2 VGA_DAT_LCD R645 1 2 0_0402_5% VGA@ EDID_DAT_LCD
1 33 VGA_DAT_LCD
C415 470P_0402_50V7K 2 2
INVT_PWM 2 INVT_PWM C32 C34
29 INVT_PWM 3 1 2
DISPOFF# C416 470P_0402_50V7K
DAC_BRIG 4 DISPOFF# 0.1U_0603_50V4Z
1 2
0.1U_0603_50V4Z

29 DAC_BRIG 5 1 1
INVPWR_B+ C417 470P_0402_50V7K
6
7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
MOLEX_53780-0790
CONN@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN/LCD CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 16 of 45
A B C D E
 5 4 3 2 1

+5VS +CRT_VCC

CRT D27
@ DAN217_SC59
D20
@ DAN217_SC59 W=40mils D52 W=40mils +CRT_VCC +CRT_VCC +3VS +3VS +3VS
2 1

1
VGA@ RB411DT146 SOT23 原本為4.7K 原本為10K

2
33 VGA_CRT_R 2 1 1 1

2K_0402_5%

2K_0402_5%
R63 0_0402_5% R103 R6 R77 R108 R107

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
0.1U_0402_16V4Z
C436
VGA@ D22 C6
2 1 @ DAN217_SC59 0.1U_0402_16V4Z
33 VGA_CRT_G

3
R125 0_0402_5% 2 2
+3VS

1
D VGA@ @ D
33 VGA_CRT_B 2 1

2
R98 0_0402_5%

G
UMA@
29 MSEN#
UMA@ JCRT1 VGA_DDC_DATA_C 1 3 2 1 3VDDCDA 9
2 1 CRT_R_C 1 2 CRT_R_L 6 R126 0_0402_5%

S
9 CRT_R

2
R376 0_0402_5% L25 Q3

G
11
UMA@ BK1608LL121-T 0603 1 16 BSS138_NL_SOT23 UMA@
2 1 CRT_G_C 1 2 CRT_G_L 7 17 VGA_DDC_CLK_C 1 3 2 1
9 CRT_G 3VDDCCL 9
R374 0_0402_5% L20 12 R84 0_0402_5%

S
UMA@ BK1608LL121-T 0603 2
2 1 CRT_B_C 1 2 CRT_B_L 8
9 CRT_B Q5
R375 0_0402_5% L21 13 VGA@

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
BSS138_NL_SOT23
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 BK1608LL121-T 0603 3 2 1 VGA_DDCDATA 33
1

1
@ @ @ 1 1 1 DDC_MD2 9 R127 0_0402_5%
For EMI
R364

R367

R366
C430 C432 C431 14 VGA@
C27 C28 C3 4 2 1
2 2 2 VGA_DDCCLK 33
10 R78 0_0402_5%
2 2 2
15
2

1 5
4.7P_0402_50V8C 4.7P_0402_50V8C 4.7P_0402_50V8C C24

100P_0402_50V8J
SUYIN_070549FR015S208CR
+CRT_VCC HSYNC_L
1 2 CONN@
R326 0_0603_5% 2
1 2 2 1 VGA_DDC_DATA_C
C433 0.1U_0402_16V4Z R368 10K_0402_5% 1 2 VSYNC_L 1
R325 0_0603_5% C435 1
5
1

100P_0402_50V8J
UMA@

100P_0402_50V8J
1 1
P
OE#

CRT_HSYNC 2
9 CRT_HSYNC 1 2CRT_HSYNC_B 2 A Y 4 D_CRT_HSYNC C4 VGA_DDC_CLK_C
R124 30_0402_5% C397 C399 2
G

U6

15P_0402_50V8J

15P_0402_50V8J
VGA@ 74AHCT1G125GW_SOT353-5 2 2
3

33 VGA_HSYNC 2 1 1
R392 0_0402_5% +CRT_VCC
C C
VGA@

100P_0402_50V8J
2 1 1 2 C25
33 VGA_VSYNC 2
R393 0_0402_5% C26 0.1U_0402_16V4Z
5
1

UMA@
P
OE#

CRT_VSYNC 1 2CRT_VSYNC_B 2 4 D_CRT_VSYNC

9 CRT_VSYNC A Y
R123 30_0402_5%
G

74AHCT1G125GW_SOT353-5 U5
3

Close to GMCH Close to VGA

B B

A A

Title
<Title>

Size Document Number Rev

CustomLA-4841P 1.0

Date: Monday, December 15, 2008 Sheet 17 of 45

5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
 5 4 3 2 1

+3VS

R1035 1 2 8.2K_0402_5% PCI_DEVSEL#

R1036 1 2 8.2K_0402_5% PCI_STOP#

R1037 1 2 8.2K_0402_5% PCI_TRDY#

27 PCI_AD[0..31]
R1038 1 2 8.2K_0402_5% PCI_FRAME# U56B
PCI_AD0 D11 F1 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 27
R1039 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 PCI_GNT0#
D PCI_AD2
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1#
PCI_GNT0# 27 D
R1040 1 AD2 REQ1#/GPIO50
2 8.2K_0402_5% PCI_IRDY# PCI_AD3 E12 AD3 GNT1#/GPIO51 A7
PCI_AD4 E9 F13 PCI_REQ2#
R1041 1 AD4 REQ2#/GPIO52
2 8.2K_0402_5% PCI_SERR# PCI_AD5 C9 AD5 GNT2#/GPIO53 F12
PCI_AD6 E10 E6 PCI_REQ3#
R1042 1 PCI_PERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
2 8.2K_0402_5% B7 AD7 GNT3#/GPIO55 F6
PCI_AD8 C7
PCI_AD9 AD8 PCI_CBE#0
C5 AD9 C/BE0# D8 PCI_CBE#0 27
PCI_AD10 G11 B4 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 27
PCI_AD11 F8 D6 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 27
PCI_AD12 F11 A5 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 27
PCI_AD13 E7
PCI_AD14 AD13 PCI_IRDY#
A3 AD14 IRDY# D3 PCI_IRDY# 27
+3VS PCI_AD15 D2 E3 PCI_PAR
AD15 PAR PCI_PAR 27
PCI_AD16 F10 R1 PCI_PCIRST#
PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6 PCI_DEVSEL# 27
R1043 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD18 D10 E4 PCI_PERR#
PCI_AD19 AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
R1044 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD20 F7 J4 PCI_SERR#
PCI_AD21 AD20 SERR# PCI_STOP#
C3 AD21 STOP# A4 PCI_STOP# 27
R1045 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD22 F3 F5 PCI_TRDY#
AD22 TRDY# PCI_TRDY# 27
PCI_AD23 F4 D7 PCI_FRAME#
AD23 FRAME# PCI_FRAME# 27
R1046 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD24 C1
PCI_AD25 AD24 PCI_PLTRST#
G7 AD25 PLTRST# C14
R1047 1 2 8.2K_0402_5% PCI_PIRQE# PCI_AD26 H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK 15
PCI_AD27 D1 R2
AD27 PME# EC_PME# 20,29
R1048 1 2 8.2K_0402_5% PCI_PIRQF# PCI_AD28 G5
PCI_AD29 AD28
H6 AD29
R1049 1 2 8.2K_0402_5% PCI_PIRQG# PCI_AD30 G1
PCI_AD31 AD30
H3 AD31
R1050 2 1 8.2K_0402_5% PCI_PIRQH#

C PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
R1051 1 2 8.2K_0402_5% PCI_REQ0# PCI_PIRQC# J6 F2 PCI_PIRQG#
PIRQC# PIRQG#/GPIO4 PCI_PIRQG# 27
PCI_PIRQD# C4 G2 PCI_PIRQH#
R1052 1 PIRQD# PIRQH#/GPIO5
2 8.2K_0402_5% PCI_REQ1#
ICH9M REV 1.0
R1053 1 2 8.2K_0402_5% PCI_REQ2#
C2
R1054 1 2 8.2K_0402_5% PCI_REQ3#
2 1 1 2 PCI_CLK
@ R10 @ 33_0402_5%
22P_0402_50V8J

A16 swap override Strap Boot BIOS Strap

B B
Low= A16 swap override Enble
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location R1057
0_0402_5%
PCI_PCIRST# 2 1 PCI_RST# 27
0 1 SPI

1
@R1055
PCI_GNT3# 1 2 R1056
1K_0402_5% 100K_0402_5%
1 0 PCI

2
+3VALW
1 1 LPC *

5
@ U58
PCI_PLTRST# 2

P
+3VALW B PLT_RST#
Y 4 PLT_RST# 7,22,24,28,29,33
1 A

1
@ R1058
SPI_CS1#_R 1 2 MC74VHC1G08DFT2G SC70 5P R1059
20 SPI_CS1#_R

3
1K_0402_5% 100K_0402_5%
@ R1060 R1061
PCI_GNT0# 1 2 0_0402_5%

2
1K_0402_5% 2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 18 of 45
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
+3VS

1 2 SM_INTRUDER# R1063
R1062 1M_0402_5% GATEA20 1 2
1 2 LAN100_SLP 10K_0402_5%
R1064 330K_0402_1%
1 2 ICH_INTVRMEN R1066
R1065 330K_0402_1% KB_RST# 1 2
10K_0402_5%

D D

+RTCVCC

U56A LPC_AD[0..3] 24,29

1 2
R1068 20K_0402_5% ICH_RTCX1 C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
1 2 C24 RTCX2 FWH1/LAD1 K4
PLACE UNDER OPNE DOOR R1109 20K_0402_5% L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
A25 RTCRST# FWH3/LAD3 K2
SRTCRST#

RTC
LPC
F20 SRTCRST#
SM_INTRUDER# C22 K3 LPC_FRAME#
INTRUDER# FWH4/LFRAME# LPC_FRAME# 24,29
1 1 +VCCP

2
C1220 C1210 ICH_INTVRMEN B22 J3 LPC_DRQ0# T121 PAD
JOPEN2 JOPEN1 LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1 T122 PAD
1U_0603_10V4Z @ 1U_0603_10V4Z @

2
2 2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 29
AJ27 H_A20M# R1070
A20M# H_A20M# 4
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R1071 H_DPRSTP#
DPRSTP# AJ25 1 2 H_DPRSTP# 5,7,43
F14 AE23 H_DPSLP# 0_0402_5%

LAN / GLAN
H_DPSLP# 5

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R1072 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 4
56_0402_5%
D13 AD22 H_PWRGOOD 3/28 add 56ohm
LAN_TXD0 CPUPWRGD H_PWRGOOD 5
ICH_RTCX1 D12 LAN_TXD1 H_IGNNE#
E13 LAN_TXD2 IGNNE# AF25 H_IGNNE# 4
within 2" from R1557

CPU
R1069
1 2 ICH_RTCX2 +1.5VS B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# 4 +VCCP
AG25 H_INTR
C INTR H_INTR 4 C
10M_0402_5% B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# 29
1 1 R1073 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
C1211 C1212 AF23 H_NMI
NMI H_NMI 4
HDA_BITCLK AF6 AF24 H_SMI# R1075
HDA_BIT_CLK SMI# H_SMI# 4
4.7P_0402_50V8J 4.7P_0402_50V8J HDA_SYNC AH4 56_0402_5%
2 2 HDA_SYNC H_STPCLK#
STPCLK# AH27 H_STPCLK# 4
HDARST# AE7

2
HDA_RST# THRMTRIP_ICH# R1078
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# 4,7
ADC_ACZ_SDIN0 AF4
25 ADC_ACZ_SDIN0 HDA_SDIN0
Y8
28 HDA_SDIN1
HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 placed within 2" from

IHDA
1 4 AH3 HDA_SDIN2 ICH8M
AE5 HDA_SDIN3
2 3 SATA4RXN AH11
HDA_SDOUT AG5 AJ11
32.768KHZ_12.5P_MC-146 HDA_SDOUT SATA4RXP
SATA4TXN AG12
PAD T123 AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
PAD T124 AE8 HDA_DOCK_RST#/GPIO34
SATA5RXN AH9
AG8 SATALED# SATA5RXP AJ9
SATA5TXN AE10
23 PSATA_IRX_DTX_N0_C AJ16 SATA0RXN SATA5TXP AF10
0.01U_0402_50V7K AH16
23 PSATA_IRX_DTX_P0_C

SATA
SATA0RXP
HDD 23 PSATA_ITX_DRX_N0
PSATA_ITX_DRX_N0C1213 1
PSATA_ITX_DRX_P0C1214 1
2
2
PSATA_ITX_DRX_N0_C AF17
PSATA_ITX_DRX_P0_C AG17 SATA0TXN SATA_CLKN AH18
AJ18
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_PCIE_SATA# 15
23 PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA 15
0.01U_0402_50V7K AH13 AJ7
23 ODD_IRX_DTX_N0_C SATA1RXN SATARBIAS#
0.01U_0402_50V7K AJ13 AH7 R1081 1 2
23 ODD_IRX_DTX_P0_C SATA1RXP SATARBIAS
ODD 23 ODD_ITX_DRX_N0
ODD_ITX_DRX_N0 C1215 1
ODD_ITX_DRX_P0 1
2 ODD_ITX_DRX_N0_C
2 ODD_ITX_DRX_P0_C
AG14
AF14
SATA1TXN 24.9_0402_1%
23 ODD_ITX_DRX_P0 SATA1TXP
C1216 Within 500 mils
0.01U_0402_50V7K ICH9M REV 1.0

B XOR CHAIN ENTRANCE STRAP:RSVD B

+3VS

@ R1082
1 2 ACZ_SDOUT
1K_0402_5% 25 ACZ_SYNC 1 2 HDA_SYNC
R315 33_0402_5%
28 HDA_SYNC_MDC 1 2
@ R1083 R306 33_0402_5%
1 2 ICH_RSVD
ICH_RSVD 20
1K_0402_5%
25 ACZ_BITCLK 1 2 HDA_BITCLK_AUDIO_R 1 2 33_0402_5%HDA_BITCLK
R817 0_0402_5% R1198
28 HDA_BITCLK_MDC 1 2 HDA_BITCLK_MDC_R 1 2
+COINCELL @R818 0_0402_5% R1130 33_0402_5%
@

25 ACZ_RST# 1 2 HDARST#
1

R316 33_0402_5%
R1234
1K_0402_5%~D
28 HDA_RST_MDC# 1
R307
2
33_0402_5%
modify_11/12
RTCVREF 1 2 HDA_SDOUT
25 ACZ_SDOUT
2

R317 33_0402_5%
Z4012

28 HDA_SDOUT_MDC 1 2
R312 33_0402_5%
2

+RTCVCC
A A

D55
1

BAT54CW_SOT323~D
1
C1451
1U_0603_10V4Z~D
27.4
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 19 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

+3VS 1 2 SERIRQ Place closely pin AF3 Place closely pin H1

R1084 10K_0402_5% +3VALW R1085 1 2 2.2K_0402_5%
1 2 PCI_CLKRUN# R1087 1 2 2.2K_0402_5%
R1086 8.2K_0402_5% U56C CLK_48M_ICH CLK_14M_ICH
1 2 EC_THERM# ICH_SMBCLK G16 AH23 GPIO21 1 2 +3VS
24,28 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@ R1088 8.2K_0402_5% ICH_SMBDATA A13 AF19 GPIO19 R1089 8.2K_0402_5%
24,28 ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 OCP# CL_RST#1 E17 AE21 GPIO36 @ @

SATA
GPIO
ME_EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SMB
R1090 10K_0402_5% C17 AD20 GPIO37 R1091 R1092
CLKSATAREQ# ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
1 2 B18 SMLINK1
R1093 10K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
CLK14 CLK_14M_ICH 15
1 2 PM_BMBUSY# ICH_RI# F19 AF3 CLK_48M_ICH

Clocks
CLK_48M_ICH 15

2
@ R1094 8.2K_0402_5% RI# CLK48
1 2 EC_SCI# PAD T125 SUS_STAT# R4 P1 ICH_SUSCLK T126 PAD 1 @ 1 @
R1095 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C1217 C1218
4 XDP_DBRESET# G19 SYS_RESET#
C16 SLP_S3#
D SLP_S3# SLP_S3# 29 D
ICH8 don't have PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
7 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# 29 2 2
G17 SLP_S5#
SLP_S5# SLP_S5# 29
29 EC_LID_OUT# EC_LID_OUT# A17 SMBALERT#/GPIO11 R695 100_0402_5%
S4_STATE#/GPIO26 C10 T127 PAD
H_STP_PCI# A14 1 2 M_PWROK
15 H_STP_PCI# STP_PCI#
R_STP_CPU# ICH_PWROK

SYS GPIO
15 H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWROK 7,29
+3VS 1 2SB_SPKR 1 2
R1096 @ 10K_0402_5% PCI_CLKRUN# L4 M2 1 2 @ R1097 10K_0402_5%
27,29 PCI_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR 7,43
low-->default 0_0402_5% R1098
ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#

Power MGT
WAKE# BATLOW#
High -->No boot 29 SERIRQ
SERIRQ M5 SERIRQ
EC_THERM# AJ23 R3 PWRBTN_OUT#
29 EC_THERM# THRM# PWRBTN# PBTN_OUT# 29

7,29,43 VGATE 1 2 VRMPWRGD D21 VRMPWRGD LAN_RST# D20 1 2

R1099 0_0402_5% R1100 0_0402_5%
+3VS 1 2 GPIO49 1 2 PAD T128 A20 D22 R_EC_RSMRST# R_EC_RSMRST# R1104
1 2 10K_0402_5%
R1101
@ 10K_0402_5% R1102 100K_0402_5% TP11 RSMRST#
@ 4 OCP# OCP# AG19 R5 CK_PWRGD_R R1105 1 2 0_0402_5%
GPIO1 CK_PWRGD CK_PWRGD 15
ISOLATEB AH21
22 ISOLATEB GPIO6
checklist pull hi AG21 R6 M_PWROK
GPIO7 CLPWROK M_PWROK 7
29 EC_SMI# EC_SMI# A21
EC_SCI# GPIO8 +3VS
29 EC_SCI# C12 GPIO12 SLP_M# B16 T129 PAD
0825 Change GPIO pin assignment PAD T130 C21 GPIO13
0612 Change GPIO pin assignment AE18 GPIO17 CL_CLK0 F24 CL_CLK0
CL_CLK0 7
R1106
K1 B19 0.1U_0402_16V4Z 1 2
GPIO18 CL_CLK1 3.24K_0402_1%
AF8 GPIO20

1
AJ22 F22 CL_DATA0 1
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 7
22,24,28 ICH_PCIE_WAKE_R_ECARD# ICH_PCIE_WAKE_R_ECARD# 1 2ICH_PCIE_WAKE# A9 C19 C1219 R1107

GPIO
Controller Link
R1229 0_0402_5% GPIO27 CL_DATA1 453_0402_1%
PAD T132 D19 GPIO28
CLKSATAREQ# L1 C25 CL_VREF0_ICH
15 CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0 2
22,24,28 LANWAKE_R_ICH_WAKE# LANWAKE_R_ICH_WAKE# AE19 A19 NA lead free

2
SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C WL_WAKE_R_ICH_WAKE# C
22,24,28 WL_WAKE_R_ICH_WAKE# 1 2EC_PME# EC_PME# 18,29 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#
CL_RST# 7
R1230 0_0402_5% GPIO49 AH24 D18
CL_RST#1 CLGPIO5 GPIO49 CL_RST1#
+3VALW 1 2 @ A8 GPIO57/CLGPIO5
R1108 10K_0402_5% A16 D54 @
ICH_LOW_BAT# SB_SPKR MEM_LED/GPIO24
1 2 26 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 1 ACIN 29,37,38
R1110 8.2K_0402_5% MCH_ICH_SYNC# AJ24 C11
7 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
1 2 ICH_PCIE_WAKE# ICH_RSVD B21 C20 +3VALW 1 2 RB411DT146 SOT23
19 ICH_RSVD TP3 WOL_EN/GPIO9
R1111 1K_0402_5% R1118 10K_0402_5%

MISC
PAD T133 AH20 TP8
1 2 ICH_RI# PAD T134 AJ20 @
R1113 10K_0402_5% TP9
PAD T135 AJ21 TP10
1 2 XDP_DBRESET#
R1114 10K_0402_5%
1 2 ME_EC_CLK1
ICH9M REV 1.0
RSMRST circuit
R1115 10K_0402_5% U56D
1 2 ME_EC_DATA1 N29 V27 DMI_RXN0 DMI_RXN0 7 R1103 @ R656
R1116 10K_0402_5% PERN1 DMI0RXN DMI_RXP0 0_0402_5% 0_0402_5%
N28 PERP1 DMI0RXP V26 DMI_RXP0 7

Direct Media Interface

1 2 EC_LID_OUT# P27 U29 DMI_TXN0 DMI_TXN0 7 1 2 1 2 POK 39
R1117 10K_0402_5% PETN1 DMI0TXN DMI_TXP0
P26 PETP1 DMI0TXP U28 DMI_TXP0 7
GLAN_RXN L29 Y27 DMI_RXN1 DMI_RXN1 7 R_EC_RSMRST#
22 GLAN_RXN PERN2 DMI1RXN 29 EC_RSMRST#
1 2 CLGPIO5 GLAN_RXP L28 Y26 DMI_RXP1 DMI_RXP1 7
22 GLAN_RXP PERP2 DMI1RXP
R1163 10K_0402_5% GLAN 0.1U_0402_16V7K~N2 1 C1221GLAN_TXN_C M27 W29 DMI_TXN1 DMI_TXN1 7
22 GLAN_TXN PETN2 DMI1TXN
1 2 EC_SMI# 0.1U_0402_16V7K~N2 1 C1222GLAN_TXP_C M26 W28 DMI_TXP1 DMI_TXP1 7
22 GLAN_TXP PETP2 DMI1TXP
R1119 8.2K_0402_5%
PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 7
24 PCIE_RXN3 PERN3 DMI2RXN
PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 7
24 PCIE_RXP3 PERP3 DMI2RXP

PCI-Express
WLAN 24 PCIE_TXN3 0.1U_0402_16V7K~N2 1 C1223PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 7
0.1U_0402_16V7K~N2 PETN3 DMI2TXN
24 PCIE_TXP3 1 C1224PCIE_C_TXP3 K26 PETP3 DMI2TXP AA28 DMI_TXP2 DMI_TXP2 7
PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 7
28 PCIE_RXN4 PERN4 DMI3RXN
Express Card PCIE_RXP4 G28 AD26 DMI_RXP3 DMI_RXP3 7
28 PCIE_RXP4 PERP4 DMI3RXP
28 PCIE_TXN4 0.1U_0402_16V7K~N2 1 C1225PCIE_C_TXN4 H27 PETN4 DMI3TXN AC29 DMI_TXN3 DMI_TXN3 7
B
28 PCIE_TXP4 0.1U_0402_16V7K~N2 1 C1226PCIE_C_TXP4 H26 PETP4 DMI3TXP AC28 DMI_TXP3 DMI_TXP3 7
B

PCIE_RXN5 E29 T26 CLK_PCIE_ICH#

24 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 15
PCIE_RXP5 E28 T25 CLK_PCIE_ICH
24 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 15
3G 24 PCIE_TXN5 0.1U_0402_16V7K~N2 1 C1228PCIE_C_TXN5 F27 PETN5
24 PCIE_TXP5 0.1U_0402_16V7K~N2 1 C1227PCIE_C_TXP5 F26 PETP5 DMI_ZCOMP AF29 R1120 24.9_0402_1% Within 500 mils
AF28 DMI_IRCOMP 1 2 +1.5VS
DMI_IRCOMP
C29 PERN6/GLAN_RXN
C28 AC5 USB20_N0
PERP6/GLAN_RXP USBP0N USB20_N0 31
D27 AC4 USB20_P0 USB0
PETN6/GLAN_TXN USBP0P USB20_P0 31
D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 31
AD2 USB20_P1 USB1
USBP1P USB20_P1 31
D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 31
D24 AC2 USB20_P2 Camera
SPI_CS0# USBP2P USB20_P2 31
18 SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3
SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 24
AA4 USB20_P3 3G/TV
USBP3P USB20_P3 24
D25 AB2 USB20_N4
SPI_MOSI USBP4N USB20_N4 31
E23 SPI_MISO USBP4P
SPI AB3 USB20_P4
USB20_P4 31 BlueTooth
AA1 USB20_N5
USBP5N USB20_N5 31
USB_OC#0 N4 AA2 USB20_P5 FingerPrinter
31 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 31
USB_OC#1 N5 W5 USB20_N6
31 USB_OC#1 OC1#/GPIO40 USBP6N USB20_N6 24
USB_OC#2 USB20_P6
RP39
31 USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USBP6P USB W4
Y3 USB20_N7
USB20_P6 24 WLAN
31 USB_OC#3 OC3#/GPIO42 USBP7N USB20_N7 28
EC_SWI# 4 5 USB_OC#4 M1 Y2 USB20_P7 Express Card
+3VALW OC4#/GPIO43 USBP7P USB20_P7 28
USB_OC#1 3 6 USB_OC#5 N2 W1 USB20_N8
+3VS OC5#/GPIO29 USBP8N USB20_N8 31
USB_OC#2 2 7 EC_SWI# M4 W2 USB20_P8 USB2
29 EC_SWI# OC6#/GPIO30 USBP8P USB20_P8 31
USB_OC#4 1 8 USB_OC#7 M3 V2 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 31
USB_OC#8 N3 V3 USB20_P9 USB3
OC8#/GPIO44 USBP9P USB20_P9 31
10K_1206_8P4R_5% USB_OC#9 N1 U5 USB20_N10
OC9#/GPIO45 USBP10N USB20_N10
1

2.2K_0402_5% USB_OC#10 P5 U4 USB20_P10 Mini Card2

OC10#/GPIO46 USBP10P USB20_P10
RP40 2.2K_0402_5% R1123 R1124 USB_OC#11 P3 U1
USB_OC#7 OC11#/GPIO47 USBP11N
4 5 USBP11P U2
A USB_OC#8 Q106 USBRBIAS A
3 6 AG2 USBRBIAS
USB_OC#9 2 7 SSM3K7002FU_SC70-3 AG1
2

USBRBIAS#
1
S

USB_OC#0 1 8 3 1 ICH_SMBDATA ICH_SMBDATA 24,28 Within 500 mils

13,14,15,24 ICH_SM_DA
ICH9M REV 1.0
S

10K_1206_8P4R_5%
13,14,15,24 ICH_SM_CLK 3 1ICH_SMBCLK ICH_SMBCLK 24,28 R1125
22.6_0402_1%
G
2

RP41
2

USB_OC#3 Q107
G

4 5 Security Classification Compal Secret Data Compal Electronics, Inc.

2

USB_OC#5 3 6 +5VS SSM3K7002FU_SC70-3

USB_OC#10 2 7 2006/02/13 2006/03/10 Title
USB_OC#11
Issued Date Deciphered Date
1 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE
10K_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U56E

20 mils G3: 6uA U56F 1634mA AA26 VSS[1] VSS[107] H5
A23 VCCRTC VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

1U_0603_10V4Z~D
0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 1 ICH_V5REF_RUN 2mA A6 C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C1229

C1230
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22

C1231
ICH_V5REF_SUS 2mA AE1 E15 C1232 C1233 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
2 2
0ohm Change to BEAD AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
AB25 L16 L97 AC17 L26
VCC1_5_B[4] VCC1_05[10] VSS[11] VSS[117]
L96 40 mils AC24 VCC1_5_B[5] VCC1_05[11] L17 BLM18PG181SN1_0603~D AC26 VSS[12] VSS[118] L27
+1.5VS 1 2 22U_0805_6.3V6M~D 646mA AC25 L18 0.01U_0402_16V7K 1 2 +1.5VS AC27 L5
BLM21PG600SN1D_0805~D VCC1_5_B[6] VCC1_05[12] VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12

220U_D2_4VM
+ C1235 C1236 C1237 AE25 P11 C1238 C1239 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C1234
AE26 P18 10U_0805_10V4Z AD12 M14
VCC1_5_B[10] VCC1_05[16] VSS[17] VSS[123]
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD13 VSS[18] VSS[124] M15
2 2 2 2 2 2
AE28 VCC1_5_B[12] VCC1_05[18] T18 AD14 VSS[19] VSS[125] M16
AE29 U11 AD17 M17

CORE
2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[19] VSS[20] VSS[126]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD18 VSS[21] VSS[127] M23
+5VS +3VS 22U_0805_6.3V6M~D G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] 5ohm@100MHz VSS[22] VSS[128]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD28 VSS[23] VSS[129] M29
H25 VCC1_5_B[17] VCC1_05[23] V14 1 2 +VCCP AD29 VSS[24] VSS[130] N11
1

22U_0805_6.3VAM
J24 V16 L98 AD4 N12
R1127 D45 VCC1_5_B[18] VCC1_05[24] BLM18PG181SN1_0603~D VSS[25] VSS[131]
J25 VCC1_5_B[19] VCC1_05[25] V17 1 AD5 VSS[26] VSS[132] N13
100_0402_5%~D K24 V18 C1240 AD6 N14
CH751H-40PT_SOD323-2 VCC1_5_B[20] VCC1_05[26] VSS[27] VSS[133]
K25 VCC1_5_B[21] AD7 VSS[28] VSS[134] N15
L23 R29 AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]

L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
ICH_V5REF_RUN L25 W23 23mA AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
M25 VCC1_5_B[26] AE16 VSS[33] VSS[139] N27
C1241 N23 AB23 48mA AE17 P12
1U_0603_10V6K~D VCC1_5_B[27] V_CPU_IO[1] VSS[34] VSS[140]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE2 VSS[35] VSS[141] P13
2

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
0.1U Change to 1U P24 AG29 2mA 0.1U_0402_16V4Z +3VS 1 1 1 AE24 P15
VCC1_5_B[30] VCC3_3[1] VSS[37] VSS[143]

C1242

C1243

C1244
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 AJ6 0.1U_0402_16V4Z 1 +3VS 1 AE4 P17
+5VALW +3VALW VCC1_5_B[32] VCC3_3[2] VSS[39] VSS[145]
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2

C1245

C1246
R26 AC10 0.1U_0402_16V4Z 1 +3VS AE9 P23
VCC1_5_B[34] VCC3_3[7] VSS[41] VSS[147]
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

2 2

C1247
D46 T24 AD19 AF16 P29
R1128 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]

VCCP_CORE
T27 VCC1_5_B[37] VCC3_3[4] AF20 AF18 VSS[44] VSS[150] P4
100_0402_5%~D 2 (DMI)
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 308mA AF26 R12
2

ICH_V5REF_SUS VCC1_5_B[40] VSS[47] VSS[153]

U25 VCC1_5_B[41] VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13

0.1U_0402_16V4Z

C1248

0.1U_0402_16V4Z

C1249

0.1U_0402_16V4Z

C1250
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 1 Add 0.1uF AF5 VSS[49] VSS[155] R14
1 V25 VCC1_5_B[43] VCC3_3[10] G3 AF7 VSS[50] VSS[156] R15
U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[51] VSS[157] R16
C1306 W24 J2 AG13 R17
1U_0603_10V6K~D VCC1_5_B[45] VCC3_3[12] 2 2 2 VSS[52] VSS[158]

PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[53] VSS[159] R18
2
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 VCC1_5_B[48] AG20 VSS[55] VSS[161] T12
L99 Y25 AJ4 0.1U_0402_16V4Z +3VS AG23 T13
10UH_LB2012T100MR_20%_0805~D 47mA VCC1_5_B[49] VCCHDA VSS[56] VSS[162]
1 AG3 VSS[57] VSS[163] T14
+1.5VS 1 2 AJ19 AJ3 11mA 0.1U_0402_16V4Z +3VALW C1252 AG6 T15
VCCSATAPLL VCCSUSHDA VSS[58] VSS[164]
1 AG9 VSS[59] VSS[165] T16
1U_0603_10V4Z

10U_0805_10V4Z

1342mA AC16 AC8 11mA C1253 AH12 T17

+1.5VS VCC1_5_A[1] VCCSUS1_05[1] T140 2 VSS[60] VSS[166]
1 AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 AH14 VSS[61] VSS[167] T23
T141
C1254

1 1 AD16 VCC1_5_A[3] AH17 VSS[62] VSS[168] B26

2

ARX
C1255

C1256 AE15 AD8 VCCSUS1_5_ICH_1 AH19 U12

VCC1_5_A[4] VCCSUS1_5[1] T142 VSS[63] VSS[169]
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 1U_0603_10V4Z VCCSUS1_5_ICH_2
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH22 VSS[65] VSS[171] U14
2 2 T143
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 C1257 AH28 U16
VCC1_5_A[8] VSS[67] VSS[173]
A18 AH5 U17
VCCPSUS

VCCSUS3_3[1] +3VALW VSS[68] VSS[174]

AC11 D16 0.1U_0402_16V4Z AH8 AD23
+1.5VS VCC1_5_A[9] VCCSUS3_3[2] 2 VSS[69] VSS[175]
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26
C1258 AE11 E22 AJ14 U27
VCC1_5_A[11] VCCSUS3_3[4] VSS[71] VSS[177]
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3

1U_0603_10V4Z AG10 AJ8 V1
2 VCC1_5_A[13] VSS[73] VSS[179]
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] 212mA B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]

0.1U_0402_16V4Z~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
U6 1 1 1 C26 W27
VCCPUSB

+1.5VS VCCSUS3_3[12] VSS[82] VSS[188]

AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 C27 VSS[83] VSS[189] W3

C1259

C1260

C1261
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C1262 G10 V7 E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 2 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA E8 AF2
C1263 VCCCL1_05_ICH VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
11mA T144
1 F28 VSS[93]
0.1U_0402_16V4Z AA7 G23 C1264 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 A24 +LAN_IO 1 1 0.1U_0402_16V4Z G14 A28
VCC1_5_A[28] VCCCL3_3[1] @ @ 2 VSS[96] VSS_NCTF[3]
AC6 VCC1_5_A[29] VCCCL3_3[2] B24 G18 VSS[97] VSS_NCTF[4] A29
C1265 1U_0603_10V4Z

C1266 0.1U_0402_16V4Z~D

AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1

G24 VSS[99] VSS_NCTF[6] AH29
VCC_LAN1_05_INT_ICH_1 2 2
1 2 A10 VCCLAN1_05[1] G26 VSS[100] VSS_NCTF[7] AJ1
+LAN_IO C1267 VCC_LAN1_05_INT_ICH_2 A11 G27 AJ2
0.1U_0402_16V4Z~D VCCLAN1_05[2] VSS[101] VSS_NCTF[8]
G8 VSS[102] VSS_NCTF[9] AJ28
1 2 19/78/78mA A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
0.1U_0402_16V4Z

1 R1129 0_0603_5% B12 H23 B1

C1268 VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
+1.5VS 1 2 A27 VCCGLANPLL H29 VSS[106]
L100 80mA
2
GLAN POWER
10U_0805_10V4Z

1UH_20%_0805~D ICH9M REV 1.0

2.2U_0603_6.3V4Z

+1.5VS D28 VCCGLAN1_5[1]

D29 VCCGLAN1_5[2]
1 1 1 E26 VCCGLAN1_5[3]
A C1269 C1270 C1271 A
E27 VCCGLAN1_5[4]
1mA
+3VS A26
VCCGLAN3_3
2 2 2
ICH9M REV 1.0
4.7U_0603_6.3V6M~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 21 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

+3VALW
W=60mils +LAN_IO +LAN_VDD
Q108 L22 LAN_DVDD12
FBMA-L11-322513-201LMA40T_1210

D
6 1.5A

S
5 4+3VALW_Q1 2 1 2 LAN_DVDD12
1 2 1 1 1 1 1 1 1

C395
0.1U_0402_10V7K~N C1450

0.1U_0402_10V7K~N C1448

0.1U_0402_10V7K~N C1434

0.1U_0402_10V7K~N C1420

0.1U_0402_10V7K~N C1449

0.1U_0402_10V7K~N C1435

C1421

C1422

C1423
C1431 C420 C1432 C406 C394 C1419 C1433 C1447 R1221

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
1 1 1 1 1 1 1 1 1 1 1
1U_0603_10V6K SI3456BDV-T1-E3_TSOP6 @ 0_0603_5%

G
3
B+_BIAS 2 2 2 2 2 2 2 2

22U_1206_6.3V6M

22U_1206_6.3V6M

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
2 2 2 2 2 2 2 2 2 2
2

R1200
D D
470K_0402_5%
1

EN_WOL 2@ R1201 1 1.5M_0402_5%

These caps close to U47: Pin 16, 37, 46, 53
1

D
Q27
These caps close to U47: Pin 21, 32, 38, 43, 49, 52
2
SSM3K7002FU_SC70-3 G EN_WOL# 29 U47 +LAN_IO
S 0.1U_0402_16V7K~N
3

20 GLAN_RXP 2 1 GLAN_RXP_C 29 HSOP EEDO 45 TP58 3.6K_0402_5%

C452 0.1U_0402_16V7K~N 47 LAN_EEDI R1199
@ 1 2
EEDI/AUX
20 GLAN_RXN 2 1 GLAN_RXN_C 30 HSON EESK 48 TP59
C453 44 @ +LAN_IO
EECS TP60
GLAN_TXP 23 @
20 GLAN_TXP HSIP

1
GLAN_TXN 24
20 GLAN_TXN HSIN
54 LAN_LED3 R1203
LED3 LAN_LED2
LED2 55 0_0805_5%
GLAN_REQ#9 33 56 LAN_LED1
15 GLAN_REQ#9 CLKREQB LED1
57 LAN_LED0

2
LED0
15 CLK_PCIE_LAN 26 REFCLK_P +LAN_VDDSR
W=40mils
27 3 LAN_MDIP0
15 CLK_PCIE_LAN# REFCLK_N MDIP0
+LAN_VDD 4 LAN_MDIN0 1 1 C1436
MDIN0 LAN_MDIP1 C421
7,18,24,28,29,33 PLT_RST# 20 PERSTB MDIP1 6
7 LAN_MDIN1
L23 MDIN1 LAN_MDIP2

22U_1206_6.3V6M
60mil

0.1U_0402_10V7K~N
MDIP2 9
+LAN_VDD_L LAN_MDIN2 2 2
1 2 1 SROUT12 MDIN2 10
4.7UH_1098AS-4R7M_1.3A_20% LAN_MDIP3
60mil 5
MDIP3 12
13 LAN_MDIN3
+LAN_VDD FB12 MDIN3
+3VS 1 R1204 2 0_0402_5% 62
1 1 +LAN_IO ENSR
C C1437 C412 21 C
DVDD12 LAN_DVDD12
1 2 64 RSET DVDD12 32
1

R1222 2.49K_0402_1% 38
2 2 R327 DVDD12
22U_1206_6.3V6M

C792 close to U47(PIN63)

0.1U_0402_10V7K~N

DVDD12 43
1K_0402_5% 49
LANWAKE_R_ICH_WAKE#
1 R1231 2 0_0402_5% LANWAKE# 19
DVDD12
52
, then C783 close to C792
20,24,28 LANWAKE_R_ICH_WAKE# LANWAKEB DVDD12 L101
2

ISOLATEB FBML10160808121LMT_0603
20 ISOLATEB 36 ISOLATEB
22
30mil 2 1
EVDD12 LAN_AVDD12 LAN_AVDD12
28 +LAN_VDD
EVDD12
2

LAN_XTAL1 60 1 2
R1205 CKTAL1 C389 0.1U_0402_16V7K~N
15K_0402_5% LAN_XTAL2 61 16 +LAN_IO 1 2 1 2 LAN_AVDD12
CKTAL2 VDD33 C390 0.1U_0402_16V7K~N
VDD33 37

C396
0.1U_0402_10V7K~N C1425

0.1U_0402_10V7K~N C1438

0.1U_0402_10V7K~N C1439
46 R2 1 1 1 1
1

VDD33 0_0603_5%
VDD33 53
65 EXPOSE_PAD
W=40mils

0.1U_0402_10V7K~N
+LAN_VDDSR L24 2 2 2 2
L92, C788, C778 25
VDDSR 63 +LAN_VDDSR
FBML10160808121LMT_0603
EGND
close to U28(Pin 1) <200mil Y6 AVDD33 2 LAN_AVDD33 2 1 +LAN_IO
27P_0402_50V8J

27P_0402_50V8J

31 EGND AVDD33 59
1 2 1 2
2 2 8 LAN_AVDD12 C1440 0.1U_0402_16V7K~N
AVDD12
C422

C423

25MHZ_20P_1BX25000CK1A 15 11 1 2
NC AVDD12 C1426 0.1U_0402_16V7K~N
17 NC AVDD12 14
18 NC AVDD12 58 LAN_DVDD12
1 1
34 NC These caps close to U47: Pin 8, 11, 14, 58
35 NC
39 NC IGPIO 50
40 51 LAN_CABDT
NC OGPIO LAN_CABDT
41 @
B NC R1206 B
42 NC
1 2 +3VS JLAN1
RTL8111C-GR_QFN64_9X9 +LAN_IO 12
+LAN_IO Amber LED+
10K_0402_5% LAN_LED0 1 R105 2 LAN_ACTIVITY# 11 Amber LED-

1
220_0402_5% 16
R358 RJ45_TX3- SHLD2
8 PR4-
10K_0402_5% SHLD1 15
RJ45_TX3+ 7 PR4+

2
T51 75_1206_8P4R_5% D2 RJ45_RX1- 6
C409 1 0.01U_0402_16V7K V_DAC C1441 LAN_LED2 1 LED2_LED3 PR2-
2 1 TCT1 MCT1 24 5 4 2
LAN_MDIN3 2 23 RJ45_TX3- 6 3 1000P_1206_2KV7K RJ45_TX2- 5
LAN_MDIP3 TD1+ MX1+ RJ45_TX3+ CH751H-40PT_SOD323-2 PR3-
3 TD1- MX1- 22 7 2
C1415 1 2 0.01U_0402_16V7K V_DAC 4 21 8 1 2 1 RJ45_TX2+ 4
LAN_MDIN2 TCT2 MCT2 RJ45_TX2- D4 PR3+
5 TD2+ MX2+ 20
LAN_MDIP2 6 19 RJ45_TX2+ RP42 LAN_LED3 1 2 RJ45_RX1+ 3
C1442 1 TD2- MX2- PR2+
2 0.01U_0402_16V7K V_DAC 7 TCT3 MCT3 18
LAN_MDIN1 8 17 RJ45_RX1- CH751H-40PT_SOD323-2 RJ45_TX0- 2
LAN_MDIP1 TD3+ MX3+ RJ45_RX1+ PR1-
9 TD3- MX3- 16 SHLD2 14
C419 1 2 0.01U_0402_16V7K V_DAC 10 15 +LAN_IO RJ45_TX0+ 1
LAN_MDIN0 TCT4 MCT4 RJ45_TX0- PR1+
11 TD4+ MX4+ 14 SHLD1 13
LAN_MDIP0 12 13 RJ45_TX0+ LINK_100_1000# 10
TD4- MX4- 1 Green LED-
350uH_GSL5009LF R359 +LAN_IO 9 Green LED+
10K_0402_5%
TYCO_3-440470-4
CONN@
2

D5
LAN_LED1 1 2 LED1_LED3
LED2_LED3 1 R106 2
CH751H-40PT_SOD323-2 220_0402_5%
A R1223 1 2 0_0402_5% LED1_LED3 1 R79 2 LINK_100_1000# A
D6 220_0402_5%
LAN_LED3 1 2
R7 1 2 0_0402_5%
CH751H-40PT_SOD323-2

R321 1 2 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
R1224 1 2 0_0402_5% 2007/1/15 2008/1/15 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM5787M
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

L1
1 2
SATA HDD CONN JSATA1
+5VS +5VS_HD

1 FBMA-L11-160808-301LMA20T_1206~D
PSATA_ITX_DRX_P0 @ R308 1 GND
19 PSATA_ITX_DRX_P0 2 0_0402_5% ITX_DRX_P0 2 A+
PSATA_ITX_DRX_N0 @ R314 1 2 0_0402_5% ITX_DRX_N0 3
19 PSATA_ITX_DRX_N0 A-
C393 4
@ R304 1 GND
19 PSATA_IRX_DTX_N0_C 2 0_0402_5%
IRX_DTX_N0_C 2 1 3900P_0402_50V7K 5 B-
6 B+
@ R305 1 2 0_0402_5%
IRX_DTX_P0_C 2 1 3900P_0402_50V7K 7
19 PSATA_IRX_DTX_P0_C GND
D C392
8
SATA ODD CONN D

V33
9 V33
10 V33
11 GND
12 GND
13 GND JSATA2
14 V5 close JSATA2
+5VS_HD 15 V5 1 GND
16 ODD_ITX_DRX_P0 2
V5 19 ODD_ITX_DRX_P0 RX+
17 ODD_ITX_DRX_N0 3
GND 19 ODD_ITX_DRX_N0 RX-
18 Reserved 4 GND
19 1 2 ODD_IRX_DTX_N0 5
GND 19 ODD_IRX_DTX_N0_C TX-
20 C326 1 2 0.01U_0402_50V7K ODD_IRX_DTX_P0 6
V12 19 ODD_IRX_DTX_P0_C TX+
21 C327 0.01U_0402_50V7K 7
V12 GND
22 V12
SUYIN_127043FB022S338ZR_RV
CONN@
8 DP
+5VS 9 5V
10 5V GND 14
11 MD GND 15
+5VS 12 GND
13 GND
+5VS_HD
10U_0805_10V4Z 0.1U_0402_16V4Z SUYIN_127382FR013S52_NR

10U_0805_10V4Z~N 0.1U_0402_16V7K~N 1 1 1 1
1 C499
C498 C506 C503
1 1 1 1
+ C575
C C574 C296 C377 C376 2 2 2 2 C
150U_B2_6.3VM_R45M
2 2 2 2 2 1U_0603_10V4Z 1000P_0402_50V7K~N

0.1U_0402_16V7K~N 1000P_0402_50V7K~N

Close to ODD Conn

Close to SATA HDD

+1.8VS

Output Swing Control Output De-emphasis Adjustment

SEL2_ [A:B] Swing SEL3_ [A:B] De-emphasis

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
* *

10U_1206_16V4Z
0 1x 0 0dB 1 1 1 1 1 1

C691

C286

C287

C288

C289

C290
1 1.2x 1 -3.5dB
2 2 2 2 2 2

U23 C1053
B PSATA_ITX_DRX_P0 4700P_0402_25V7K~D B
19 PSATA_ITX_DRX_P0 2 AI+ VDD 1
PSATA_ITX_DRX_N0 3 6 2 1 ITX_DRX_P0
19 PSATA_ITX_DRX_N0 AI- VDD

470_0402_5%~D
C1251 1 2 0.01U_0402_16V7K 10
19 PSATA_IRX_DTX_P0_C VDD

1
7 BO+ VDD 23

R1074
C1272 1 2 8 28
19 PSATA_IRX_DTX_N0_C BO- VDD
0.01U_0402_16V7K 5
R290 1 AVDD
2 0_0402_5% 34 SEL0_A
C1052
R292 1 2 0_0402_5% 13 27 4700P_0402_25V7K~D

2
SEL0_B AO+ ITX_DRX_N0
AO- 26 2 1
@ R293 1 2 0_0402_5% 33
@ R294 1 SEL1_A
2 0_0402_5% 14 SEL1_B BI- 21 IRX_DTX_N0_C
22 IRX_DTX_P0_C
R295 1 BI+
2 0_0402_5% 32 SEL2_A
R298 1 2 0_0402_5% 15 SEL2_B @ R285 1
OUT+ 17 2 0_0402_5%
R299 1 2 0_0402_5% 31 18 @ R286 1 2 0_0402_5%
+1.8VS R300 1 SEL3_A OUT-
2 0_0402_5% 16 SEL3_B
36 @ R288 1 2 0_0402_5%
R616 1 SD_A
2 5.1K _0402_1% 30 EN_A SD_B 35 @ R289 1 2 0_0402_5%
R617 1 2 5.1K _0402_1% 29 EN_B
@ R352 1 2 470_0402_5% 19 IREF GND 25 Equalizer Selection
GND 20 SEL0_ [A:B] SEL1_ [A:B] Compliance Channel
GND 9

+1.8VS GND 4 0 0 no equalization

AGND 24
R301 1
R303 1
2 0_0402_5%
2 0_0402_5%
11
12
CLKIN+
CLKIN- PAD 37 * 0 1 [0:2.5dB] @ 1.6 GHz

PI2EQX3201BZFE_TQFN36_6X5~D 1 0 [2.5:4.5dB] @ 1.6 GHz

1 1 [4.5:6.5dB] @ 1.6 GHz
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 23 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 A B C D E

Mini-Express Card for 3G Or TV Tuner

+3VS +1.5VS +3VALW

1 1
1 1 1 1 1 1
C193 C180 C195 C194 C192 C188

4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2

JMINI3
20,22,28 WL_WAKE_R_ICH_WAKE# WL_WAKE_R_ICH_WAKE#
1 20_0402_5% WL_WAKE# 1 2 +3VS
@R1232 1 2
3 3 4 4
+3VS 5 6
5 6 +1.5VS
1 2 3G_CLKREQ# 7 8 LPC_FRAME_R# 1 2 LPC_FRAME# LPC_FRAME# 19,29
R661 10K_0402_5% 7 8 LPC_AD3_R @R2801 0_0402_5% LPC_AD3
9 9 10 10 2
15 CLK_PCIE_Rob# CLK_PCIE_Rob# 11 12 LPC_AD2_R @ R2821 0_0402_5%
2 LPC_AD2
CLK_PCIE_Rob 11 12 LPC_AD1_R @ R2811 0_0402_5% LPC_AD1
15 CLK_PCIE_Rob 13 13 14 14 2
R284 0_0402_5% 15 16 LPC_AD0_R @ R2831 0_0402_5%
2 LPC_AD0
PLT_RST# 15 16 @R287 0_0402_5%
1 2 17 17 18 18 LPC_AD[0..3] 19,29
CLK_DB_R 19 20 MINI2_OFF#
19 20
21 21 22 22 PLT_RST# 7,18,22,28,29,33
20 PCIE_RXN5 23 23 24 24 +3VALW
20 PCIE_RXP5 25 25 26 26
27 27 28 28
29 30 ICH_SMBCLK
29 30 ICH_SMBCLK 20,28
31 32 ICH_SMBDATA
20 PCIE_TXN5 31 32 ICH_SMBDATA 20,28
20 PCIE_TXP5 33 33 34 34
35 35 36 36 USB20_N3 20
37 37 38 38 USB20_P3 20
39 39 40 40
41 41 42 42
43 44 (WWAN_LED#)
43 44
45 45 46 46
47 48 +3VS
2 47 48 2
49 49 50 50
2005/09/27 modified. 51 51 52 52

1
Base on OPTION GTM351E Datasheet Rev0.1 53 54 @
GND1 GND2 R737
Vcc 3.3V +/- 8% FOX_AS0B226-S56N-7F 10K_0402_5%
Peak Icc 2750mA CONN@

2
with max supply droop 50mA MINI2_OFF# R388
1 20_0402_5%
Average Icc 1000mA

1
D
@ Q52 2 3G_OFF#
3G_OFF# 29
2N7002_SOT23 G
S

3
Mini-Express Card---WLAN
3 +3V_WLAN 3

1 2 +3V_WLAN
+3VS
R412 0_0402_5%
+1.5VS +3VS 0.01U_0402_16V7K~N 4.7U_0805_10V4Z~N

1 1 1
C500 C489 C456

1
JMINI2
ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2 @ R1233
WLAN_ACTIVE
@ R380 1 0_0402_5% 1 2 2 2 2
31 WLAN_ACTIVE 2 MINI_PIN3 3 3 4 4
BT_ACTIVE @ R381 1 0_0402_5%
2 MINI_PIN4 5 6 10K_0402_5%
31 BT_ACTIVE 5 6
15 WLAN_REQ#4 WLAN_REQ#4 7 8 LPC_FRAME# LPC_FRAME# 19,29 0.1U_0402_16V4Z~N

2
7 8 LPC_AD3
9 9 10 10
11 12 LPC_AD2 MINI_RF_OFF# R389
1 20_0402_5%
15 CLK_PCIE_MCARD# 11 12 +1.5VS
13 14 LPC_AD1
15 CLK_PCIE_MCARD 13 14

1
LPC_AD0 D
15 15 16 16
PLT_RST# 17 18 @ Q109 2 WL_OFF# 0.01U_0402_16V7K~N
17 18 LPC_AD[0..3] 19,29 WL_OFF# 29
CLK_DEBUG_PORT 2 CLK_DB_R
R384 1 0_0402_5% 19 20 MINI_RF_OFF# MINI_RF_OFF# 2N7002_SOT23 G
15 CLK_DEBUG_PORT 19 20
21 22 S 1 1

3
PCIE_RXN3 PCIE_C_RXN3 21 22 PLT_RST# 7,18,22,28,29,33 C488
20 PCIE_RXN3 1 2 23 23 24 24 +3V_WLAN
20 PCIE_RXP3 PCIE_RXP3 R4031 20_0402_5% PCIE_C_RXP3 25 26
R404 0_0402_5% 25 26 C485
27 27 28 28 +1.5VS 2 2
29 29 30 30 1 2 ICH_SM_CLK 13,14,15,20
PCIE_TXN3 31 32 0_0402_5%1 2R373 ICH_SM_DA 13,14,15,20
20 PCIE_TXN3 31 32
PCIE_TXP3 33 34 0_0402_5% R343 0.01U_0402_16V7K~N
20 PCIE_TXP3 33 34
35 36 USB20_N6
35 36 USB20_N6 20
37 38 USB20_P6
37 38 USB20_P6 20
+3V_WLAN 1 2 39 39 40 40
@ R406 0_0402_5% 41 42
41 42 LED_WLAN#
43 43 44 44 LED_WLAN# 32
45 45 46 46 2 1 +5VS
4 100K_0402_5% R86 4
47 47 48 48 +1.5VS
49 49 50 50
51 51 52 52 +3V_WLAN
53 GND1 GND2 54

FOX_AS0B226-S56N-7F
CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 24 of 45
A B C D E
 5 4 3 2 1

+3VS

2
2
R302
R313
100K_0402_5% @ 100K_0402_5% HP_JD
@

1
D
HD Audio Codec

1
For EMI PLUG_IN# 2 Q24
PLUG_IN#
G SSM3K7002FU_SC70-3
0_0603_5%
20mil S @

3
0.1U_0402_16V4Z 1 2
R568 +3VS

1
D +AVDD_AC97 D D
1 1 1
26 PLUG_IN 2 Q25
C671 C680 C666 G SSM3K7002FU_SC70-3
L41 1 2 0.1U_0402_16V4Z 40mil 10U_1206_16V4Z S @
+VDDA

3
FBM-L11-160808-800LMT_0603 2 2 2
1 1 1
C685
C687 C669 0.1U_0402_16V4Z
10U_1206_16V4Z

25

38

9
2 2 2 U22
0.1U_0402_16V4Z C672 1000P_0402_50V7K~N

DVDD
AVDD1

AVDD2

DVDD_IO
C677 1000P_0402_50V7K~N +MIC1_VREFO
26
14 35 LINEL 1 2 AMP_LEFT 26
LINE2-L(PORT E) LINE1_OUT_L R593 6.8K_0402_5%
15 36 LINER 1 2
LINE2-R(PORT E) LINE1_OUT_R AMP_RIGHT 26 10mil 10mil

1
R589 6.8K_0402_5%
C140 2.2U_0603_6.3V6K MIC2_C_L 16 39 R92 R111
26 MIC2_L MIC2_L(PORT F) LOUT2-L(PORT A)
C141 2.2U_0603_6.3V6K MIC2_C_R 17 41 2.2K_0402_5% 2.2K_0402_5%
26 MIC2_R MIC2_R(PORT F) LOUT2-R(PORT A)

2
23 LINE1_L(PORT C) SPDIFO2 45
MIC_JD
MIC_JD
24 LINE1_R(PORT C) DMIC_CLK1/2 46
MIC-R
MIC-R
18 LINE1-VREF NC 43
MIC-L
MIC-L
20 44 2 1 1 2 JMIC1
LINE2-VREF DMIC_CLK3/4 R612 10_0402_5% C673 10P_0402_50V8J 1 1 1 1
19 6 ACZ_BITCLK_CODEC 1 2 C37 C39 2
+MIC2_VREFO 10mil MIC2-VREF BIT_CLK R610 0_0402_5%
ACZ_BITCLK 19
3
2
MIC-L 1 C_MIC1_L AC97_SDIN0_CODEC 3
2 21 MIC1_L(PORT B) SDATA_IN 8 1 2 0_0402_5% ADC_ACZ_SDIN0 19
CPLS HP-JD 220P_0402_50V7K 220P_0402_50V7K 4 4
C C689 2.2U_0603_10V6K R613 2 2 C
5 5
MIC-R1 2 C_MIC2_R 22 30 C142 1 2 2.2U_0603_6.3V6K 6

26 MONO_IN
C690 2.2U_0603_10V6K
MONO_IN 12
MIC1_R(PORT B)

PCBEEP
CBN

CBP 29
modify_11/12 26 PLUG_IN PLUG_IN 7
8
6
7
8
HPR HPR 9 9
MONO_OUT 37 10 10
ACZ_RST# 11 HPL HPL 11
19 ACZ_RST# RESET# +MIC1_VREFO 11
MIC1_VREFO_L 28 10mil +MIC1_VREFO 27 ohm 12 12

1
ACZ_SYNC 10 @ C667 1000P_0402_50V7K~N 26 1 1 13
19 ACZ_SYNC SYNC G1
32 HP_ROUT 1 2 HPR HPR R131 R130 C50 C51 14
ACZ_SDOUT HPOUT-R(PORT I) R546 27.4_0603_1% G2
19 ACZ_SDOUT 5 SDATA_OUT
33 HP_LOUT 1 2 HPL HPL 0_0402_5% 0_0402_5% 10P_0402_50V8J 10P_0402_50V8J ACES_87212-1200
HPOUT-L(PORT I) 2 2
MIC_JD 1 2 R_MIC_JD 2 @ C668 R554 27.4_0603_1% @ @ CONN@

2
R614 20K_0402_1% GPIO0/DMIC1/2 1000P_0402_50V7K~N
3 GPIO3/DMIC3/4 VREF 27
HP_JD 2 1 R_HP_JD 13
@ R611 39.2K _0402_1% SENSE A +AC97_VREF
CPLS HP-JD
34 SENSE B JDREF 40 +AC97_VREF=10mil
2
R615
1
5.1K _0402_1% 47 31
12/13 Modified this symbol for pin 13 and 14.
EAPD CPVEE

1
2 R572 1
2 2
26
2
EAPD 0_0402_5% 48
1
C681
1 1 Do not re-copy this symbol for other use
SPDIFO1
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
C686

C682

C674

R569 20K_0402_1% C1452 C1453

4 26 2.2U_0603_6.3V6K 0.1U_0402_16V4Z 10U_0805_10V4Z
DVSS1 AVSS1 2 2 2
7 42

2
@ 1 @ 1 @ 1 DVSS2 AVSS2
ALC272-GR_LQFP48

GND
GNDA modify_11/12
B B

26

26

26

26
INTSPK_L1

INTSPK_L2
INTSPK_R1

INTSPK_R2
GND GNDA D14 SM05T1G_SOT23-3~D
Speaker Connector

INTSPK_R1

INTSPK_R2

INTSPK_L1

INTSPK_L2
@
Place U50 close to U6 +VDDA GNDR14 1 2 GNDA 3 JSPK2

@
0_0603_5% 1 INTSPK_L1 1
INTSPK_L2 1
1 2 2 2 2

100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K

100P_0402_25V8K
@ R129 0_0603_5% R1151 2 3 INTSPK_R1 3 3

C15

C16
C8

C9
+5VS 0_0603_5% 1 INTSPK_R2 4 4
R900 U50 2 5 GND1
R1161 2 6
0_0603_5% D18 SM05T1G_SOT23-3~D GND2
1 2 1 EN NC 5
@ ACES_88231-0400
10K_0603_1% 2 R1171 2 CONN@
GND
0.1U_0402_16V7K~N

0.1U_0402_16V7K~N
4.7U_0805_10V4Z

4.7U_0805_10V4Z~N

0_0603_5%
3 VIN VOUT 4
1 1 R1181 2
RT9198-4GPBG SOT-23 5P 4.75V 0_0603_5%
C881 C882
2 2

A A
C883

C884

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/05/07 Deciphered Date 2009/05/07 Title
HD CODEC 92HD81
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4841P
Date: Monday, December 15, 2008 Sheet 25 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 A B C D E

R537
W=40Mil 2 1 +5VS L102 1 2
1 1 MBK1608121YZF_0603

C648 C651 0_0402_5% +5VS

0.1U_0402_16V4Z 10U_0805_10V4Z D10 R1228 0_0603_5%
2 2
1R128 1 2 4.7K_0402_5% @ MIC_GND

16
15
+MIC2_VREFO 2

6
U18 R520 1 2 10K_0402_5% GNDA
RB751V_SOD323

VDD
PVDD1
PVDD2
R801
@ R512 1 2 10K_0402_5% MIC_L1
1 MIC2_R_L L58
1 2 MIC_L_3 2 1
1 MIC2_L 25
2 2 1 0_0603_5% 1K_0402_5%
4 C642 1 R513 1 2 4
2 7 RIN+ GAIN0 2 2 10K_0402_5% @ C52 1
0.47U_0603_10V7K 3 C769
@ R573 1 GND 100P_0402_50V8J
GAIN1 3 2 10K_0402_5% GND 4
220P_0402_50V7K
D53

1
C638 1 AMP_R ACES_88231-02001 @ 2
25 AMP_RIGHT 2 17 RIN-
0.47U_0603_10V7K 18 SPK_R1 1 2 INTSPK_R1 R134 3
ROUT+ INTSPK_R1 25
R505 0_0603_5% 1
MIC_GND 0_0402_5% 2
14 SPK_R2 1 2 INTSPK_R2 @
INTSPK_R2 25
modify_11/12

2
C650 1 ROUT- R504 0_0603_5%
2 9 LIN+
0.47U_0603_10V7K
4 SPK_L1 1 2 INTSPK_L1 D12
LOUT+ R502 0_0603_5% INTSPK_L1 25
+MIC2_VREFO 2 1R132 1 2 4.7K_0402_5% PSOT05C-LF-T7 SOT-23-3
C636 1 2 AMP_L 5
25 AMP_LEFT LIN-
0.47U_0603_10V7K 8 SPK_L2 1 2 INTSPK_L2 RB751V_SOD323
LOUT- INTSPK_L2 25 R805
R503 0_0603_5% MIC_R1
1 MIC2_R_R L59
1 2 MIC_R_3 2 1
1 MIC2_R 25
2 2 1 0_0603_5% 1K_0402_5%
2 @ C54 1
12 3 C770
NC GND 100P_0402_50V8J
GND 4
10 220P_0402_50V7K
10K_0402_5% 2 @ R506 BYPASS ACES_88231-02001 2
1 19 SHUTDOWN
1
C654 MIC_GND

GND1
GND2
GND3
GND4
GND
2 1U_0603_10V4Z
+3VS P3017THF TSSOP 20P
21

20
13
11
1
1

3 3
R170
100K_0402_5%
2

D28 CH751H-40_SC76
2 1 R171 1 2 PLUG_IN PLUG_IN 25 GAIN0 GAIN1 GAIN
2.7K_0402_5%
1

D
@
1

2 Q31 0 0 6dB
29 EC_MUTE#
G SSM3K7002FU_SC70-3
1K_0402_5%
100P_0402_50V8J

S
3

R507
1
C624 0 1 10dB
*
2

2
1 0 15.6dB
25 EAPD
Change to 100p from 0.01u for EMI
-1012 1 1 21.6dB
Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off

2 2

+VDDA
1

R626
10K_0402_5%

C695
2

1 2
1

R624 1U_0603_10V4Z
10K_0402_5%
C366
EC Beep 29 BEEP# 1 2 1
R311
2 C688
2

R156 560_0402_5% 1 2 MONO_IN MONO_IN 25

1U_0603_10V4Z
1 2
1U_0603_10V4Z
1

47K_0402_5% C 1 2
2 Q36
B R623
E 2SC2411K_SC59 2.4K_0402_5%
3

C367
R160
20 SB_SPKR 1 2 1 2
ICH Beep
1

1 R157 560_0402_5% 1
1U_0603_10V4Z D11
1 2
R310 RB751V_SOD323
47K_0402_5% 10K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP/Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4121P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 26 of 45
A B C D E
 5 4 3 2 1

AP2301GN_SOT23-3
+1.8VS_CR
+1.8V Q34 +3VS

D
3 1

4.7U_ 0603_6.3V

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_ 0603_6.3V

0.1U_0402_10V6K
0.01U_0402_25V7K~N
R1214 AS CLOSE AS U44

G
1 1 1

2
1 2 +3VS
36,42 SUSP

C647

C620

C632

C619

C621
100K_0402_5% 1 +3VS_PHY

4.7U_ 0603_6.3V

0.1U_0402_10V6K
+3VS_PHY L15
2 2 2

C679
1 +3VS 1 2
FBM-L11-160808-601LMT_0603
2

C660

C675

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_ 0603_6.3V
PLACE C1139, C1140

120
125

102
103
122
2 AS CLOSE AS U44

26
56

15
14
91
92

67
73
79
81
1 1

7
U44

C337

C343

C345
D PLACE C1141, C1142 AS CLOSE AS U44 D

VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8

VCC3.3
VCC3.3
VCC3.3
VCC3.3
PCI_VCC
PCI_VCC

AVCC
AVCC
AVCC
AVCC
18 PCI_AD[0..31] 2 2
PCI_AD31 19
PCI_AD30 AD31 R542 5.9K_0402_1%
20 AD30
PLACE C1136, C1137, C1138 PCI_AD29 21 78 1 2
AS CLOSE AS U44 PCI_AD28 AD29 REF
22 AD28
PCI_AD27 23 83 OZ129XI
PCI_AD26 AD27 XI OZ129XO +3VS
24 84

+1.8VS_CR
PCI_AD25
PCI_AD24
PCI_AD23
25
27
AD26
AD25
AD24
OZH24TN XO

TPBIAS 76 IEEE1394_TPBIAS0
IEEE1394_TPAP0
29 AD23 TPA+ 75
PCI_AD22 30 74 IEEE1394_TPAN0 R594
AD22 TPA-
1

PCI_AD21 31 72 IEEE1394_TPBP0 22K_0402_5%

R1215 PCI_AD20 AD21 TPB+ IEEE1394_TPBN0
32 AD20 TPB- 71
470_0402_5% PCI_AD19 34
PCI_AD18 AD19
35 AD18
PCI_AD17 36 4 MC_3V# Layout Note: Place close to
2

PCI_AD16 AD17 MC_3V# SDCLK_MSCLK

37 113
PCI_AD15 47
AD16 SD_CLK/MS_CLK
111 SDDATA3 OZ129 and Shield GND.
AD15 SD_D3
1

D PCI_AD14 SDDATA2
48 AD14 SD_D2 112
SUSP 2 Q21 PCI_AD13 49 107 SDDATA1 C643
G SSM3K7002FU_SC70-3 PCI_AD12 AD13 SD_D1 SDDATA0 OZ129XI
50 AD12 SD_D0 108 2 1
S PCI_AD11 51 110 SD_CMD
3

PCI_AD10 AD11 SD_CMD SD_WP 15P_0402_50V8J

52 AD10 SD_WP 117

2
PCI_AD9 53 114 SDCD# X3
PCI_AD8 AD9 SD_CD#
54 AD8
PCI_AD7 57 CLK_PCI_CB
PCI_AD6 AD7 MSDATA1 24.576MHz_16P_3XG-24576-43E1
58 95

1
PCI_AD5 AD6 MS_D1/XD_D7 C635
59 AD5 XD_D6 93

1
10_0402_5%~D
PCI_AD4 60 89 2 1 OZ129XO
PCI_AD3 AD4 XD_D5 R1216
61 AD3 XD_D4 87
PCI_AD2 62 88 MSBS @ 15P_0402_50V8J
C PCI_AD1 AD2 MS_BS/XD_D3 MSDATA0 C
63 AD1 MS_D0/XD_D2 90
PCI_AD0 64 94 MSDATA2

2
AD0 MS_D2/XD_D1 MSDATA3
MS_D3/XD_D0 96
XD_CE# 119
PCI_CBE#3 28 100
18 PCI_CBE#3 C/BE3# XD_RB#

4.7P_0402_50V8C
PCI_CBE#2 38 118
18 PCI_CBE#2 C/BE2# XD_CLE +3VS_CR
PCI_CBE#1 46 109 1
18 PCI_CBE#1 C/BE1# XD_ALE
PCI_CBE#0 55 105
18 PCI_CBE#0 C/BE0# XD_WE#
101 C676
R514 XD_RE# @ SDCLK
XD_WPO# 98
PCI_AD21 CBS_IDSEL MSCD# 2 +3VS
1 2 5 IDSEL MS_CD# 99 1
CLK_PCI_CB 45 97
15 CLK_PCI_CB PCI_CLK XD_CD# +3VS_CR
100_0402_5% PCI_DEVSEL# 42 C324
18 PCI_DEVSEL# DEVSEL#

1
PCI_FRAME# 39 10P_0402_50V8J
18 PCI_FRAME# FRAME# 2
PCI_IRDY# 40 85 R241
18 PCI_IRDY# IRDY# PHY_TEST0

3
S

4.7U_ 0603_6.3V

0.1U_0402_10V6K
PCI_TRDY# 41 86 470_0402_5%
18 PCI_TRDY# TRDY# PHY_TEST1 G
PCI_STOP# 43 MC_3V# 2 U45 1
18 PCI_STOP# STOP#
PCI_PAR 44 AP2301GN_SOT23-3
18 PCI_PAR

2
PCI_REQ0# PAR C323 C1444
18 PCI_REQ0# 17 2 D

1
PCI_GNT0# PCI_REQ# NC
18 PCI_GNT0# 18 PCI_GNT# NC 8

1
PCI_RST# D 2 MSCLK
18 PCI_RST# 1 PCI_RST# NC 9
PCI_PIRQG# 11 10 1 2 MC_3V# 1
18 PCI_PIRQG# INTA# NC
CB_PME# 3 13 Q82 G
CB_PME# PME# NC
6 126 C332 S SSM3K7002FU_SC70-3 C325

3
R524 2 CLKRUN# NC
1 100K_0402_5% NC 127 1U 10V Z Y5V 0603 10P_0402_50V8J
2 2
106 MEDIA_LED NC 128
@ R525 1 2 0_0402_5%~D
20,29 PCI_CLKRUN#
AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

LED behave: OZH24TN LQFP 128P_14X14

3 in 1 Card Reader
12
16
33
66
68
104
115
116
121
123
124

82
80
77
70
69
65

Idel ---------> low

B Accress data --> always high L16 B
2 1
0_0603_5% J3IN1
+3VS_CR 6 VDD_SD
SDDATA0 9
SDDATA1 DAT0_SD
10 DAT1_SD
SDDATA2 2
SDDATA3 DAT2_SD
3 CD/DAT3_SD
IEEE1394_TPBIAS0 SDCLK_MSCLK R199 1 2 22_0402_5% SDCLK 7
SD_WP CLK_SD
11 WP_SD
1U_0603_10V4Z

SD_CMD 4 CMD_SD
1

1
56.2_0402_1%

56.2_0402_1%

1 SDCD# 1 CD_SD
5 VSS_SD
R547 R555 C656 8 VSS_SD
2
2

MSDATA1 19 VCC_MS
13 VCC_MS
IEEE1394TPA+/- and IEEE1394TPB+/- SDCLK_MSCLK R200 1 2 22_0402_5% MSCLK 14
MSCD# SCLK_MS
Same Wire Length P-TWO_CU8042-A0G1G-P
16 INS_MS
MSDATA0 18
IEEE1394_TPAP0 R235 0_0402_5% MSBS SDIO_MS
1 2 4 TPA+ GND 6 20 BS_MS
IEEE1394_TPAN0 R238 1 2 0_0402_5% 3 5 MSDATA3 15
IEEE1394_TPBP0 R236 0_0402_5% TPA- GND MSDATA2 RESERVED_MS
1 2 2 TPB+ 17 RESERVED_MS
IEEE1394_TPBN0 R237 1 2 0_0402_5% 1 21
TPB- VSS_MS
12 VSS_MS
Layout Note: Shield GND for J1394A 22 GND
IEEE1394_TPA and TPB 23 GND
1

1
56.2_0402_1%

56.2_0402_1%

PROCO_MDR019-C0-1202
R559 R1219 CONN@

A A
2

2
270P_0402_50V7K

2 5.1K_0402_1%

2
C659 R571
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/01 Deciphered Date 2008/09/01 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OZ129_Card Reader / 1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note: Place close to OZ129 Chipset. Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4841P
Date: Monday, December 15, 2008 Sheet 27 of 45
5 4 3 2 1

hexainf@hotmail.com
GRATIS - FOR FREE
 5 4 3 2 1

Express card

D JEXP1 D
+1.5VS_PEC
Express Card Power Switch 4.7U_0805_10V4Z~N 1 GND
USB20_N7 R48 1 2 0_0402_5% USB20_N7_R2
20 USB20_N7 USB_D-
+1.5VS 1 1 USB20_P7 R47 1 2 0_0402_5% USB20_P7_R 3
U11 +1.5VS_PEC 20 USB20_P7 USB_D+
EXPR_CPUSB# 4
C90 C89 CPUSB#
2 1 12 1.5Vin 1.5Vout 11 5 RSV
C91 0.1U_0402_16V4Z~N 14 13 0.1U_0402_16V4Z~N 6
1.5Vin 1.5Vout 2 2 ICH_SMBCLK RSV
+3VS 20,24 ICH_SMBCLK 7 SMB_CLK
+3VS_PEC ICH_SMBDATA 8
20,24 ICH_SMBDATA SMB_DATA
2 1 2 3.3Vin 3.3Vout 3 +1.5VS_PEC 9 +1.5V
C74 0.1U_0402_16V4Z~N 4 5 10
3.3Vin 3.3Vout +3VALW_PEC ICH_PCIE_WAKE_R_ECARD# +1.5V
+3VALW 20,22,24 ICH_PCIE_WAKE_R_ECARD# 1 R37 20_0402_5% PCIE_PME#_R 11 WAKE#
2 1 17 AUX_IN AUX_OUT 15 +3VALW_PEC 12 +3.3VAUX
C85 0.1U_0402_16V4Z~N +3VALW_PEC PERST# 13
PLT_RST# 4.7U_0805_10V4Z~N PERST#
7,18,22,24,29,33 PLT_RST# 6 SYSRST# OC# 19 +3VS_PEC 14 +3.3V
15 +3.3V
SYSON 20 8 PERST# 15 EXPCARD_REQ#16 EXPCARD_REQ#16 16
29,36,41 SYSON SHDN# PERST# CLKREQ#
1 1 CPUSB# 17
SUSP# CLK_PCIE_EXPR# CPPE#
29,33,36,40,41 SUSP# 1 STBY# NC 16 15 CLK_PCIE_EXPR# 18 REFCLK-
C92 C93 CLK_PCIE_EXPR 19
15 CLK_PCIE_EXPR REFCLK+
CPUSB# 10 7 0.1U_0402_16V4Z~N 20
CPPE# GND 2 2 PCIE_RXN4 GND
20 PCIE_RXN4 21 PERn0
EXPR_CPUSB# 9 20 PCIE_RXP4 PCIE_RXP4 22
CPUSB# PERp0
23 GND
18 PCIE_TXN4 24
RCLKEN +3VS_PEC 20 PCIE_TXN4 PETn0
PCIE_TXP4 25
20 PCIE_TXP4 PETp0
P2231NL_QFN20 4.7U_0805_10V4Z~N 26 GND
C +1.5V_CARD Max. 650mA, Average 500mA 27 GND
C
1 1 28 GND
+3V_CARD Max. 1300mA, Average 1000mA 29 GND
C75 C73 30
0.1U_0402_16V4Z~N GND
2 2
FOX_1CX41201_26P_LT-S
CONN@
MDC Conn.
JMDC1

1 GND1 RES0 2
19 HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4 20mil
5 GND2 3.3V 6 +MDC_VCC
19 HDA_SYNC_MDC 7 IAC_SYNC GND3 8
19 HDA_SDIN1 1 2 @ 9 IAC_SDATA_IN GND4 10
R49 33_0402_5% 11 12
19 HDA_RST_MDC# IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC 19
1
C1429
@
GND
GND
GND
GND
GND
GND

22P_0402_50V8J
2
13
14
15
16
17
18

Connector for MDC Rev1.5

ACES_88018-124G
B CONN@ B

+3VALW

1
C748 C749

0.1U_0402_16V4Z 1U_0603_10V4Z
3

2 @
S
@ G
29 MDC_ON# 1 2 2
R735 100K_0402_5% Q51
@ SI2301BDS_SOT23
@
D
W=40mils
1

+MDC_VCC

1
C750 C751

4.7U_0805_10V4Z 0.1U_0402_16V4Z
@ 2 @
A 9/29 follow HEL80's A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXPRESS CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 28 of 45
5 4 3 2 1
 L18
+3VALW +EC_AVCC 2 1
+EC_AVCC
1
+3VALW
2 FBM-11-160808-601-T_0603
Board ID +3VALW
C481
C482
1 1 1 1 1 1 1000P_0402_50V7K~N 0.1U_0402_16V4Z~N
+3VALW

0.1U_0402_16V4Z~N
C281

0.1U_0402_16V4Z~N
C285

0.1U_0402_16V4Z~N
C277

0.1U_0402_16V4Z~N
C493

1000P_0402_50V7K~N
C269

1000P_0402_50V7K~N
C291

2
ECAGND2 1
2 1 2007-09-19 change Brd ID
FBM-11-160808-601-T_0603 L19 R232

2
2 2 2 2 2 2
Ra 47K_0402_5%
@
R405

1
10K_0402_5% AD_BID
1

111
125

2
EC_PME#

22
33
96

67
EC_PME# 18,20

9
U29 R231 C272
Rb 15K_0402_5% 0.1U_0402_16V4Z

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
2

1
R266 0_0402_5%
GATEA20 1 21 1 2
19 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 16
19 KB_RST#
KB_RST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP#
BEEP# 26 M/B rev:0.1; 0.2; 0.3; 1.0
SERIRQ 3 26
20 SERIRQ
LPC_FRAME# 4
SERIRQ# FANPWM1/GPIO12
27 ACOFF Voltage:0.0; 0.4; 0.8; 1.0
19,24 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 38
LPC_AD3 5
19,24 LPC_AD3 LAD3
CLK_PCI_EC LPC_AD2 7 PWM Output C273 1 2 0.01U_0402_16V7K ECAGND
19,24 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
19,24 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 44
1

LPC_AD0 BATT_OVP
R272
19,24 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 44
ADP_I/AD2/GPIO3A 65 ADP_I 38
CLK_PCI_EC 12 AD Input 66 AD_BID
15 CLK_PCI_EC PCICLK AD3/GPIO3B
@ 10_0402_5% R228 PLT_RST# 13 75
7,18,22,24,28,33 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 EC_RST# 37 76 BIST
+3VALW BIST 16
2

EC_SCI# ECRST# SELIO2#/AD5/GPIO43

1 20 EC_SCI# 20 SCI#/GPIO0E
@ C282 47K_0402_5% PCI_CLKRUN# 38
20,27 PCI_CLKRUN# CLKRUN#/GPIO1D
2 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 16
15P_0402_50V8J C268 70 EN_DFAN1
2 KSI[0..7] EN_DFAN1/DA1/GPIO3D EN_DFAN1 4
0.1U_0402_16V4Z DA Output 71 IREF
30 KSI[0..7] IREF/DA2/GPIO3E IREF 38
KSI0 55 72 M_PWROK_EC 1 2
1 KSO[0..15] KSI0/GPIO30 DA3/GPIO3F CHGVADJ 38
KSI1 56 R256 0_0402_5%
30 KSO[0..15] KSI1/GPIO31
KSI2 57
KSI3 KSI2/GPIO32 EC_MUTE#
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# 26
KSI4 59 84
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B VGA_ON
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 VGA_ON 33
+5VALW KSI6 61 PS2 Interface 86 WL_OFF# WL_OFF# 24
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 30
EC_SMB_DA1 R263 2 1 4.7K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 30
KSO1 40
EC_SMB_CK1 R262 2 1 4.7K_0402_5% KSO2
KSO3
KSO4
41
42
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23 SDICS#/GPXOA00 97
R274
SPI_PULLDOWN 2
EN_WOL#
@
1 4.7K_0402_5%
SPI Flash (8Mb*1)
@ C507
43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# 22
+3VS KSO5 2 0_0402_5% SPI_CLK_R
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
VGATE
1 1 2
R419
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 7,20,43
EC_SMB_DA2 R264 2 1 4.7K_0402_5% KSO7 46 SPI Device Interface 0.1U_0402_16V4Z~N
KSO8 KSO7/GPIO27 +3VALW
47 KSO8/GPIO28
EC_SMB_CK2 R265 2 1 4.7K_0402_5% KSO9 48 119 FRD#SPI_SO C314
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI 20mils
49 KSO10/GPIO2A SPIDO/WR# 120 1 2
KSO11 50 SPI Flash ROM 126 SPI_CLK 2 R437 1
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# 0.1U_0402_16V4Z~N 10K_0402_5%
51 KSO12/GPIO2C SPICS# 128
KSO13 52 U37
KSO14 KSO13/GPIO2D FSEL#SPICS# 2
53 KSO14/GPIO2E 1SPI_CS# 1 CS# VCC 8
KSO15 54 73 LCD_DET# LCD_DET# 16 R439 15_0402_5% 2 7
KSO15/GPIO2F CIR_RX/GPIO40 MSEN# FRD#SPI_SO 1 SO HOLD#
PAD T57 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 MSEN# 17 2SPI_SO 3 WP# SCLK
SPI_CLK_R 1
6 2 SPI_CLK
BT_ON# 82 89 FSTCHG 15_0402_5% R275 4 5 15_0402_5% R420
31 BT_ON# KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 38 GND SI
90 BATT_CHG_LED# SPI_SI 1 2 FWR#SPI_SI
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 32
91 CAPSLED# T58 PAD MX25L1605AM2C-12G_SO8 15_0402_5% R438
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED#
44 EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_LOW_LED# 32
MSEN# R309 1 2 10K_0402_5% EC_SMB_DA1 78 93 SCRLED# T56 PAD
44 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
EC_SMB_CK2 79 SM Bus 95 SYSON
4,33 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 28,36,41
4,33 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 43
127 ACIN
AC_IN/GPIO59 ACIN 20,37,38
C251 100P_0402_25V8K

6 SLP_S3# 100 EC_RSMRST#

20 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20
14 SLP_S5# 101 EC_LID_OUT#
+5VS_HD 20 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 20
15 EC_SMI# 102 EC_ON
20 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 30
R271 16 LID_SW# 103 EC_SWI#
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 20
4.7K_0402_5% 17 104 ICH_PWROK
SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK 7,20
TP_DATA 1 2 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16
TP_CLK 1 2 EC_PME# 19 GPIO 106 3G_OFF#
+3VALW 18,20 EC_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 3G_OFF# 24
R270 R2571 2 0_0402_5% 25 107 MDC_ON#
33 VGA_THER# EC_THERM#/GPIO11 GPXO10 MDC_ON# 28
4.7K_0402_5% @ FAN_SPEED1 28 108
4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
30 KILL_ON# KILL_ON# 29
R229 E51_TXD FANFB2/GPIO15
30 EC_TX/GPIO16
KSO1 1 2 47K_0402_5% 31 110 SLP_S4# SLP_S4# 20
KSO2 ON_OFF EC_RX/GPIO17 PM_SLP_S4#/GPXID1 EC_ENBKL
1 2 47K_0402_5% 30 ON_OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 EC_ENBKL 16
R230 PWR_LED# 34 114 USB_EN USB_EN 31
30,32 PWR_LED# PWR_LED#/GPIO19 GPXID3
EC_MUTE# 1 2 10K_0402_5% PAD T59 NUMLED# 36 GPI 115 EC_THERM#
NUMLED#/GPIO1A GPXID4 EC_THERM# 20
116 SUSP#
GPXID5 SUSP# 28,33,36,40,41
R277 117 PBTN_OUT#
GPXID6 PBTN_OUT# 20
Place under open door location XCLKO 1 R278 2 XCLKI 118 LCD_VCC_TEST_EN
@ 20M_0603_5% XCLKI GPXID7 LCD_VCC_TEST_EN 16
122 XCLK1
XCLKO 123 124 C322 1 2 4.7U_0603_6.3V6M
+3VALW XCLK0 V18R
AGND
GND
GND
GND
GND
GND

JECDB1 C270 2 1 0.1U_0402_16V4Z

1 1
2 C292 C297 KB926QFD2_LQFP128
11
24
35
94
113

69

2
1

4
15P_0402_50V8J

15P_0402_50V8J

E51_TXD 3 3
4
OSC

OSC

4
ACES_85205-0400 ECAGND
CONN@
NC

NC
2

X2
32.768KHZ_12.5PF_Q13MC14610002

+3VALW
Q1
APX9132ATI-TRL_SOT23-3

LID_SW# 3 2
GND

LID_SW# VOUT VDD

1

LID Switch
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 29 of 45

hexainf@hotmail.com
GRATIS - FOR FREE
 A B C D E

INT_KBD CONN. JKB1

KSO8 C449 100P_0402_25V8K KSI7 C235 100P_0402_25V8K

+3VALW KSI1 1 KSI3 C239 100P_0402_25V8K KSI6 C236 100P_0402_25V8K

KSI7 1
2
Power Button KSI6 3
2
3
KSO9 C249 100P_0402_25V8K KSI5 C237 100P_0402_25V8K

100K_0402_5%
KSO9 4
KSI4 4 KSI2 C240 100P_0402_25V8K KSO0 C441 100P_0402_25V8K
5 5

R297
KSI5 6
KSI[0..7] KSO0 6 KSI1 C241 100P_0402_25V8K KSO1 C442 100P_0402_25V8K
29 KSI[0..7] 7 7
KSI2 8

1
D15 KSO[0..15] KSI3 8 KSO10 C248 100P_0402_25V8K KSO2 C443 100P_0402_25V8K
29 KSO[0..15] 9 9
2 KSO5 10
ON_OFF 29 10
PWR_ON-OFF_BTN# 1 KSO1 11 KSO11 C247 100P_0402_25V8K KSI4 C238 100P_0402_25V8K
51ON# KSI0 11
3 51ON# 37 12 12
1 KSO2 KSI0 C242 100P_0402_25V8K KSO3 C444 100P_0402_25V8K 1
13 13
CHN202UPT SC-70 KSO4 14
KSO7 14 KSO12 C246 100P_0402_25V8K KSO4 C445 100P_0402_25V8K
15 15
+3VALW KSO8 16 16

1
2 KSO6 17 KSO13 C245 100P_0402_25V8K KSO5 C446 100P_0402_25V8K
KSO3 17
18 18

2
C1418 D13 KSO12 19 KSO14 C244 100P_0402_25V8K KSO6 C447 100P_0402_25V8K
R296 1000P_0402_50V7K~N RLZ20A_LL34 KSO13 19
20 20
4.7K_0402_5% 1 KSO14 KSO15 C243 100P_0402_25V8K KSO7 C448 100P_0402_25V8K
21

2
@ KSO11 21
22 22

1
D KSO10 23

1
23
29 EC_ON
EC_ON 1
R291
2 2
G Q26
KSO15 24
25
24
25
For EMI
0_0402_5% S SSM3K7002FU_SC70-3 26

3
G1
27 G2
ACES_85202-2505L
@CONN

SW/B CONN.

2 2

2-3:ON, 1-2:OFF +5VALW

SW1
Wireless_SW 1BS003-1210L_3P JFN1
4 4
PWR_ON-OFF_BTN#
G2
G1

3 3
3
2
1

PWR_LED# 2 6
29,32 PWR_LED# 26
1 5
5
4

3
2
1

15
+3VS +3VALW
ACES_85201-0405
TP50
@ ME@
1

R12
@ R1131
KILL_ON#

0_0402_5% 100K_0402_5%
2

29 KILL_ON#

3 3

JTP1
Touch PAD/B CONN. 29 TP_CLK
TP_CLK
TP_DATA
1 1
29 TP_DATA 2 2
3 3
4 4
+5VS 5 5
1 6 6
7 GND
C300 1 1 8
0.01U_0402_16V7K @ @ GND
2

C1416
ACES_85201-06051

3
100P_0402_25V8K C1417
@CONN
2 2 D24
SM05T1G_SOT23-3~D

100P_0402_25V8K
@

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 30 of 45
A B C D E
 CM1293-04SO_SOT23-6
+5VALW +USB_AS
0.1U_0402_16V4Z USB_P1 1 4 USB_P0
CH1 CH4
1
80 mils U12

1
1 8 + C434 C223
GND OUT R155
2 IN OUT 7 2 Vn Vp 5 +USB_AS
3 6 150U_B2_6.3VM_R45M 30K_0402_5%
USB_EN# IN OUT 2
1 4 EN# OC# 5
C228

1 2
RT9711BPS SO 8P USB_N1 3 6 USB_N0
0.1U_0402_16V4Z D CH2 CH3
2 USB_EN# Q14 @ D19
2
G SSM3K7002FU_SC70-3

1
USB_OC#0 20 S

3
R154
100K_0402_5% +USB_AS

W=80mils JUSB1

2
USB20_N0 2 1 1
20 USB20_N0 VCC
R1 0_0402_5% USB_N0 2
USB_P0 D-
3 D+
USB20_P0 2 1 4
20 USB20_P0 GND
R3 0_0402_5%
+USB_CS 5
+5VALW GND1
6 GND2
7 GND3
8 GND4
80 mils 1
U14
GND OUT 8 SUYIN_020173MR004G565ZR
2 IN OUT 7 CONN@
3 IN OUT 6

1
1 USB_EN# 4 5
C253 EN# OC# R38
RT9711BPS SO 8P 30K_0402_5% +USB_AS
0.1U_0402_16V4Z
2 JUSB2
W=80mils

2
USB20_N1 2 1 1
20 USB20_N1 VCC
R54 0_0402_5% USB_N1 2
USB_OC#3 20 D-
USB_P1 3
USB20_P1 D+
1 2 USB_OC#2 20 20 USB20_P1 2 1 4 GND
R44 0_0402_5% R62 0_0402_5%

1
D
5 GND1
USB_EN# USB_EN# 2 Q13 6
G SSM3K7002FU_SC70-3 GND2
7 GND3
S 8

3
GND4
+USB_BS/+USB_CS =80mils
+USB_BS SUYIN_020173MR004G565ZR
+5VALW ME@
+USB_BS +USB_CS

80 mils 1
U13
GND OUT 8 1
JUSB3
1
2 IN OUT 7 2 2
3 6 USB20_N8 3
IN OUT 20 USB20_N8 3
1 USB_EN# 4 5 USB20_P8 4
EN# OC# 20 USB20_P8 4
C64 5 5

1
RT9711BPS SO 8P 6
0.1U_0402_16V4Z R36 6
7 7
2 30K_0402_5% 8 8
USB20_N9 9
20 USB20_N9 9
USB_OC#1 20 USB20_P9 10
20 USB20_P9

2
10
11 11
D29 12 12
+5VS 13
USB20_P5 G1
1 GND IO2 3 14 G2

1
USB20_N5 D E&T_3703-E12N-03R
2 IO1 VIN 4 +5VS

1
USB_EN# 2 Q8 ME@
G SSM3K7002FU_SC70-3 R605
PRTR5V0U2X_SOT143-4
S

3
@ 10K_0402_5%
Bluetooth

2
Fingerprint 32 BT_LED#
BT_LED# JBT1

BT_ACTIVE 1
24 BT_ACTIVE 2

1
JFP1 D WLAN_ACTIVE
24 WLAN_ACTIVE 3
USB20_P5 1 Q43 2 BTON_LED
20 USB20_P5 1 4
USB20_N5 2 2N7002_SOT23 G 20 USB20_N4 USB20_N4
20 USB20_N5 2 5
3 S 20 USB20_P4 USB20_P4

3
3 6

1
4 4 7
5 +3VS +3VALW R606
+3VS 5 +BT_VCC 8
+5VS 6 6
7 10K_0402_5% ACES_87212-0800
GND

1
8 @

2
GND R8 R9
ACES_85201-06051 0_0402_5% 0_0402_5%
CONN@
Camera

2
+5VS

1
C759 C760
1 1
C30 C29 0.1U_0402_16V4Z 1U_0603_10V4Z

3
2
S
G
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1 2 2
2 2 29 BT_ON#
R755 100K_0402_5% Q56
JCAM1 SI2301BDS_SOT23
+5VALW R13 1
USB20_N2 USB_N2 1 D
20 USB20_N2 2 1 2 W=40mils

1
USB20_P2 0_0402_5% USB_P2 2
20 USB20_P2 2 1 3 3 +BT_VCC
2

R15 0_0402_5% 4
R1226 4
5 5 1
2

10K_0402_5% 6 C761 C762

GND1
7 GND2
D1 4.7U_0805_10V4Z 0.1U_0402_16V4Z
1

USB_EN# @ ACES_88266-05001 2
PSOT24C_SOT23 CONN@
1

D
1

29 USB_EN USB_EN 2 Q4
G SSM3K7002FU_SC70-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BlueTooth/FP/Felcia
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 31 of 45

hexainf@hotmail.com
GRATIS - FOR FREE
 5 4 3 2 1

D D

+5VALW R93 White

2.2K_0402_5%
1 2 2 1 LED3 PWR_LED# PWR_LED# 29,30
19-213A/T1D-CP2Q2HY/3T 0603 WHITE

C C

R710 LED2 Amber

3.3K_0402_5%
+5VALW 1 2 4 3 BATT_LOW_LED#
A
BATT_LOW_LED# 29
R711
3.3K_0402_5%
+5VALW 1 2 2 1 BATT_CHG_LED#
B
BATT_CHG_LED# 29
Blue
HT-297UD/CB _BLUE/AMB_0603

R708 LED5 Amber

3.3K_0402_5%
+5VS 1 2 4 3 BT_LED#
A
BT_LED# 31
R709
3.3K_0402_5%
+5VS 1 2 2 1 LED_WLAN#
B
LED_WLAN# 24
Blue
HT-297UD/CB _BLUE/AMB_0603

B B

A A

Security Classification Compal Secret Data

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 32 of 45
5 4 3 2 1
 5 4 3 2 1

PEG_NRX_GTX_N[0..15]
PEG_NRX_GTX_N[0..15] 9
PEG_NRX_GTX_P[0..15]
PEG_NRX_GTX_P[0..15] 9
PEG_NTX_GRX_N[0..15]
PEG_NTX_GRX_N[0..15] 9
PEG_NTX_GRX_P[0..15]
PEG_NTX_GRX_P[0..15] 9

JP57B
D D
PEG_NRX_GTX_N1 109 110
JP57A PEG_NRX_GTX_P1 PEX_RX1# GND PEG_NTX_GRX_N1
111 PEX_RX1 PEX_TX1# 112
113 114 PEG_NTX_GRX_P1
PEG_NRX_GTX_N0 GND PEX_TX1
B+ 1 PWR_SRC 1V8RUN 2 +1.8VS 115 PEX_RX0# GND 116
3 4 PEG_NRX_GTX_P0 117 118 PEG_NTX_GRX_N0
PWR_SRC 1V8RUN PEX_RX0 PEX_TX0# PEG_NTX_GRX_P0
5 PWR_SRC 1V8RUN 6 119 GND PEX_TX0 120
7 8 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN 15 CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
9 10 CLK_PCIE_VGA 123 124 VGA_TV_CRMA
PWR_SRC 1V8RUN 15 CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr VGA_TV_CRMA
11 PWR_SRC 1V8RUN 12 125 CLK_REQ# GND 126
13 14 127 128 VGA_TV_LUMA
PWR_SRC 1V8RUN 7,18,22,24,28,29 PLT_RST# PEX_RST# TV_Y/HDTV_Y VGA_TV_LUMA
15 16 VGA_ON 129 130
PWR_SRC RUNPWROK SUSP# 28,29,36,40,41 29 VGA_ON RSVD GND
17 18 +5VS 131 132 VGA_TV_COMPS
GND 5VRUN RSVD TV_CVBS/HDTV_Pb VGA_TV_COMPS
19 GND GND 20 4,29 EC_SMB_DA2 133 SMB_DAT GND 134
21 22 135 136 VGA_CRT_R VGA_CRT_R 17
GND GND 4,29 EC_SMB_CK2 SMB_CLK VGA_RED
23 GND GND 24 29 VGA_THER# 137 THERM# GND 138
17 VGA_HSYNC VGA_CRT_HSYNC 139 140 VGA_CRT_G VGA_CRT_G 17
VGA_CRT_VSYNC VGA_HSYNC VGA_GRN
17 VGA_VSYNC 141 VGA_VSYNC GND 142
17 VGA_DDCCLK VGA_DDC_CLK 143 144 VGA_CRT_B VGA_CRT_B 17
VGA_DDC_DATA DDCA_CLK VGA_BLU
17 VGA_DDCDATA 145 DDCA_DAT GND 146
147 IGP_UCLK# LVDS_UCLK# 148
149 IGP_UCLK LVDS_UCLK 150
PEG_NRX_GTX_N15 25 26 151 152
PEG_NRX_GTX_P15 PEX_RX15# PRSNT2# PEG_NTX_GRX_N15 CLK_NVSS_27M GND GND
27 PEX_RX15 PEX_TX15# 28 15 CLK_NVSS_27M 153 RSVD LVDS_UTX3# 154
29 30 PEG_NTX_GRX_P15 CLK_NV_27M 155 156
GND PEX_TX15 15 CLK_NV_27M RSVD LVDS_UTX3
PEG_NRX_GTX_N14 31 32 157 158
PEG_NRX_GTX_P14 PEX_RX14# GND PEG_NTX_GRX_N14 RSVD GND
33 PEX_RX14 PEX_TX14# 34 159 IGP_UTX2# LVDS_UTX2# 160
35 36 PEG_NTX_GRX_P14 161 162
PEG_NRX_GTX_N13 GND PEX_TX14 IGP_UTX2 LVDS_UTX2
37 PEX_RX13# GND 38 163 GND GND 164
C PEG_NRX_GTX_P13 39 40 PEG_NTX_GRX_N13 165 166 C
PEX_RX13 PEX_TX13# PEG_NTX_GRX_P13 IGP_UTX1# LVDS_UTX1#
41 GND PEX_TX13 42 167 IGP_UTX1 LVDS_UTX1 168
PEG_NRX_GTX_N12 43 44 169 170
PEG_NRX_GTX_P12 PEX_RX12# GND PEG_NTX_GRX_N12 GND GND
45 PEX_RX12 PEX_TX12# 46 171 IGP_UTX0# LVDS_UTX0# 172
47 48 PEG_NTX_GRX_P12 173 174
PEG_NRX_GTX_N11 GND PEX_TX12 IGP_UTX0 LVDS_UTX0
49 PEX_RX11# GND 50 175 GND GND 176
PEG_NRX_GTX_P11 51 52 PEG_NTX_GRX_N11 177 178 VGA_LVDSAC- VGA_LVDSAC- 16
PEX_RX11 PEX_TX11# PEG_NTX_GRX_P11 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# VGA_LVDSAC+
53 GND PEX_TX11 54 179 IGP_LCLK/DVI_B_CLK LVDS_LCLK 180 VGA_LVDSAC+ 16
PEG_NRX_GTX_N10 55 56 181 182
PEG_NRX_GTX_P10 PEX_RX10# GND PEG_NTX_GRX_N10 DVI_B_HPD/GND GND
57 PEX_RX10 PEX_TX10# 58 183 RSVD LVDS_LTX3# 184
59 60 PEG_NTX_GRX_P10 185 186
PEG_NRX_GTX_N9 GND PEX_TX10 RSVD LVDS_LTX3
61 PEX_RX9# GND 62 187 GND GND 188
PEG_NRX_GTX_P9 63 64 PEG_NTX_GRX_N9 189 190 VGA_LVDSA2- VGA_LVDSA2- 16
PEX_RX9 PEX_TX9# PEG_NTX_GRX_P9 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# VGA_LVDSA2+
65 GND PEX_TX9 66 191 IGP_LTX2/DVI_B_TX2 LVDS_LTX2 192 VGA_LVDSA2+ 16
PEG_NRX_GTX_N8 67 68 193 194
PEG_NRX_GTX_P8 PEX_RX8# GND PEG_NTX_GRX_N8 GND GND VGA_LVDSA1-
69 PEX_RX8 PEX_TX8# 70 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 VGA_LVDSA1- 16
71 72 PEG_NTX_GRX_P8 197 198 VGA_LVDSA1+ VGA_LVDSA1+ 16
PEG_NRX_GTX_N7 GND PEX_TX8 IGP_LTX1/DVI_B_TX1 LVDS_LTX1
73 PEX_RX7# GND 74 199 GND GND 200
PEG_NRX_GTX_P7 75 76 PEG_NTX_GRX_N7 +3VALW 201 202 VGA_LVDSA0- VGA_LVDSA0- 16
PEX_RX7 PEX_TX7# PEG_NTX_GRX_P7 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# VGA_LVDSA0+
77 GND PEX_TX7 78 +5VALW 203 IGP_LTX0/DVI_B_TX0 LVDS_LTX0 204 VGA_LVDSA0+ 16
PEG_NRX_GTX_N6 79 80 VGA_PWGOD# 205 206
PEX_RX6# GND 36 VGA_PWGOD# DVI_A_HPD GND
PEG_NRX_GTX_P6 81 82 PEG_NTX_GRX_N6 207 208 VGA_DAT_LCD VGA_DAT_LCD 16
PEX_RX6 PEX_TX6# PEG_NTX_GRX_P6 DVI_A_CLK# DDCC_DAT VGA_CLK_LCD
83 GND PEX_TX6 84 209 DVI_A_CLK DDCC_CLK 210 VGA_CLK_LCD 16
PEG_NRX_GTX_N5 85 86 211 212 ENVDD
PEX_RX5# GND GND LVDS_PPEN VGA_LVDDEN 16
PEG_NRX_GTX_P5 87 88 PEG_NTX_GRX_N5 213 214
PEX_RX5 PEX_TX5# PEG_NTX_GRX_P5 DVI_A_TX2# LVDS_BL_BRGHT VGA_ENBKL
89 GND PEX_TX5 90 215 DVI_A_TX2 LVDS_BLEN 216 VGA_ENBKL 16
PEG_NRX_GTX_N4 91 92 217 218
PEG_NRX_GTX_P4 PEX_RX4# GND PEG_NTX_GRX_N4 GND DDCB_DAT
93 PEX_RX4 PEX_TX4# 94 +1.5VS 219 DVI_A_TX1# DDCB_CLK 220
95 96 PEG_NTX_GRX_P4 221 222
B PEG_NRX_GTX_N3 GND PEX_TX4 DVI_A_TX1 2V5RUN B
97 PEX_RX3# GND 98 223 GND GND 224
PEG_NRX_GTX_P3 99 100 PEG_NTX_GRX_N3 225 226 +3VS
PEX_RX3 PEX_TX3# PEG_NTX_GRX_P3 DVI_A_TX0# 3V3RUN
101 GND PEX_TX3 102 227 DVI_A_TX0 3V3RUN 228
PEG_NRX_GTX_N2 103 104 229 230
PEG_NRX_GTX_P2 PEX_RX2# GND PEG_NTX_GRX_N2 GND 3V3RUN
105 PEX_RX2 PEX_TX2# 106
107 108 PEG_NTX_GRX_P2
GND PEX_TX2
ACES_88990-2D08

ACES_88990-2D08

B+ +1.8VS +3VS +5VS

2 1 1 1 1 1
C1443 C424 C425 C426 C427 C429

0.1U_0603_25V7K 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

VGA@ 1 VGA@ 2 2 VGA@ VGA@ 2 2 VGA@ 2 VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4841P
Date: Monday, December 15, 2008 Sheet 33 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

D H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 D

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

H_3P0

1
H14 H15 H16 H17 H18
HOLEA HOLEA HOLEA HOLEA HOLEA

H_3P7
1

1
H19 H20 H21 H22
HOLEA HOLEA HOLEA HOLEA
H_4P2
1

1
C C

H23 H24 H25 H26 H27 H28 H29 H30

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

H_3P2
1

1
H31
HOLEA

H_5P6
1

H33
HOLEA
H_4P4 H_3P1N FD1 FD2 FD3 FD4
1

@ @ @ @

1
B B

H34
HOLEA
1

H35 H36
HOLEA HOLEA
1

H37
HOLEA
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screws
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 34 of 45
5 4 3 2 1
 A

KAL80 POWER UP SEQUENCE

ACIN/BATT-IN
51ON#
(only BATT-IN)

← 126ms →
5VALW/3VALW
644ms
RSMRST# ←→
Suspend Clock (32KHz) SUSCLK

→ ←←→
ICH9 internal clock 864us 244ms
ON/OFF#

EC_ON 360ms

PWRBTN_OUT# ←→
1.59ms ←
→ 2.74ms
SYSON#

1.8V ←250ms
→
SLP_S5# ← → 30.6us
SLP_S4# ←→30us
SLP_S3# ←→
SUSP# ← 3.88s → 888us
+5VS ←→ 104us
+3VS
←→ ←112us
→
+1.5VS
2.02ms
+0.9VS →1.46ms
←
VCCP ←→ 24.1ms
VR_ON ← → 1.20ms
CPU_CORE ←→ 5.26ms
This signal is
VGATE ←→
asserted high when
A both SLP_S3# and A
VRMPWRGD are high CK_PWRGD
1.03ns
CLK_MCH_BCLK ←
→
ICH_PWROK ←114ms→ 1.20ms
PCI_RST# ←→
1.06ms ←→
H_PWRGOOD

H_RESET# ←2.20ms→

Title
<Title>

Size Document Number Rev

CustomLA-4841P 1.0

hexainf@hotmail.com A
Date: Monday, December 15, 2008 Sheet 35 of 45

GRATIS - FOR FREE

 A B C D E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer +1.8V to +1.8VS Transfer

+3VALW +3VS
B+_BIAS 4A +5VALW +5VS 8A +1.8V +1.8VS
4.7A
U40 B+_BIAS
8 1 10U_0805_10V4Z~N U39 U41
D S

1
7 2 8 1 8 1 10U_0805_10V4Z~N
D S D S D S

47K_0402_5%
R198 1 6 3 7 2 7 2
D S D S D S

R1227
5 D G 4 1 1 1 6 D S 3 1 6 D S 3
330K_0402_5% C271 C465 C256 C278 5 4 1 1 VGA@ 5 4 1 1
2 SI4800DY_SO8 D G C284 C283 C727 D G C728 C697
1 2 10U_0805_10V4Z~N SI4800DY_SO8 SI4800DY_SO8 1
VGA@

1
2 2 2 10U_0805_10V4Z~N 10U_0805_10V4Z~N 2 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N
RUNON 3VS_GATE 2 2 VGA@ 2 2
1 2 VGA@ VGA@
R197 1 RUNON 1 2 1 5VS_GATE 0.1U_0402_16V4Z~N
100K_0402_5% 0.1U_0402_16V4Z~N R267 C279
C264 47K_0402_5%
1

D 0.01U_0402_25V7K~N 0.01U_0402_25V7K~N 1.8VS ON 1 1.8VS_GATE

2
SUSP 2 2 R608
2 1
G Q18 100K_0402_5%
S SSM3K7002FU_SC70-3 VGA@ C696
3

1
D 0.01U_0402_25V7K~N
VGA_PWGOD# 2 VGA@
33 VGA_PWGOD# 2
G Q48
S SSM3K7002FU_SC70-3

3
SUSP 1 R665 2 VGA@
+CPU_CORE 1 2 +VCCP @ 0_0402_5%
C211 0.1U_0402_16V4Z~N

2 +3VALW 2
1

R409

100K_0402_5%
2

SYSON#
1

D
SYSON 2 Q42
28,29,41 SYSON
G SSM3K7002FU_SC70-3
S
3
2

R365
10K_0402_5%
1

+5VALW
1

R340
3 3
100K_0402_5%
2

27,42 SUSP SUSP

1

D
SUSP# 2 Q32
28,29,33,40,41 SUSP#
G SSM3K7002FU_SC70-3
2

S
3

R338
10K_0402_5%
1

Discharge circuit-1 +1.8V +0.9VS +5VS +3VS +1.5VS

1

1
R133 R351 R391 R383 R382

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

2

2
1

1
D D D D D
SYSON# 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2
G G G G G
4 S Q12 S Q33 S Q39 S Q38 S Q37 4
3

3
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

SYSON -> SUSP# -> VGA_ON->VGA_PWGOD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4841P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 36 of 45
A B C D E
 5 4 3 2 1

PC1 PR1

@
2200P_0402_50V7K~D @ 56K_0402_5%~D
ADPIN VIN
1 2 1 2

PJPDC1 PL1
SMB3025500YA_2P PR2
1 1 1 2 1M_0402_1%~N
1 2
VIN
VS VIN
2

0.01U_0402_25V7K~D
2

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
D D

1
100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
PR5 PR4

1
PC3

PC5

PC7

PC8
3 3 PR3 10K_0402_5%~D 1K_0402_5%~D

PC2

PC4

PC6
82.5K_0402_1%~D 1 2 ACIN 20,29,38

2
4 4 PR6

2
8
22K_0402_1%~D
PU1A
5 N41 1 2 VinDe_IN3

P
+ VinDe_Out
O 1

19.6K_0402_1%~D
0.1U_0402_16V7K~D
6 VinDe_Ref
2 -

1
1

1
PC10

PR8
LM393DR_SO8 PR7

4
ACES_88290-044G PC9 PD1 10K_0402_5%~D
@ VIN 1000P_0402_50V7K~D RLZ4.3B_LL34

2
2

2
32.3

2
PD2 PR9
10K_0402_5%~D
2 1
RLS4148_LL34-2 RTCVREF

1
3.3V

8
1

1
PU1B
5

P
PR10 PR14 +
O 7
PJP1 68_1206_5% 68_1206_5% 6 -

G
PD3 @ JUMP_43X118
2 1 1 1 LM393DR_SO8
2 2 Vin Detector

4
BATT+
RLS4148_LL34-2
VS
Max. typ. Min.
C
PQ1
L-->H 18.234 17.841 17.449 C

CHGRTCP 3 TP0610K-T1-E3_SOT23-3
1 H-->L 17.597 17.210 16.813
0.22U_1206_25V7K
1

PR11
PC11

100K_0402_5%~D PC12
0.1U_0603_25V7K~D
2

PR12
2

22K_0402_5%~D
1 2 51ON#_Gate
30 51ON#
1

PR13
APL5156-33DI-TRL_SOT89-3 200_0805_5%
RTCVREF
PU3
2

3 VOUT VIN 2

GND
4.7U_0805_6.3V6K~D
1
PC13

B 1 B
PC14
2

1U_0805_25V4Z~D
2

PJP2
@ JUMP_43X118
+5VALWP 1 1 2 2 +5VALW

PJP4
@ JUMP_43X118
1 1 2 2

PJP6 PJP7
@ JUMP_43X118 @ JUMP_43X118
+3VALWP 1 1 2 2 +3VALW +0.9VSP 1 1 2 2 +0.9VS

PJP8
@ JUMP_43X118
1 1 2 2 +1.5VS
+1.5VSP

A A
PJP10
@ JUMP_43X118 PJP11
1 1 @ JUMP_43X118
+VCCPP 2 2 +VCCP
+1.8VP 1 1 2 2 +1.8V
PJP12
@ JUMP_43X118 PJP13
1 1 @ JUMP_43X118 Security Classification Compal Secret Data
2 2
1 1 2 2 Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
DCIN / Precharge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 37 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 A B C D E

PQ4 PQ5 B+
VIN FDS4435BZ_SO8 FDS4435BZ_SO8
PR21
8 1 1 8 0.015_2512_1%
D S S D

0.01U_0402_25V7K~D
7 2 2 7 PJP14
D S S D CHG_B+
6 D S 3 3 S D 6 1 4 2 2 1 1

1
5 D G 4 4 G D 5

2
3.3_1210_5%~D

PC25

PC21

PC22

PC26

PC19
2 3 @ JUMP_43X118 PR22

1
PC23 100K_0402_1%~D

2
PR23

0.01U_0402_25V7K~D

1
2

100K_0402_1%~D

CHGEN#

2
1

1000P_0402_50V7K~D

1000P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1 PC15 PC24 PC16 1

PVCC

1
2

5
6
7
8

1
PC20

PR24
0.01U_0603_50V7K~D 0.1U_0402_16V7K~D PU4 0.1U_0805_25V7K

1 2

1
/BATDRV

3.3_1210_5%~D
1 2 1 28 1 2 PQ6
CHGEN PVCC

2
1

4
3
2
1
PR26
PR27 AO4466_SO8

2
PC17 PC18 2.2_0603_5%~D PQ7

S
S
S
G
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D 27 BTST 1 2 4 FDS4435BZ_SO8

2
BTST

2
2 PR25

D
D
D
D
340K_0402_1%~D ACN 2 26 DH_CHG
ACN HIDRV
2

ACP 3

3
2
1

5
6
7
8
PC27 ACP PR28

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL3 0.02_2512_1%
1

ACDET ACDRV PH PD7 10U_LF919AS-100M-P3_4.5A_20% BATT+

5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M~D
ACSET RLS4148_LL34-2 PC28 PR29

REGN
2 3

2
PR31 0.1U_0603_25V7K~D 4.7_1206_5%~D

5
6
7
8

PC33
PR30 56.2K_0402_1%~D

10U_1206_25V6M~D
680P_0603_50V7K~D
54.9K_0402_1% 1 2 6 PQ8
+3VALW

PC32
ACSET

2
24

2
REGN

1
AO4712_SO8

PC31
PR32 PC30

1
PC29 100K_0402_1%~D 1U_0603_10V6K~D 4
0.01U_0402_25V7K~D

2
2

2
90W adapter 1 2ACOP 7 ACOP
PR33 PC34 23 DL_CHG

3
2
1
340K_0402_1%~D 0.47U_0603_16V7K~N LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3A CP setting
1

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=4.27A PGND 22
OVPSET 8 PC35
2 OVPSET 0.1U_0402_16V7K~D 2
Input OVP : 22.3V
1 2
Input UVP : 16.98V 9 AGND LEARN 21 ACOFF 29
2

1
Fsw : 300KHz PR34
54.9K_0402_1% VREF PC36 PC37
20 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

2
CELLS
1

10 VREF

2
PQ9

1
SI2301BDS-T1-E3_SOT23-3 PC38 PR87
1U_0603_10V6K~D 0_0402_5%~D
PR35 @ 19 SRP

2
100K_0402_1%~D SRP

1
1 2GATE 2 11 VDAC SRN 18 SRN
PR86
+3VALW 1 2 BAT 17
1

0_0402_5%~D

1
PC40 VADJ 12
0.1U_0603_25V7K~D VADJ PC39
2

ACSET 0.1U_0603_25V7K~D

2
TP 29
ACGOOD# 13 ACGOOD ICHG setting RTCVREF VREF
PR37
SRSET 16 2 1 IREF 29

2
/BATDRV 14 47K_0402_1%~D @
BATDRV

1
@

1
PR38 PR39 PR40
15 IADAPT
1 2 100K_0402_1%~D PC41 100K_0402_1%~D 100K_0402_1%~D
IADAPT @0.01U_0402_25V7K~D

1
BQ24751ARHDR_QFN28_5X5 PR42

2
3 10_0603_5%~D 3
ACIN 20,29,37
COIN RTC Battery

1
D
29 ADP_I ACGOOD# 2 PQ11
G SSM3K7002F_SC59-3

1
PJP15 IREF Current S

3
+COINCELL 1 PC42 @
1 100P_0402_50V8J~D
2

2
2
3 G1 0.486V 0.5A
4 @
G2
SUYIN_060003FA002G201NL 2.916V 3A

REGN
VREF VREF
PR43
PQ12 VREF
1

2
B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 GATE
B+_BIAS
PR44 PR45 PR46
470K_0402_5%~D

100_0805_5%~D @ 0_0402_5%~D 200K_0402_1%~D 100K_0402_1%~D

1
0.1U_0805_25V7M~N

PR48
2

1
+5VALW 210K_0402_1%~D D
2

1
PR47

PC44 29 CHGVADJ 1 2 VADJ PR49 2 PQ13

100K_0402_1%~D G SSM3K7002F_SC59-3 CHGEN#
1

S
2

3
1

1
PR50 D D
1
1
220K_0402_5%

1SS355_SOD323-2

PD9 499K_0402_1%~D ACOFF 1 2 2 PQ14 29 FSTCHG 2 PQ15

2

G SSM3K7002F_SC59-3 G SSM3K7002F_SC59-3
1
PR51

PC45 S S
2

3
0.1U_0402_16V7K~D
4 PR52 4
2

340K_0402_1%~D
1

D
2

2 PQ16
0.1U_0603_25V7K~D

G RHU002N06_SOT323-3
220K_0402_5%

S CHGVADJ Battery Voltage/per cell

3
2
1
PC46

PR53

0V 3V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
2

Charger
1

3.3V 4.2V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
KFW11 1.0

Date: Monday, December 15, 2008 Sheet 38 of 45

A B C D E
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJP16 PR54
@ JUMP_43X118 0_0805_5%
1 1 2 2 1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D
4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
VL

5
6
7
8
PC47

PC48

PC49

8
7
6
5

1
PC52
PQ18

PC50

PC51
D PQ17 D

1U_0603_10V6K~D
AO4466_SO8

2
2
AO4466_SO8

2
PC53

4.7U_0805_6.3V6K~D
4

1
PC54
4 0.1U_0603_25V7K~D

PC55
1
+5VALWP

3
2
1
1
2
3
PL4

7
PL5 PU5 PC56 2 1
1 2 1U_0603_10V6K~D 4.7UH_PCMC063T-4R7MN_5.5A_20%

V5FILT

LDO
VIN
+3VALWP

4.7_1206_5%~D
4.7UH_PCMC063T-4R7MN_5.5A_20% 33 19 1 2
TP V5DRV

5
6
7
8

1
1

8
7
6
5

PR57
680P_0603_50V7K~D 4.7_1206_5%~D
DH3 26 15 DH5 PQ20
DRVH2 DRVH1

PR56
PQ19 PR55 PR58
0_0402_5%~D AO4712_SO8 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
VBST2 VBST1
2

1 0_0603_5%~D
0_0603_5%~D

2
2

2
PR59

61.9K_0402_1%~D
4

2
PC57 + 4 PC58 PC59

2
680P_0603_50V7K~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

1
1

PR60
330U_D3L_6.3VM_R25M LX3 25 16 LX5 1
1

2 LL2 LL1

PC60

PC61
3
2
1

2
+ PC62

1
2
3
DL3 23 18 DL5 330U_D3L_6.3VM_R25M

1
DRVL2 DRVL1
2
10K_0402_1%~D
2

PGND 22

2
PR61

FB3 30 VOUT2

10K_0402_1%~D
PR62
C C

VOUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 VREF2
PC63 0.22U_0603_10V7K~D
VSW 9
8 LDOREFIN @ PR63 0_0402_5%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical) SKIPSEL 29 6237_SKIP 2 1 VL
PR64 0_0402_5%~D
1 2
3.3VALWP PD10 PR65
20 NC PGOOD2 28

VS RLZ5.1B_LL34 100K_0402_1%~D
POK 20
1 2 1 2 EN_LDO 4 13 PR67
Imax=6A EN_LDO PGOOD1
2
200K_0402_5%~D

255K_0402_1%~D
2
PR66

PC64 6237_EN1 14 12 ILM1 2 1

0.22U_0603_25V7-K EN1 TRIP1
Iocp=9A PR68

TONSE
VREF3
1

6237_EN2 27 31 ILIM2 2 1

GND
1

EN2 TRIP2
Fsw=300kHz

2
255K_0402_1%~D

2
B B

0_0402_5%~D
@ PR69 SN0806081RHBR_QFN32_5X5

21
VL 0_0402_5%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
806K_0603_1%

PR70
2

6237_NC

6237_TON
1
PR71

2VREF_ISL6237 1
PR73

1
PR72
@ 47K_0402_5%~D
PC65
5VALWP
1

2 1 1 2 PR74

1U_0603_10V6K~D

2
44 MAINPWON
@
Imax=6A

2VREF_ISL6237
0_0402_5%~D
0.047U_0402_16V7K~N

2
PC66 0_0402_5%~D
1

1
2

0.047U_0603_16V7K~D

Iocp=9A
PC67
2

PQ21
TP0610K-T1-E3_SOT23-3
@
Fsw=400kHz
1 3

PD11
1 2
1SS355_SOD323-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+3VALWP, +5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 39 of 45

hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

D D

PJP17
@ JUMP_43X118
1 1 6268_B+
B+ 2 2
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

10U_1206_25V6M~D
PHASE_1.5V
1.5VSP

10U_1206_25V6M~D
PC68

1
UG_1.5V

PC69
PR75 PR76
6268_1.5V 1 2 1 2 1 2 Imax=3.5A

2
@
10K_0402_1%~D 0_0603_5%~D PC70
+5VS
@
0.1U_0603_25V7K~D Iocp=6A

1
BOOT_1.5V
PR77

5
6
7
8
0_0603_5%~D Fsw=294kHz

16

15
8

1
PR78 4.7_0603_5%~D

2
1 2 6268_1.5V PQ22

PHASE

BOOT
UG
GND

PGOOD
AO4466_SO8
PC71 4
C 3 VIN PVCC 14 1 2 C

2.2U_0603_6.3V6K~D

3
2
1
6268_1.5V 4 VCC LG 13 LG_1.5V PL6
4.7U_D104C-919AS-4R7N_5.2A_20%
+1.5VSP

1
1 2 +1.5VSP
PC72

2
2.2U_0603_6.3V6K~D 12 1

2
PGND

5
6
7
8
PR79

1
PR80 4.7_1206_5%~D + PC73
0_0402_5%~D PQ23 PC74 220U_6.3V_M
1 2 5 11 ISEN_1.5V
1 2 AO4712_SO8 4.7U_0805_6.3V6K~D

2 1

2
28,29,33,36,41 SUSP# EN ISEN 2

COMP
PR81 PC76

FSET
4
1

2
@ PC75 5.11K_0402_1%~D 680P_0603_50V8J~D

VO
FB
PR82

1
0.1U_0402_16V7K~D PU6 2K_0402_1%~D
2

10
ISL6268CAZ-T_SSOP16

3
2
1

1
1
22P_0402_50V8J~D
1
PR83

1
PC77

2200P_0402_50V7K~D

1
49.9K_0402_1%~D

2
PC78
PR84 0.01U_0402_25V7K~D

2
1
PC79
45.3K_0402_1%~D

1
PR85

2
1.33K_0402_1%~D

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
1.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 40 of 45
5 4 3 2 1
 5 4 3 2 1

D D

PC98

1
PC97 1U_0402_6.3V6K~D

1
1U_0402_6.3V6K~D

2
2
PR108 PR109
+5VALWP 2 1 1 2 +5VALWP

2
2.2_0603_1%~D 2.2_0603_1%~D
PR110
PC99
28,29,33,36,40 SUSP# 2 1 0.01U_0402_25V7K~D

1
PJP19 @
@ JUMP_43X118
0_0402_5%~D

1
1 1 PC100 PC101
B+ 2 2 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
ISL6228_B+
680P_0402_50K X7R~D
470P_0402_50V8J~D

2
1

+5VALWP
PC102

PC103

ISL6228_B+ 2 PR111 1 2 PR112 1 ISL6228_B+

2

10_0603_1% 10_0603_1%

1
PR113

1K_0402_1%~D

2
@ PC105

2
1000P_0402_50V7K~D PR115

1
PR114 22K_0402_1%~D
1000P_0402_50V7K~D 681_0402_1%~D PR116 PC104 18K_0402_1%~D
C 90.9K_0402_1%~D 1000P_0402_50V7K~D C
PR117

1
PC106
2 1 1 2

1
PR118

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1%~D GND_T

2
PR120
PR119 PR121 681_0402_1%~D
1 2 8 28 2 1 +5VALWP 34K_0402_1%~D 1000P_0402_50V7K~D
FB1 PGOOD2 PR122
PC107
12.1K_0402_1%~D 2 1 1 2

1
1K_0402_1%~D
ISL6228_B+ @ PR123
9 27 FB2_+1.8VP 1 2
VO1 FB2
68K_0402_1%~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

8
7
6
5
PC109

PC110

PC108 PQ29 PR124

.01U_0402_16V7K~D FDS8884_SO8 10 26 1 2
2

OCSET1 VO2
1 2
12.1K_0402_1%~D
4
2

PR125 11 25
12.1K_0402_1%~D EN1 PU8 OCSET2 PR126
0_0402_5%~D
1
2
3

ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B+
1

PL8 SYSON 28,29,36

+VCCPP 1 2 LX_VCCPP 12 24 .01U_0402_16V7K~D

PHASE1 EN2 PC111
220U_D2_4VM

220U_D2_4VM

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

5
6
7
8

1
PC112

PC113
1.8U_D104C-919AS-1R8N_9.5A_30% 1 2 PC114
8
7
6
5

@1 1 PR127 PQ30 1 2
4.7_1206_5%~D PQ31 @ 0.01U_0402_25V7K~D FDS8884_SO8
D
D
D
D

2
+ + FDS6670AS_NL_SO8
PC115

PC116

UG_VCCPP 13 23
UGATE1 PHASE2

2
PR128
680P_0603_50V8J~D
2

4 12.1K_0402_1%~D
B 2 2 B
G 4
1

PC117

2 1 2 1BST_VCCPP
14 22 UG_1.8VP

1
BOOT1 UGATE2
S
S
S

PL9 +1.8VP
2

3
2
1
PR129
LGATE1

LGATE2
PC118 LX_1.8VP 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.8VP
1
2
3

1
0_0603_5%~D

220U_D2_4VM
0.1U_0402_16V7K~D
PR130 1.8U_D104C-919AS-1R8N_9.5A_30%

5
6
7
8
4.7_1206_5%~D 1
PQ32

D
D
D
D
15

16

17

18

19

20

21
FDS6670AS_NL_SO8 +

PC119
680P_0603_50V8J~D
PC120

2
DCR 7.6m ohm(max) PR131

1
2
DCR 7.6m ohm(max)

PC123
+5VALWP +5VALWP BST_1.8VP 1 2 1 2 4 G
2

+VCCPP 2.2_0603_5%~D

2
0.1U_0402_16V7K~D

S
S
S
PC121 PC122
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1.8VP
1

3
2
1
Imax=6A
LG_VCCPP LG_1.8VP Imax=6A
Iocp=9A
Iocp=9A
Fsw=366kHz
Fsw=303kHz

A A

Security Classification Compal Secret Data

Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
VCCPP/1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 41 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

D D

+1.8V

1
PJP21

1
@ JUMP_43X118

2 2
PU10

4.7U_0805_6.3V6K~D
1 VIN VCNTL 6 +3VALW

1
PC128

4.7U_0805_6.3V6K~D
2 GND NC 5

1
1K_0402_1%~D

PC129
1
3 7

2
VREF NC

2
PR134 4 8
VOUT NC
C C
9

2
TP
APL5331KAC-TRL_SO8~N
PR136

1K_0402_1%~D
+0.9VSP

1
0_0402_5%~D D

10U_0805_6.3V6M~D
1 2 2

1
27,36 SUSP

PC133
G PR137 PC131
S

2
1
PQ33

2
PC132
@

2
0.1U_0402_16V7K~D
RHU002N06_SOT323-3 0.1U_0402_16V7K~D

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
+0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 42 of 45
5 4 3 2 1
 5 4 3 2 1

+5VS

2
5

5
PC134

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR138 +CPU_B+
PL10

29
VR_ON
2 1 1_0603_5%~D
FBMA-L18-453215-900LMA90T_1812
@ 1 2 B+

1
5600P_0402_25V7K
1 1

100U_25V_M

100U_25V_M
10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
1U_0603_10V6K~D
D D

1
+ +

PC140

PC135

PC141

PC136

PC142
PR139 499_0402_1%~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D
1

1
PC138

PC139
1U_0603_10V6K~D
7,20 DPRSLPVR 1 2

1
PC137

PC143

2
PR140 0_0402_5%~D 2 2

2
5,7,19 H_DPRSTP# 1 2

5
PR1480_0402_5%~D

PR1490_0402_5%~D

PR1420_0402_5%~D

PR1500_0402_5%~D

PR1460_0402_5%~D

PR1430_0402_5%~D

PR1440_0402_5%~D
PR141 0_0402_5%~D

1
0_0402_5%~D
CLK_EN# 1 2

PR145
+3VS PR147 0_0402_5%~D PQ34

DPRSLPVR_CPU
SI7686DP-T1-E3_SO8

DPRSTP#_CPU
1 2 4

CLK_EN#_CPU

VR_ON_CPU
2

2
+3VS

1U_0603_10V6K~D

3V3_CPU
1.91K_0402_1%~D
PL11 0.36UH_ETQP4LR36WFC_24A_20%

VID6

VID5

VID4

VID3

VID2

VID1

VID0
PC144
PR152 PC145

3
2
1
1
BOOT_CPU1 1 2 1 2 4 1 +CPU_CORE
2

PR151

4.7_1206_5%~D
PR153

5
6
7
8

5
6
7
8

1
2.2_0603_5%~D 0.22U_0603_10V7K~D 3 2

1
10K_0402_1%~D
PR154

3.65K_1206_1%
499_0402_1%~D PQ36

49

48

47

46

45

44

43

42

41

40

39

38

37

1
PR156
SI4634DY-T1-E3_SO8
2

PR155
PQ35 PR157

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

680P_0603_50V8J~D
SI4634DY-T1-E3_SO8 1_0402_5%~D

1 2
7,20,29 VGATE 1 36 4 4

2
PGOOD BOOT1

PC147
5 H_PSI# PR158 @ 0_0402_5%~D

2
2 35 UGATE_CPU1 VSUM 1 2
1U_0603_10V6K~D PC146 PR159 10K_0402_1%~D PSI# UGATE1 PC148

2
POW_MON 1 2 1 2 PMON 3 34 PHASE_CPU1 1 2

3
2
1

3
2
1
PMON PHASE1 ISEN1 VCC_PRM
C PR160 147K_0402_1%~D 4 33 C
RBIAS RBIAS PGND1 0.22U_0603_16V7K~D
1 2
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
PR161 @ 4.22K_0402_1% PH1

1
1 2 1 2 NTC 6 31 PVCC_CPU
NTC PVCC

PC149

PC150

PC152
@ 100K_0603_1%_TH11-4H104FT SOFT 7 30 LGATE_CPU2

2
SOFT LGATE2 PQ37
1 2
@ 0.015U_0402_16V7K PC151 OCSET 8 29 SI7686DP-T1-E3_SO8
0.068U_0603_50V7K~N PC153 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 VW 9 28 PHASE_CPU2
VW PHASE2
PR162 11.5K_0402_1%~D COMP 10 27 UGATE_CPU2 PL12 0.36UH_ETQP4LR36WFC_24A_20%
COMP UGATE2 PR163 PC155
1 2

3
2
1
FB_CPU 11 26 BOOT_CPU2
1 2 1 2 4 1
PC154 FB BOOT2
1 2

5
6
7
8

5
6
7
8

1
DROOP

1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D 3 2
FB2 NC
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR165 6.81K_0402_1%~D PQ38 PR164

GND

VDD
RTN

DFB

1
VIN

10K_0402_1%~D
4.7_1206_5%~D

3.65K_1206_1%
PQ39
VO

1 2

1
PR166

PR167
SI4634DY-T1-E3_SO8 SI4634DY-T1-E3_SO8 PR168
1 2 PU11
13

14

15

16

17

18

19

20

21

1VDD_CPU 22

23

24

1 2
FB2_CPU 4 4 1_0402_5%~D
PC156 1000P_0402_50V7K~D

2
29.1
RTN
VSEN_CPU

DFB

Vin_CPU

ISEN1 PC157 PR169 @ 0_0402_5%~D

VDIFF

DROOP

2
ISEN2 680P_0603_50V8J~D 1 2

2
PR171 97.6K_0402_1%~D PC158 470P_0402_50V7K~D 1 2 +5VS

3
2
1

3
2
1
1

1 2 2 1 VSUM PC160
PR170 1_0603_5%~D 1 2
PR172 PC159
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2
2

PC161 220P_0402_50V7K~D VCC_PRM

ISEN2
PR174
PR173 PC162 1000P_0402_50V7K~D
1 2 1 2 1 2 +CPU_B+
1

255_0402_1%~D
1 2 PC163 10_0603_5%~D
Fsw=300kHz
2

PR175 1K_0402_1%~D
PC164 0.022U_0603_25V7K 0.1U_0603_25V7K~D
5 VCCSENSE 1 2 1 2
VSUM
1

PR176 0_0402_5%~D
1

2.61K_0402_1%~D

PC165 PC166
@0.022U_0603_25V7K
PR177

0.022U_0603_25V7K
2

1 2
5 VSSSENSE PR178 0_0402_5%~D
2
1

11K_0402_1%~D

PC167 180P_0402_50V8J~D
PR179

1 2
2

1 2 1 2 PH2
2

PR180 1K_0402_1%~D PR181 3.57K_0402_1%~D 10KB_0603_5%_ERTJ1VR103J

PC168 0.068U_0603_50V7K~N
1

VCC_PRM 1 2
PC170 0.22U_0603_10V7K~D
A A
PC169 2 1 2 1
0.22U_0603_16V7K~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KFW11
Date: Monday, December 15, 2008 Sheet 43 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
 5 4 3 2 1

+3VALWP

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

2
PD12

PD13

PD14

PD15
D D
@
BATT+
BATT++

1
@
@ @ Battery Connect/OTP
BATT+

PL13
SMB3025500YA_2P
1 2 BATT++
+3VALWP

100P_0402_50V8J~D
1

1
100P_0402_50V8J~D
1

PC174
PC173
PC171

PC172 1000P_0402_50V7K~D @
2

2
0.01U_0402_25V7K~D
2

PR182 Place clsoe to EC pin

47K_0402_5%~D
1 2 BATT_TEMP
BATT_TEMP 29

1
PJPB1 battery connector PR198 PR183

2
BATT_SMD

BATT_SMC
1K_0402_5%~D

BATT_B/I
1K_0402_5%~D PC175
2 1 0.1U_0402_16V7K~D

1
SMART PJP22

@
1 PR184
Battery: 1
2 2
3 1K_0402_5%~D
3
4 2 1
1.BAT+
4
5 5 1 2 +3VALWP
@
2.BAT+ 6 6
7 PR185
7
C
3.ID 10 GND 8 8 6.49K_0402_1%~D
C
11 9
4.B/I GND 9

5.SMC SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 29

6.SMD PR186
100_0402_5%~D
7.TS
8.GND CPU
9.GND 1 2 EC_SMB_CK1 29 PH1 under CPU botten side :
PR187
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS
BATT+
1

2
PR188

1
340K_0402_1%~D PC176
0.1U_0603_25V7K~D
CPU

1
VS
2

PR189
10.7K_0402_1%~D VL

2
1
0.01U_0402_25V7K~D

PR191
B PR190 147K_0402_1%~D B

2
499K_0402_1%~D 1 2
1

PC177

PR192
205K_0402_1%~D
2
2

PR193

1
8
61.9K_0402_1%~D
1 2 OTP_IN+ 3 PD16

P
+
8

PR194 LM358ADR_SO8 1 OTP_OUT 1 2

10K_0402_1%~D 5 BATT_IN 1 2 OTP_IN- 2
0 MAINPWON 39
P

+ VL -

G
1 2 BATT_OUT7 1SS355_SOD323-2
0 PR195 PU12A
6

4
-
G

1
29 BATT_OVP 150K_0402_1%~D LM358ADR_SO8
1

PU12B PH3
4

1
100K_0603_1%_TH11-4H104FT

1
PR196
105K_0402_1%~D PC178 PR197

2
1000P_0402_50V7K~D 150K_0402_1%~D
2

2
2
PC179
1U_0603_10V6K~D

OVP voltage :
LI-3S :13.50V--BATT-OVP=1.5V
BATT-OVP=0.111*BATT+
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1

D 2 D

10

11

12
C C
13

14

15

16

17

18

19

20

21

22

B 23 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PW PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KFW11 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 15, 2008 Sheet 45 of 45
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE