LH51256 T-¥6-2.3-/ CMOS 256K (32K x 8) Static RAM FEATURES 32,768 x 8 bit organization Access times: 100/120 ns (MAX.) Power consumption: Operating: 248 mW (MAX.) (Ta = -40 to 85°C, minimum cycle) Standby: 16.5 wW (MAX.) (Ta = 0 to 60°C) Fully static operation TTL compatible /O Three state outputs Single +5 V power supply Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP DESCRIPTION ‘The LH51256 is a 256K bit static RAM organized as 92,7688 bits. Itis fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 28ND 28-PIN SOP TOP VIEW sis Figure 1. Pin Connections for DIP and SOP Packages5555555 5 al Tob 23-14 MEMORY ARRAY. 612x512) coLUMN ti) circus ‘COLUMN ADORESS DECODER ‘COLUMN ADDRESS BUFFERS BXIO RAM Aan Figure 2. LH51256 Block Diagram PIN DESCRIPTION Yeo ‘eno SIGNAL, PIN NAME ‘SIGNAL, PIN NAME ‘Aa-Ars | Address input VO1-VOs | Data VO os Chip Enable input Veo Power supply We Write Enabie input GND Ground OE Output Enable input TRUTH TABLE _ [WEE MODE 1,10, “ee Dore H x Nonselected | HighZ ‘Standby (Isa) 1 L t Wite Datain | Operating (loc) [1 L 4 Reed Data out [Operating (loc) L H | Output disable High-2 | Operating (loc) NOTE: 1, XaHorkABSOLUTE MAXIMUM RATINGS PARAMETER ‘SYMBOL RATING unt [NOTE ‘Supply voltage Veo -0.31047.0 Vv 1 Input voltage. Vi “0.310470 Vv 1 ‘Operating tomperature Topr ~40t0 +85 °C ‘Storage temperature Tstg__ | 8510 +150 °C NOTE: 4. Tho maximum applcablo voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (Ta = -40 to + 85°C) PARAMETER Syweo._ [| _ MIN [TR WAX, UNIT Supply voltage Veo. 45 50 55 7 Vor 22 v Input volt mpuvensae Vi. 03 Vv Tb -23-14 DC CHARACTERISTICS (Vcc = 5 V + 10%, Ta = -40 to +85°C unless otherwise noted) pataeven___| “SYMBOL ‘owomions une] war Voo= 58, Input leakage current Hut Vinvz 010 Vcc 1 A CE or OE = Vin, Output leakage current. | | hol Vio = 010 Veo 1 HA CE = Vi, Operating current feo ama 45 mA 1551 CE Vn 10 mA CE2 Voo- 02V, Standby current f Tan 00 460°C" 2 Ce Isa CE2 Veo -0.2V, Tan 4010 65°C %0 HA a Vou fous 2.1 mA 04 v Vou Ton = 1.0 mA, 2a v AC CHARACTERISTICS (1) READ CYCLE (Vcc =5 V + 10%, Ta = -40 to +85°C) PARAMETER svuao. |_MiS2seN10__ | LHS1256N2 | yup | NoTE WN, [_MAX_|_MIN_| WAX. Feead oyele time 100 120 7 ‘Address access time —_t ee a) | 120 |e GE accoss time 100 120 | ns Ouiput enable time 50 eo | ne Output hold time 3 3 1 ‘GE Low to output in Low-Z 5 3 a8 i ‘GE Low to output in Low-z [tox s | 5 19 1 GE High to ovtput in High-Z tz ° 30 o | 9 | as 1 ‘GE High to output in High-Z Tov ° 30 0 | 80 [as 1 NOTE: 1, Active output to high-impedance and high-impedance to output active tests specified for a 4600 mV transition trom stoady stata lovols nto the tost load, Coan = & pF.2) WRITE CYCLE (Vcc = 5 V + 10%, Ta = -40 to +85°C) TT 46-23-/]4 PARAMETER SYMBOL LHS1256/N-40 LAS T2SNE2 unit | Note WIN, | MAX | WIN, | WAX. ‘Write cycle time two 100 120 | ns ‘GE Low to and of writa tow 90 100 ns ‘Address valid to end of write aw 90 100 ns ‘Address setup time as 5 5 18 Write recovery time twa 15 15 ne Write pulse width ‘we 50 50 ns Input data setup time tow 30 30 8 Input data hold time to 10 10 ns WE High to output active tow, ° Q ns 1 WE Low to output in High-Z twz 0 30 ° 30 ns 1 ‘OE High to output in High-Z tonz 0 30 0 3o_ | ns 1 NOTE: 1, Active output to high-impodance and highimpedanco to output active tests specified for a 4500 mV transition from steady state levels into the test load. CLoan » 5 pF. AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude osvio24v | Input risefall timo 101s | Timing reference level 15V TTTL + Cx = 100 pF Output load conditions (Includes scope and jig capacitance) CAPACITANCE ' (Ta = 25°C, f= MHz) PARAMETER ‘SYMBOL | coNoMmONS | MIN” | TYR | MAX | UNIT Input capacitance Cw Vin=OV | 7 pF Inpuvvoutput capacitance Gio Wo=0V 10 oF, NOTE: 11, This parameter is sampled and not production tosted, DATA RETENTION CHARACTERISTICS (Ta = -40 to +85°C except as noted) PARAMETER SYMBOL | CONDITIONS min. | Tve_| MAX. | UN | NOTE Data retention voltage | Vecon | CE Vocon-0.2V 2.0 v Veco = 3V TE2 Vecon-0.2V, fl rn Ta = 010 480°C, i Data retention current | Jocon [v= 2'0 Vecor = aED Veen 02. 2 Vecor -0.2V, Ta = 40 to-485°C, c HA Viv = Oto Vecon __| ‘CE setup time ‘tcoR 0 ns GE hold time 18 tee ns 1 NOTE: 4. tae » Read cycle timoT-4b-23-/ GE2 Vecon 02V Figure 3. Low Voltage Data Retention tao Bo Ang tan & VA « Li ie Hor Sel Pour XX _owavau XO} NoTE: WE = HGH med Figure 4. Read Cycle1 tO-K HY to fo-A OE ae tow =e (ROTED a — (wore 4 (NOTE Dy ACES Notes: _ __ 1. The write pulse occurs during the overtap (yp) of CE = LOW and WE = LOW. 2. tow is dotined as the time from the CE low transton 1 the and a wrt, 8.43 dofined as the time from address chango to the stat of wring 4-tyn #8 defined a tho time from tho end of weing tothe address change. '5, Whon the UO pins ara Inthe output stata, Input signal with the opposite loge level must not be applied, Figure 5, Write Cycle 1 (OE Clock) —— WWOTES Wore) (NOTES) “co Pour EAA) tttt ow Ton (NOTE 5) WY NoTES: 1, The write pulse occurs during the overtap (typ) of CE = LOW and WE = LOW. 2 toy i delined as the tin. fom tha CE low transton to tha end of wie, 3. gg 5 datinad as the time from address change tothe stat of witng, 4. typ 8 delined as tho timo from the end of wring o tha adress change. 5, When tho VO pins ar inthe output stale input signals withthe opposite logic evel must nol be applied. 6.11 CE LOW transton occurs at the same time or alter WE LOW transition, the output wil remain high-impedance. 7.1 CE HIGH transicn occurs at the same time of prior lo tha WE HIGH transition, the output wil remain high-impedance. ssases| Figure 6. Write Cycle 2 (OE Low)ORDERING INFORMATION — P VY LH51256 xX - Ht To46~ 3 ~ Device Type Package Speed 101 u 43 199 Access Time (ns) 3 Blank 26-pin, 600-mil DIP (O1P28-P-600) N_ 2-pin, 450-mil SOP (SOP28-P-450) CMOS 256K (32K x 8) Static RAM Example: LH51256N-10 (CMOS 256K (92K x 8) Static RAM, 100 ns, 28-pin, 450-mil SOP) svze0]