Clean Rooms, Wafer Cleaning

and Gettering

Reading Assignments:
Plummer, Chap 4.1~4.4, 4.6

1
Yield & Profit
Wafergood
YW = ×100%
Wafertotal
Diesgood
YD = ×100%
Diestotal
Chipsgood
YC = ×100%
Chipstotal
YTotal = YW × YD × YC
Yield high, Profit high!
2
Yield & Profit

From Hong Xiao

3
 2007 ITRS

Contaminants may consist of particles, organic films (photoresist), heavy

metals or alkali ions.
Modern IC factories employ a three tiered approach to controlling unwanted
contaminants: 1. clean factories 2. wafer cleaning 3. gettering
4
 Particles vs. Yield

Open / short lines Degrade E Field

5
 Metal Ions vs. Yield
2ε S qN A (2φ f ) qQ M
Example #1: MOS VTH is given by V TH = V FB + 2φ f + + (1)
CO CO

If tox = 10 nm, then a 0.1 volt Vth shift can be caused by

QM = 6.5 x 1011 cm-2 (< 0.1% monolayer or 10 ppm in the oxide).

Example #2: MOS DRAM, minimize the junction leakage

WORD • Refresh time of several msec

LINE Reverse-biased requires a generation lifetime of
junction
BIT LINE
1
τ = ≈ 100 μsec (2)
ACCESS
-- --- - ---- -- STORED σv th N t
CHARGE
MOS ON MOS
TRANSISTOR CAPACITOR
• This requires Nt ≈ 1012 cm-3 or
≈ 0.02 ppb (see text).

6
 IC Manufacturing Process
原料 無塵室(clean room)
金屬化製 化學機械 化學氣相 測試
程 研磨 沉積
晶片
高溫製程 離子佈植 蝕刻 封裝

光罩 微影技術 最後測試

設計

Factory environment is cleaned by:

• Hepa filters and recirculation for the air.
• “Bunny suits” for workers.
• Filtration of chemicals and gases.
• Manufacturing protocols. 7
 History of Cleanroom
Development of cleanrooms started from hospitals.

1900
8
 Cleanroom Today

PHOTO: IBM
9
Cleanroom Pictures

10
 Working in Cleanroom
The most important contamination source in the fab is people.

per min

11
 Particle Spec.
American Fed. 209E

0.5μm

Normal
office
building

Airborne particles

12
Particle Size
Airborne particles

13
Example of Cleanroom

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 Cleanroom - Laminar Flow

Turbulent flow (>class 100) Laminar Flow (<class 100)

(low cost) (high cost) 15
 Cleanroom Design
Ballroom-type: process and service (dirty) areas located on the same floor.

Remain
positive
pressure

dirty area
HEPA Filter : high-efficiency particulate air filter
16
 Cleanroom Design
Centrifugal fan

Air plenum

Higher
pressure

Air shaft

17
 Cleanroom Design
Air plenum

Axial fan

18
Cleanroom Design
Filter fan

19
 Cleanroom Design
¾ Mini-environment (class 0.1 at 0.1μm)
¾ SMIF : Standard Mechanical InterFaces

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300mm Wafer Pod

21
 Wafer Cleaning
Need to remove the contaminations on wafer surface
Contamination Possible source Effects
Particles Equipment, ambient, gas, Low oxide breakdown field, Poly-Si and
Deionized (DI) water, chemical metal bridging-induced low yield (both
open and short)

Metal Equipment, chemical, reactive ion Low breakdown field, Junction leakage, Vt
etching (RIE), implantation, ashing shift, Reduced minority lifetime

Organic Vapor in room, residue of resist, Change in oxidation rate

storage containers, chemical

Microroughness Initial wafer material, chemical Low oxide breakdown field

Low mobility of carrier

Native Oxide Ambient moisture, DI water rinse Degraded gate oxide, low quality of epi-film,
high contact resistance, poor silicide
formation

22
 2007 ITRS

Contaminants may consist of particles, organic films (photoresist), heavy

metals or alkali ions.
Modern IC factories employ a three tiered approach to controlling unwanted
contaminants: 1. clean factories 2. wafer cleaning 3. gettering
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13 Cleaning Steps in CMOS Processes
(Front-End)

• Wafer start • P-apt

• Start oxide • Gate oxide
• Zero layer • Poly-Si
• N-well I/I define • N-LDD, p-LDD
• P-well I/I • Spacer
• Well-drive in • S/D thin oxide
• Etch oxide • N+-S/D
• STI • P+-S/D
• Sac oxide • BPSG
• VT, N-apt • Contact etch

24
 Primary Wafer Cleaning Steps
Cleaning Steps Major impact factor

Pre-oxidation cleaning Oxide breakdown filed

Pre-lithography cleaning PR adhesion

Pre-metal (contact/via plug) cleaning Contact resistance

Post-etch Cleaning PR veil and residue

Post-Implant Cleaning PR residue

Post-CMP Cleaning Surface residue

25
 Post Etch Cleaning
After metal etching, PR
stripping, and metal After poly-Si etch After contact hole SiO2 etch
remove

Polymer and Pillar Formation

26
 Gate Oxide Integrity (GOI)
Oxide quality is strongly related to the wafer cleaning, which determines
the yield, reliability, and performance of IC circuits

Si wafer
Chemical technology
Wafer
DI water Impurity,
metals
Cleaning
Chemical
technology Gate Oxide
equipment
Integrity

Roughness
Drying Particles Temp
process
Gases
Cleaning Oxidation technology
recipe

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Silicon Dioxide Grown on Improperly
Cleaned Silicon Surface

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 Cleaning Technology
¾ Wet Cleaning
• Immersion technique: bulky chemical solution
• Megasonic cleaning
– particles and contamination can be removed with dilute solution
• Centrifugal spray cleaning
– Cheaper & faster

¾ Dry cleaning
• Ultraviolet-ozone clean (UVOC)
– Effective in removing hydrocarbon
• HF/H2O vapor clean
• O2 plasma cleaning
• Ar/H2 plasma cleaning
• Thermal cleaning

29
 Procedure of Wet Wafer Cleaning
• Wet cleaning = cleaning + rinsing + drying

30
 Standard RCA Clean
¾ H2SO4 : H2O2 = 3 : 1 to 5:1 (Sulfuric-peroxide mixture, SPM)
• 120-130°C for 10-20 min.
• Dissolve heavy organic molecules
• Remove heavy metals
¾ HF : H2O = 1: 50 ( 1 min )
¾ NH4OH : H2O2 : H2O = 1 (0.05) : 1 : 5 (RCA-1, SC-1, APM)
• 70-80°C for 10-20 min.
• oxidize organic molecules
• Complex BI and BII metals (Cu, Au, Ag, Ni, Zn, Co, Cr etc)
• Remove particles (with megasonic)
¾ HCl : H2O2 : H2O = 1 : 1 : 6 (RCA-2, SC-2, HPM)
• 70-80°C for 10-20 min.
• Remove alkali ions and Al3+, Fe3+, Mg2+ ions, etc. by forming water solvable chloride
complex
¾ (HF-last)
Original RCA clean

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 Dependence of Ebd Yield on
Particle Density
Particle concentration(number/mL)
in ULSI-grade semiconductor chemicals

≥0.2um ≥0.5um

NH4OH 130-140 15-30

H2O2 20-100 5-20

HF 0-1 0

HCl 2-7 1-2

H2SO4 180-1150 10-80

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 Particle Adhesion & Removal
¾ Adhesion
• Static charge
• Van der Walls forces
• Electrical double layer
• Capillary action around the particle
• Chemical bond
¾ Removing Mechanism
• Dissolution
• Oxidizing degradation and dissolution
• Lift-off effect by slight etching of the wafer surface
• Electric repulsion

33
 Deposition of Particles onto Wafer
Surface as a Function of PH

As a function of PH value H2O2 consumes gradually with time

34
 Metallic Contamination
¾ Impacts on yield
• Structural defects at the interface
• Stacking faults during later oxidation or epitaxial process
• Increased leakage current of p-n junctions
• Reduced minority carrier lifetime
¾ Adhesion mechanisms
• Direct binding : Au, Ag, Pt has higher electronegativity tending to
neutralize by capturing electron from Si
• Incorporated in oxide during oxide formation : Al2O3, Cr2O3, CrO2,
Fe3O4….
¾ Removal
• Converting metal into ions which are soluble in the solution
• Oxide removal

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 Metallic Contamination
Element Eletronegativity Half-cell
Reduction
potential

Au 2.4 1.68

Pt 2.2 1.19

Ag 1.9 0.80

Hg 1.9 0.79

Cu 1.9 0.34 Tendency

Si 1.8 0.10 To be
participated on
bare Si
Pb 1.8 -0.13

Sn 1.8 -0.14

Ni 1.8 -0.23

Fe 1.8 -0.41

Zn 1.6 -0.76

Al 1.5 -1.66

Mg 1.2 -2.34

Ca 1.0 -2.87

Na 0.9 -2.71

K 0.9 -2.92
36
 Metallic Contamination

Example of
SPM clean

37
Metallic Contamination

Ca

15nm SiO2
38
Oxide Defect Density Versus Iron
Contamination

39
 Organic Contamination
¾ Impacts on yield
• Cause incomplete cleaning
¾ Adhesion mechanisms/sources
• Organic vapor in the ambient
• Container
• Photoresist
¾ Removal
• Dry ashing (O2 plasma)
• SPM
• Ozone-injected water
– Lower temperature, simplicity, reduced chemical usuage

40
 Surface Roughness
¾ Mainly caused in SC1 (SPM and SC2 won’t)
• NH4OH acts as etchant of oxide
• H2O2 acts as oxidants
¾ Surface roughness reduction
• Reduce proportion of NH4OH(the etchant)
• Reduce the temperature of the bath
• Reduce the cleaning time
¾ Be careful, the concentration of NH4OH can not be too low
(0.05-0.25; efficiency issue)

41
Today’s Gate Dielectric

SiO2 density = 2.2 g/cm3

1 layer of SiO2 ~ 0.36 nm

42
Surface Roughness

43
Effect of Roughness on
Electrical Properties

44
 Native Oxide
¾ Issues caused by native oxide
• Uncontrolled ultrathin oxide growth
• High contact resistance
• Inhibition of selective CVD or epitaxy
• Metal impurities are included in native oxide

HF-last SPM
45
 MOS Capacitor IV
with and without Preoxide

Preoxide: 300oC in O2；to prevent Si etch at high-temp

46
 Contact Angle

Surface of Si Surface of SiO2

Hydrophilic surfaces are more easily wet by cleaning solutions and during
drying any particles on the surface tend to stay in solutions until solution
is removed from the surface
Hydrophobic surfaces are more difficult to clean, cleaning solutions do not
wet as well and during drying solutions tend to bead up on the surface
Leaving the particles on the surface instead of keeping particles in the
solution . 47
 Wafer Cleaning Facility
Wet Bench
DI Water Tank

48
Conventional Wet Bench

49
 Rinser

Spray rinser: Overflow rinser:

Mechanical agitation improves Less aggressive chemical removal
chemical removal but may Lower tendency of particle deposition
increase particle deposition Preferable for hydrophobic surface 50
 Spin Dryer & IPA Dryer
¾ Spin dryer
• Centrifugal force : High rotation speed (>2000 rpm)
Stand along IPA Dryer • Particles entrained by air flow and risk of splash back
• Sensitive to drying marks
¾ IPA spin dryer
• Adding IPA to enhance water evaporation.
• IPA consumption
• Safety issue

Hydrophobic regions
Vertical Multi-Cassette
51
 IPA Dryer

¾ Isopropyl alcohol (IPA)

52
 Marangoni Dryer
¾ Marangoni effect
• Different surface tension stress
due to different IPA concentration.
¾ Drying mechanism
• IPA dissolves in water so that the surface tension stress is
reduced.
• H2O molecules migrates
from low stress region
toward high stress region.

53
Comparison of Wafer Drying Methods

54
 Limitations of Wet Cleaning Process
• Incompatibility for full-scale cluster tool
• Problems of high-aspect-ratio structures
• Particles are easier to control in gases than in liquid
• Cost, disposal safety

55
 Evolution of Cleaning

RCA IMEC Single Wafer

Dilute Solution
Cleaning

Cost-effective!
56
 Vapor Phase Cleaning
• Removal of organic contaminant
– UV/O3, plasma O2, plasma H2
• Removal of native oxide contaminant
– HF/H2O vapor (F terminated), reduction in
H2, Low-energy Ar
• Removal of metallic contaminant
– UV/Cl2, HCl/N2, remote plasma HCl/Ar/O2

absorbed impurity + hv ⎯⎯⎯⎯

200−300 nm UV
→excited impurity
O2 + hv ⎯⎯⎯⎯
184.9 nm UV
→2O
O + O2 ⎯⎯
→O3
O2 + hv ⎯⎯⎯⎯
253.7 nm UV
→O + O2
⇒ Excited impurity + (O, O3 ) ⎯⎯
→volatile compound

57
 Advanced Cluster System: vertical
furnace with HF-vapor cleaning
Oxidation Tube
LPCVD Poly-Si

HF-vapor
cleaning

Wafer in/out

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 Impurity Gettering
Noble
Period A Gases
I Alkali Ions
1 2
1 H He
A
1.008 II III
A
IV
A
V
A A
VI VII
A 4.003
3 4 56 7 8 9 10
2 Li Be
Deep Level Impurites in Silicon B C N O F Ne
6.941 9.012 10.81 12.01 14.01 16.00 19.00 20.18
11 12 VIII 13 14 15 16 17 18
3 Na Mg Al Si P S Cl Ar
B B B B B
22.99 24.31 III IV V VI VII I
B B
II 26.98 28.09 30.97 32.06 35.45 39.95
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
4 K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
39.10 40.08 44.96 47.88 50.94 51.99 54.94 55.85 58.93 58.69 63.55 65.39 69.72 72.59 74.92 78.96 79.90 83.80
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
5 Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
85.47 87.62 88.91 91.22 92.91 95.94 98 101.1 102.9 106.4 107.9 112.4 114.8 118.7 121.8 127.6 126.9 131.3
55 56 57 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
6 Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
132.9 137.3 138.9 178.5 180.8 183.9 186.2 190.2 192.2 195.1 197.0 200.6 204.4 207.2 209.0 209 210 222
87 88 89 104 105 106 107

Elemental Semiconductors
7 Fr Ra Ac Unq Unp Unh Uns

Shallow Acceptors

Shallow Donors
223 226 227.0 261 262 263 262

Getting: collecting unwanted elements (Alkai and heavy metal ions) in

inactive regions of the chip.
59
 PSG Layer
T (溛)
Devices in near 800
1200 1100 1000 900
surface region
10 - 20 痠μm Cu
Denuded Zone 10 -4
or Epi Layer Au
I
-6
10 Fe
Cr
Interstitial
10 -8 I Diffu
sivity Pt Diffusers

10 -10

Diffusivity (cm2 sec-1)

Intrinsic Ti
Gettering 10 -12 Au
Region μm
500+ ?m
S
-14
10
B, P
10 -16 As
Si

10 -18
Dopants

10 -20
Backside
Gettering 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Region 1000/T (Kelvin)

• Gettering mechanism: free the gettered element, diffusion, trapped.

• For the alkali ions, gettering generally uses dielectric layers on the topside
(PSG or barrier Si3N4 layers).
• For metal ions, gettering generally uses traps on the wafer backside or in the
wafer bulk.
• Backside = extrinsic gettering. Bulk = intrinsic gettering.
• Common extrinsic gettering methods include roughen backside, ion
implantation, polysilicon deposition, phosphorous diffusion etc.
60
 Intrinsic Gettering

Outdiffusion
1100
Precipitation

900

700
em

C
T

Nucleation
Þ
p
tu
a
er

re

500
Time
SiO2 precipitates (white dots) in bulk

• “Trap” sites can be created by SiO2 precipitates (intrinsic gettering), or by

backside damage (extrinsic gettering).

• In intrinsic gettering, CZ silicon is used and SiO2 precipitates are formed in

the wafer bulk through temperature cycling at the start of the process.
61