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PADDR[2]~reg0
PADDR[3]~reg0
PADDR[21]~reg0
PADDR[10]~reg0
PADDR[22]~reg0
PADDR[23]~reg0
PADDR[24]~reg0
PADDR[25]~reg0
PADDR[4]~reg0
PADDR[5]~reg0
PADDR[6]~reg0
PADDR[29]~reg0
PADDR[30]~reg0
PADDR[31]~reg0
PADDR[7]~reg0
IN_ADDR[0..31] PADDR[8]~reg0
PADOUT
PADDR[9]~reg0 [1-2]
PPROT[1]~reg0
PPROT[0]~reg0
PPROT[2]~reg0
PWDATA[0]~reg0
PWDATA[16]~reg0
PWDATA[10]~reg0
PWDATA[11]~reg0
PWDATA[12]~reg0
PWDATA[13]~reg0
PWDATA[14]~reg0
PWDATA[15]~reg0
PWDATA[1]~reg0
PWDATA[17]~reg0
PWDATA[18]~reg0
PWDATA[19]~reg0
PWDATA[20]~reg0
PWDATA[21]~reg0
PWDATA[22]~reg0
PWDATA[23]~reg0
PWDATA[2]~reg0
PWDATA[24]~reg0
PWDATA[25]~reg0
PWDATA[26]~reg0
PWDATA[27]~reg0
PWDATA[28]~reg0
PWDATA[3]~reg0
PWDATA[29]~reg0
PWDATA[30]~reg0
PWDATA[31]~reg0
PWDATA[4]~reg0
PWDATA[5]~reg0
PCLK~input
PCLK I O O
IO_IBUF [1-2]
PWDATA[6]~reg0 O
[1-2]
IN_DATA[6]~input CLK PWDATA[6]~output
6 PWDATA[0..31]
I O D Q I O
PRESETn~input
PRESETn I O
PWDATA[7]~reg0 IO_IBUF
PWDATA[8]~reg0
OUT_RDATA[3]~reg0
OUT_RDATA[4]~reg0
OUT_RDATA[21]~reg0
OUT_RDATA[22]~reg0
OUT_RDATA[23]~reg0
OUT_RDATA[24]~reg0
OUT_RDATA[25]~reg0
OUT_RDATA[26]~reg0
OUT_RDATA[27]~reg0
OUT_RDATA[28]~reg0
OUT_RDATA[29]~reg0
OUT_RDATA[30]~reg0
OUT_RDATA[31]~reg0
PADDR[15]~reg0
PADDR[14]~reg0
PADDR[17]~reg0
PADDR[16]~reg0
PADDR[18]~reg0
PADDR[19]~reg0
PADDR[20]~reg0
PADDR[0]~reg0
PADDR[11]~reg0
PADDR[12]~reg0
PADDR[13]~reg0
OUT_RDATA[14]~reg0
OUT_RDATA[15]~reg0
OUT_RDATA[16]~reg0
OUT_RDATA[17]~reg0
OUT_RDATA[18]~reg0
OUT_RDATA[19]~reg0
OUT_RDATA[20]~reg0
OUT_RDATA[0]~reg0
OUT_RDATA[1]~reg0
OUT_RDATA[10]~reg0
OUT_RDATA[11]~reg0
OUT_RDATA[12]~reg0
OUT_RDATA[13]~reg0
DATAB COMBOUT
PADDR[27]~reg0
DATAC
DATAB COMBOUT
DATAC PADDR[28]~reg0
LOGIC_CELL_COMB
CLK PADDR[28]~output
Decoder0~3
D Q I O
DATAA
ENA IO_OBUF
DATAB COMBOUT CLRN
DATAC
LOGIC_CELL_COMB
PSEL[5]~reg0
LOGIC_CELL_COMB
Decoder0~5 PSEL[7]~reg0
DATAA
CLK PSEL[7]~output
DATAB COMBOUT
D Q I O
DATAC
SCLR IO_OBUF
LOGIC_CELL_COMB CLRN
Decoder0~6
DATAA
OUT_RDATA[5]~reg0
DATAB COMBOUT
DATAC CLK OUT_RDATA[5]~output
LOGIC_CELL_COMB D Q I O
OUT_RDATA[6]~reg0
PSEL[3]~reg0
CLK PSEL[3]~output
D Q I O
SCLR IO_OBUF
CLRN
PSEL[4]~reg0
CLK PSEL[4]~output
D Q I O
SCLR IO_OBUF
CLRN
OUT_RDATA[7]~reg0
PSEL[0]~reg0
CLK PSEL[0]~output
D Q I O
SCLR IO_OBUF
CLRN
PSEL[1]~reg0
CLK PSEL[1]~output
D Q I O
SCLR IO_OBUF
CLRN
PSEL[2]~reg0
CLK PSEL[2]~output
D Q I O
SCLR IO_OBUF
CLRN
OUT_RDATA[8]~reg0
OUT_RDATA[9]~reg0
current_state.SETUP
OUT_SLVERR~0
OUT_SLVERR~reg0
O CLK DATAA
Q OUT_SLVERR~output
[1-2] D DATAB COMBOUT CLK
CLRN Q I O OUT_SLVERR
DATAC D
CLRN IO_OBUF
O DATAD
[1-2] LOGIC_CELL_COMB
current_state.ENABLE
PREADY~input Selector2~0 COMBOUT
CLK
PREADY I O DATAA Q Selector1~0 [1-2]
D
IO_IBUF DATAB CLRN current_state.IDLE DATAA
Selector0~0
PSLVERR~input DATAC COMBOUT DATAB
DATAA current_state.IDLE~0 CLK
PSLVERR I O DATAD Q OUT_RDATA[0]~0 DATAC COMBOUT
DATAB COMBOUT DATAA COMBOUT D
IO_IBUF DATAE CLRN DATAA DATAD
DATAC LOGIC_CELL_COMB
Transfer~input LOGIC_CELL_COMB DATAB DATAE
DATAD
Transfer I O DATAC COMBOUT LOGIC_CELL_COMB
LOGIC_CELL_COMB
IO_IBUF DATAD PWDATA[31]~0
DATAE DATAA
DATAF DATAB
PENABLE~reg0 LOGIC_CELL_COMB
PENABLE~output
CLK
Q I O PENABLE
D
CLRN IO_OBUF
IN_WRITE~input OUT_RDATA[0]~1
IN_WRITE I O DATAA COMBOUT
IO_IBUF DATAB
LOGIC_CELL_COMB PWRITE~reg0
CLK PWRITE~output
D Q I O PWRITE
ENA IO_OBUF
CLRN
PSTRB[3]~reg0
PSTRB[0]~reg0
PSTRB[1]~reg0