Michael Hennerich - Multichannel Phase Coherent System

Multichannel phase
coherent transceiver
system with
GNU Radio interface
Michael Hennerich
Systems Development Group
17 September
1 ©2019 Analog Devices, Inc. All rights reserved.
2019
RADAR
► RADAR application examples
 Short range Tracking
 Weather radar
 Maritime radar
 Level sensors
 Mapping
 Threat detection
 Missile guidance
 Phase array techniques are common

 Removal of mechanical elements for reliability and size
 Fast steering and multiple beams
 Improved SNR and phase noise
 Important System Factors:

 Low Phase Noise at small offsets
 High bandwidth – range resolution
 Synchronization between channels
 Dynamic Range/SNR
 Fast response
 Common Frequency range: 1-12GHz
 MIMO or Phased-MIMO RADAR
17 September
2 // ©2019 Analog Devices, Inc. All rights reserved.
2019
Signals Intelligence
► Signals Intelligence (SIGINT) – Intelligence gathering by intercepting signals
 Communications Intelligence (COMINT)
 Intercept communications to determine who is transmitting and content of transmission
 Interrogation, transceiver acts as a cell tower
 Electronic Signals Intelligence (ELINT)

 Non-communications based signal identification
 Direction Finding
 Time Difference of Arrival (TDOA)
 Array of directed antennas
 Important Signal Chain Factors

 Fast sweeping to identify targets
 High sensitivity
 Medium to High Output Power depending on system
 Sometimes RX Only
 Common Frequency range: 30MHz to 6GHz
17 September
3 // ©2019 Analog Devices, Inc. All rights reserved.
2019
Phased Array Overview
17 September
2019
Phased-Array RADARs
► RADAR systems utilizing array of antennas
► Analog or Digital phase shifters provide directionality

 Eliminate mechanical rotations
 Each channel possesses different phase
 Steers wavefront (WF) out of antenna at angle 𝜃
 Looks at particular WF into antenna
► Array can be 2-dimensional

 Allows for steering in both x- and y-directions
 Large number of elements per channel
► Can also utilize antenna polarization

 To transmit & decipher additional information
17 September
2019
Beamforming techniques
► Phase shifting achieved in analog domain ► Phase shifting achieved in digital domain
► Amplitude control achieved in analog domain ► With use of:
► Align channels on antenna side of ADC / DAC  NCOs (continuous-wave signals)
 Digital FIR filters (broadband signals)
► Uses discrete phase-shifters
► Equalize channels on FPGA side of ADC / DAC
► Multiple channels can be combined
 Lower number of amplifiers ► Each channel can be independently controlled
 Lower number of phase shifters  Within DSP constraints
 Requires more commands to shifters / attenuators  Provides maximum channel configurability
 Multibeam capability
17 September
2019
ADAR1000: 4 Channel Analog Beamformer
Key Features
► 8 GHz to 16 GHz frequency range
► Single-pin transmit and receive control
► 360° phase adjustment range
► 2.8° phase resolution
► ≥31 dB gain adjustment range
► Bias and control for external transmit and receive modules
► Memory for 121 prestored beam positions
► Four –20 dBm to +10 dBm power detectors
► 88-terminal, 7 mm × 7 mm LGA package
Key Benefits
► Compact form factor for electronically steered analog beamformer
► Negative bias voltage from integrated DAC intended for gate bias of
GaAs or GaN amplifier
► Support low power bias mode with 50% reduction in power
consumption
► Potential 5G applications
17 September
2019
Phased-Array Dynamic Range & Spurious Improvements
► After Rx phase and amplitude calibrations: 0

Single Rx Channel, Fund. Power [dBFS]=-0.91, SFDR=114
 Rx system is time and amplitude aligned -20

 System performance better than individual Rx -40
-60
-80
► When the number 𝑁 of ADC channels is doubled: -100
 The effective number of bits is incremented -120
-140
 The Rx noise spectral density (NSD) is lowered
-160
1900 1950 2000 2050 2100
Frequency (MHz)
► If channel spurious contributions uncorrelated: 128 Combined Channels, Fund. Power [dBFS]=-0.91, SFDR=134.9
 Spurious do not add 0
-20
 Aligned, desired signal do add
-40
 But noise floor lowers -60
-80
-100
► Results in 10log(𝑁) improvement in dynamic -120
range -140
-160
1900 1950 2000 2050 2100
► Improves combined Rx system sensitivity Frequency (MHz)
Combined Rx Channels In Phased-Arrays Improve System Dynamic Range!

17 September
2019
Phased-Array Tx Phase Noise Improvements
► After Tx amplitude and phase calibrations:

 Output Tx signals can be combined constructively Phase Noise Improvements When Combining Calibrated Tx Channels
-80
 System phase noise improvements achieved N=1
N=2
 System spurious performance can be improved -90
N=4
-100
► Improvements rely on uncorrelated channels -110

 Requires separate PLL sources to subarrays
 Desire noise to not add constructively -120
~3dB Phase Noise
Improvement With
-130
Each 2x Channel
► If noise sources are uncorrelated: -140
Increase!
 10log(𝑁) phase noise improvements/channel

achieved -150
102 103 104 105 106 107
 System data throughput can be increased Frequency [Hz]
Combined Tx Channels In Phased-Arrays Improve System Phase Noise!

17 September
2019
RF Transceivers Enable Forced Spurious Decorrelation
in Digital Beamforming Phased Arrays [5]
17 September
2019
Transceiver Integrated Circuits
What Are Integrated Transceivers (TRx)?
► Single-chip ICs which contain: Chip-Level Transmitter and Receiver Integration
 Full Rx signal chains
 ADCs & ADC interface to baseband
 Down-convert mixers Mixer
Rx Input ADC
 Variable digital or analog filters
VGA IF Amp
 Variable gain amplifiers or attenuators
 Full Tx signal chains

 DACs & DAC interface to baseband Rx PLL Clock
with VCO Generator
 Up-convert mixers DSP
 Variable digital and/or analog filters Microprocessor
 Variable gain amplifiers and/or attenuators
Mixer
 On-chip PLLs allow for complete system solution Tx Output DAC
IPA IF Amp
 On-chip microprocessors for system calibrations

 General-purpose input/output (GPIO) connections Tx PLL
with VCO
 To monitor Rx or Tx status
Transceiver IC
 To enable automatic gain control
 To quickly issue frequency hops or system response
17 September
2019
Transceivers for Low Power & Small Form Factor
How Does Integration Lead to Smaller-Footprint & Lower-Power SDR Systems?
Balun
RxMixer1
► TRx ICs enable low-SWaP SDR systems Rx1
ADC1
 Multiple Rx & Tx channels available on-chip LNA VGA1 IF Amp
 Can serve as backbone to phased-array systems Rx PLL

with VCO
► Built-in calibration algorithms Balun
 Facilitate system-level calibrations Rx2

ADC2
RxMixer2
 Digital pre-distortion (DPD) LNA VGA2 IF Amp
 Spurious rejection algorithms Clock

DSP
 Improve system dynamic range & spurious Microprocessor Calibrations Generator
Balun
TxMixer1
DAC1
► Application programming interface (API) Tx1
HPA IPA IF Amp
 Vetted software to control the radio
 Capable of being incorporated into end design Tx PLL
with VCO
► JESD204 interface Balun
DAC2
 Developed hardware description language (HDL) Tx2
TxMixer2
HPA IPA IF Amp
 Easily integrate with FPGA or ASIC BBP 12mm x 12mm
Multi-Channel Transceiver IC
17 September
2019
ADRV9009: Highly Agile Wideband Integrated RF Transceiver
► Integrated Dual Rx and Dual Tx

 LO Range: 75 MHz < Fc < 6GHz
 Max Rx BW = 200MHz
 Max Tx BW = 450MHz, Primary Signal BW = 200MHz
 Max Orx BW = 450MHz
► Integrated Clock Generation

 Frequency Agile
 Rx / Tx Local Oscillator
 16 bit ADC/DAC
 Accepted Clocks up to 1GHz
► Digital Features
 Rx: DC Offset, QEC, AGC
 Tx: LO leakage, QEC
 Programmable FIRs
 12.288 Gbit/s JESD204-B interface
 Embedded ARM
► GPIOs
 AUX DAC, AUX ADCs
 GPIO
 Rx MGC, AGC (Hybrid)
► Low power:
 3.5W RX only
 3.7W TX only
 5.6W TX+Orx
 Less in TDD
17 September
2019
Analog Devices RF SOM (System on Module)
Production Ready Module, MIL-202 qualified
ADRV9009-ZU11EG RF SOM : $7999 ► Power Modules

► Processor  12V input
 Quad Core ARM Cortex A53 (1.5 GHz each) ► 4 Gbyte DDR4 + ECC for Processors
 L1 cache : 32 KB Instruction, 32 KB Data ► 128 Mbyte SPI Flash
 L2 cache : 512 KB ► USB 2.0 (OTG Controller + Phy)
► Processor ► 4 x GTR share among:
 Dual ARM R5 (600 MHz each)  PCIe® Gen2 x4,
 L1 cache : 32 KB Instruction, 32 KB Data  2x USB3.0,
 128KB Memory per core  SATA 3.1,
► GPU : Mali-400 MP2 up to 667MHz  DisplayPort,
 L2 Cache 64KB ► 4x Tri-mode Gigabit Ethernet
► FPGA  1 x 10/100/1000 Ethernet Phy
 Kintex Ultrascale+ Fabric ► 2xUSB 2.0
 653k Logic Cells  1 USB 2.0 Phy
 52.7 Mb Block RAM ► 2x SD/SDIO
 2,928 DSP Slices  1x MicroSD Card (lockable)
 Vivado license required Xilinx ZU11EG ► 2x UART,
► 2x CAN 2.0B,
► 2 Banks of 2 Gbyte (x32) DDR4 for PL (Radio) ► 2x I2C,
► 128 Mbyte SPI Flash ► 2x SPI,
► MicroSD Card (lockable) ► 4x 32b GPIO
► 24 x GTH (12.5 Gb/s)
► ADRV9009 RF Transceiver  2x 100G Ethernet MAC/PCS w/RS-FEC
 245.76 MSPS Rx (200 MHz Bandwidth)  PCI Express® Gen 3 (x16)
 491.52 MSPS Tx (450 MHz Bandwidth)  External JESD204B ADRV9009 Devices
 491.52 MSPS Observer (450 MHz Bandwidth)
 128-tap FIR Filters for equalization ► Full Linux based reference design
 Multi-chip phase synchronization for RF LO and ► Fully integrated and tested system
baseband clocks ► Common connector
 75 – 6000 MHz tuning range ► Digital I/O pins :
 2 Rx, 2 Tx, 2 Tx Monitor (per device) ► U.FL connectors : 20
ADI ADRV9009
17 September
2019
Synchronization For Many Channel System
JESD 204B ADC/DAC
Multichip Synchronization (MCS)
IIO buffer sample JESD 204B ADC/DAC
Physical
Host Transport Transport
Layer
(MATLAB, (USB, PCIe, Layer Link Layer
DMA FPGA GTX
Simulink, Ethernet, ADRV9009 JESD204B
High Speed
etc) QSPF, etc) Specific JESD 204B ADC/DAC
Transceiver
Aapplication Layer Sync JESD204B Deterministic Latency RF Phase Sync
Clock Sync
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2019
JESD204B
Digital Interface
synchronization
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2019
High-Speed Converter / FPGA / ASIC Interfaces
How Do Converters Communicate With the Baseband Interfaces?
► Faster rates increase converter data volume
Historical LVDS With Quad-ADC Newer Serialized JESD204B/C
► Data sent to baseband processor (BBP) • Requires Equal Trace Lengths
• Changing Converter Resolution/Count
•
•
Fewer Traces Required
Scalable For Additional Channels
 Field programmable gate array (FPGA) Necessitates Complete Hardware Redesign • Scalable For Changing Converter Resolution
FPGA
Quad ADC IC
 Application-specific integrated circuit (ASIC) Quad ADC IC
200MSPS 200MSPS Lane1
► Historically done with parallel interfaces: 12-bit
ADC1
12-bit
ADC1
 Low-voltage differential signal (LVDS) >

200MSPS 200MSPS
12-bit
200MSPS
12-bit
Lane2
ADC2 ADC2
 Complementary metal-oxide semiconductor FPGA JESD
SYNC
JESD
(CMOS) 200MSPS 200MSPS
Serializer Deserializer
12-bit 12-bit
► Newer JESD204 serialized standard ADC3 ADC3 Lane3
simplifies: Lane4
200MSPS 200MSPS
 Board layout (fewer number of traces for 12-bit
ADC4
12-bit
ADC4
interface)
 Provides deterministic latency
 Scalable to increasing sample rates & channel
counts
17 September
2019
JESD204 Standard
► 2006: JESD204
 1 lane, 3.125Gbps
► Designed as high-speed serial data link ► 2008: JESD204A

between converter (ADC, DAC) and logic  Multi-lane, 3.125 Gbps
device ► 2012: JESD204B
 Up to 32 lanes per link  Multi-lane, 12.5 Gbps
 Up to 32 Gbps (raw) per lane  Deterministic latency
► Describes data mapping and framing  Subclass 0, 1, 2
 More flexible clocking scheme
► Multi-chip synchronization
► 2017: JESD204C
► Deterministic latency
 Multi-lane, 32 Gbps
 64b/66b and 64b/80b encoding
 Forward Error Correction
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2019
JESD204 Architecture
Overview Layers
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2019
Converter Device
► Does either A2D or D2A conversion

► Contains one or more converters
 All synchronous
► Modern converter devices often include
digital processing
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2019
Logic Device
► Implements digital signal processing

► Often implemented in a FPGA
► One logic device can interface multiple
synchronous converter devices
 Multi-point link
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2019
Link
► Link consist of multiple independent lanes

► Differential current-mode-logic (CML) signaling
► 8b/10b data encoding (JESD204B)
► Embedded clock
► Data scrambling
 Optional, but highly recommended
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2019
Link/Lane Parameters
Parameter* Description
DID Device identification
LID Lane identification
F Octets per frame
K Frames per multi-frame
L Number of lanes per converter device
N Converter resolution
N' Number of bits per sample (recommended to be multiple of 4)
SCR Scrambling enabled/disabled
HD High-density (Single sample split over multiple lanes)
JESDV JESD204 Version (JESD204A, JESD204B)
SUBCLASSV JESD204B Subclass (0, 1, 2)
* Table is a excerpt of the most important parameters
● Parameters are used to describe the link and lane configuration
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2019
Link Synchronization
Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames
F F F F A F F F F F A F F F F F A
D
D D D D D D D D D D D D D D D D D
K K K
Receiver
De-asserts
SYNC~
Code Group Synchronization Initial Lane Alignment Sequence User Data
R D D D D A R Q C C D D A R D D D D A R D D D D A
Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames
K=K28.5 code group synchronization comma character

► Receiver asserts SYNC A=K28.3 lane alignment symbol
F=K28.7 frame alignment symbol
► Transmitter repeatedly sends /K/ character R=K28.0 start of Multi-Frame
Q=K28.4 start of link configuration data
C= JESD204 link configuration parameters
► Receiver performs CGS and character alignment D=Dx.y data symbol
LMFC=Local Multi-Frame Clock
► Receiver de-asserts SYNC

► Transmitter starts sending ILAS and data
17 September
2019
Initial Lane Alignment Sequence
Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames
F F F F A F F F F F A F F F F F A
D
D D D D D D D D D D D D D D D D D
K K K
Receiver
De-asserts
SYNC~
Code Group Synchronization Initial Lane Alignment Sequence User Data
K=K28.5 code group synchronization comma character

A=K28.3 lane alignment symbol
F=K28.7 frame alignment symbol
R=K28.0 start of Multi-Frame
Q=K28.4 start of link configuration data
R D D D D A R Q C C D D A R D D D D A R D D D D A C= JESD204 link configuration parameters
D=Dx.y data symbol
Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames LMFC=Local Multi-Frame Clock
► After link synchronization the transmitter sends the (Initial Lane Alignment Sequence) ILAS
► Allows verification of link alignment
 Special control character at the start and end of ILAS multi-frame
► Second ILAS multi-frame contains link configuration parameters
 Allows to verify configuration and lane mapping
17 September
2019
Latency
► Propagating data over the link takes time

► JESD204 defines latency as the time difference between when the sample is
inserted in the TX framer and outputted on the RX defamer
 Part of the latency is fixed
 Digital pipeline delays
 Trace lengths
 Part of the latency depends on manufacturing and environmental conditions (PVT)
 PCB propagation delays
 Process, Voltage, Temperature (PVT)
► Some systems/algorithms are latency sensitive

 Closed-loop-control systems
 RADAR
17 September
2019
Deterministic Latency
► Latency can be defined as deterministic when the time from the input of the JESD204x
transmitter to the output of the JESD204x receiver is consistently the same number of clock
cycles
 In parallel implementations, deterministic latency is rather simple – clocks are carried with the data
 In serial implementations, multiple clock domains exist, which can cause nondeterminism
► End-to-End (JESD link) Latency is consistent (and deterministic) across PVT variations and from
power-on to power-on
► Non-deterministic latency components are not removed, but compensated
 Data is buffered before released to the application layer (elastic buffer)
 Release happens at deterministic release opportunities
► Supported by JESD204C and JESD204B subclass 1 and 2
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2019
Local Multi-Frame Clock
► Each JESD204B device generates an internal local multi-frame clock (LMFC)

 1-32 frames long
► Beginning of the LMFC is synchronized externally
 Subclass 0: N/A (no deterministic latency)
 Subclass 1: SYSREF
 Subclass 2: SYNC
► Internal events are synchronized to the LMFC
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2019
SYSREF
► SYSREF is used as a synchronization signal

 In Subclass 1
► Source synchronous to the device clock
► Three modes
 Periodic, gapped periodic, one-shot
► LMFC is aligned to SYSREF
17 September
2019
Deterministic Latency
► Deterministic link latency is achieved by using a elastic buffer with an appropriate data release point.
► Alignment of all local multi-frame clocks (LMFCs) at the TX and RX devices by SYSREF
► Release point for the data must be after the last arriving lane (L1)
17 September
2019
JESD204 Interface Framework
► System-level integrated HDL and software JESD204
Interface Framework
framework covering the whole stack
 Hardware: Reference and rapid prototyping systems
 HDL: Components for JESD204 protocol handling
 Software: Drivers to manage clock-chips, converters
and HDL
► Components have been co-designed for
improved interoperability
► Key features
 Automatic interface configuration based on
application settings
 High-level API
 Dynamic re-configuration
 Improved diagnostics
► ADI provides full stack reference designs
 Works out of the box
 Starting point for development of custom designs
17 September
2019
JESD204 Diagnostics
► Statistical Eyescan, Bit-error-rate monitoring
 Detect electrical signal integrity issues JESD204
Interface Framework
► Clock rate monitoring for all system clocks
 Detect bad clock wiring
 Detect clock failures
► Initial lane sequence monitoring and
verification
 Detect lane swaps
► Lane arrival monitoring (relative to SYSREF)
 Detect potential sources of non-deterministic
latency
► SYSREF alignment monitoring
 Detect SYSREF timing and configuration issues
► Continuous monitoring
 Application is notified as soon as failure occurs
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2019
Multichip
Synchronization
17 September
2019
Synchronization For Many Channel System
JESD 204B ADC/DAC
Multichip Synchronization (MCS)
IIO buffer sample JESD 204B ADC/DAC
Physical
Host Transport Transport
Layer
(MATLAB, (USB, PCIe, Layer Link Layer
DMA FPGA GTX
Simulink, Ethernet, ADRV9009 JESD204B
High Speed
etc) QSPF, etc) Specific JESD 204B ADC/DAC
Transceiver
Aapplication Layer Sync JESD204B Deterministic Latency RF Phase Sync
Clock Sync
17 September
2019
Multichip Synchronization
► Multichip Synchronization (MCS) synchronizes
baseband data paths of multiple devices
► Accomplished through SYSREF, REF_CLK
and JESD deterministic latency
► Controlled through API functions
► Provides synchronization for:
 Device clock dividers
 High speed digital clock divider
 BB PLLs (ADCs/DACs)
 NCOs
 JESD LMFC
 RF PLLs phases
 Gain control AGC
 State machines
17 September
2019
Integrated RF Transceiver latencies
Analog circuitry delay Digital processing pipeline delay JESD204
Interface latency
ADC cycle latency (Filters, QEC, NCO, etc.)
► Overall Latency
depends on
► BB Rate
► ADC clock
► Filter settings
RF PLL Synchronization ► Is deterministic
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2019
RF Phase
Synchronization
17 September
2019
RF PLL Synchronization
► RF phase synchronization is a new

transceiver feature
► Provides deterministic phase across:
 Power cycles
 LO frequency changes
 Initializations
 Temperature
► Works across multiple TRX.
► Phase is unique to each transceiver chip
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2019
Phase Synchronization of Single ADRV9009 Over
Power Cycles
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2019
Phase Synchronization Between ADRV9009s
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2019
ADRV9009 RF PLL phase synchronization
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2019
Phase Offsets and SOM
► SOM can be factory calibration with measure

offset provided in EEPROM
► Calibrated phases allow aligned multi-SOM
synchronization
► EEPROM can be updated by user if necessary
► Calibration procedure will be available to users
EEPROM
©2019 Analog Devices, Inc. All rights reserved.

42
System considerations
 Overall phase synchronization is determined by a number of
factors
 Board level clock routing (tCLK)
 On-chip reference path routing (tREFPATH)
 PLL and LO divider path (tPLL)
 RF & antenna paths (tRF)
 The LO phase synchronization method addresses the initial PLL

phase and LO divider state and reduces their temperature
dependence to a negligible amount compared to other sources of
phase drift in the system
 In a beamforming/MIMO system, there is a system level antenna

calibration which is performed to equalize the sum of these paths
between all channels. The goals of this transceiver mechanism
are:
 Reduce the complexity of the antenna calibration by initializing to a
more consistent startup condition with deterministic PLL phase and LO
divider state.
 Reduce the temperature dependence of the system phase
synchronization to allow the antenna calibration to run less frequently
during operation.
 Allow transceivers to be stopped and started in an operational system
and “hot synchronize” with the other transceiver elements.
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2019
Distributed
Multichip Clock
Synchronization
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2019
Distributed Multichip Clock Synchronization
► Requirements
 Deterministically align clocks and minimize channel
skews across all outputs and layers in a clocking tree
 Meet setup and hold times for SYSREF signals
relative to the device clock at each data converter
(TRX)
► Problems
 Large number of clocks required
 In multiple-device clock tree structures that are based
on simple clock buffers, controlling setup and hold
times is challenging
 Maintain deterministic phase accuracy across multiple
levels of clock expansion
 Maintain clock jitter, phase noise performance across
all tree layers and avoid extra clock spurs
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2019
Multichip Clock Distribution
SSRQ PASS-THRU
SYNC & SYSREF REQUEST
REF
IN
PLL DEL /O ∆T
CLOCK 0
VCO 0 0 0
DEL /O ∆T
DEL /O ∆T SYSREF 0
1 1 1
0 0 0
SYNC &
SSRQ SYSREF
REQUEST DEL /O ∆T
1 1 1
Max Clock DEL /O ∆T
CLOCK N/2
CS N-1 N-1 N-1
SCLK SERIAL
Frequency
SDI PORT DEL /O ∆T SYSREF N/2
SDO DEL /O ∆T N N N
N-1 N-1 N-1 To
Clock IC Clock IC 1
DEL /O ∆T N/2 CLOCK (N/2)2
N N N Clock IC 2
SYSREF (N/2)2
Stage 1 Clock IC N/2

Stage 2
* Expandable to multiple stages
Advantages
Large Clock Trees
Simplifies Clock/SYSREF Sync & Alignment
Single VCO generates all clocks (cost)
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2019
Multichip Reference Distribution
SSRQ PASS-THRU
SYNC & SYSREF REQUEST Stage 2
SSRQ SYNC & SYSREF REQUEST
PLL +
DEL /O ∆T VCO
0 0 0
DEL /O ∆T DEL /O ∆T
0 CLOCK 0
1 1 1 0 0
Reference
REF
IN Frequency DEL /O ∆T
SYSREF 0
1 1 1
DEL /O ∆T
N-1 N-1 N-1 To
Clock IC
DEL /O ∆T N/2 DEL /O ∆T
CLOCK N/2
N N N N-1 N-1 N-1
DEL /O ∆T
SYSREF N/2
N N N
Stage 1 CLOCK (N/2)2

* Expandable to multiple stages Clock IC 2
** Reference Clean Up options with external VCXO SYSREF (N/2)2
Clock IC N/2
Advantages
Large Clock Trees w/ Ultralow Jitter Clocks
Simplifies Clock/SYSREF Sync & Alignment
Minimizes Traces Length of x GHz Clocks
Multiple boards via backplane reference
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2019
Large Clock Trees: Clock vs Reference
Distribution Comparison
Clock Distribution Reference Distribution
Jitter Low Ultralow
Number of VCOs 1 (cost advantage) 1 per Clock Device
Correlated Close in Phase Noise Yes (1) No (1)
(due to single PLL/VCO)
Timing Requirement: Easy Easy to Moderate (2)
Multichip Output Synchronization
Timing Requirement: Easy to Moderate (2) Easy to Moderate (2)
SYSREF Generation
Inter-stage Frequency Max Clock Speed (GHz) Reference Frequency (MHz)
RF routing concerns, may increase PCB cost sooner
than Reference Distribution method
Risk of unwanted Signal Coupling Yes Lower Risk

onto Clock Signal (ADC SFDR) PLL/VCO loop filter at final stage will remove coupling
affects on reference distribution
(1) Application-dependent advantage
(2) Dependent on clock device family chosen. Newer clock device families have developed methods to ease these requirements
17 September
2019
HMC7044
► SOM uses HMC7044 for clock/reference
distribution for onboard ADRV9009s and between
multiple SOMs
► JESD204B/JESD204C-compatible system
reference (SYSREF) pulses
► 14 ultralow noise and configurable outputs
► Programmable phase delay:
 25 ps analog, and ½ VCO cycle digital delay on each
output
► Multiple HMC7044 can be synced

► Supports both Reference and Clock Distribution
techniques
 Multi-SOM can choose either or
17 September
2019
Multi-ADRV9009 Synchronization 4R4T
17 September
2019
Multi-ADRV9009 Synchronization with
Daughtercard 8R8T
SOM 1
SOM 2
17 September
2019
Multi-SOM Sync 16R16T
SOM 1
SOM 2
SOM 3
 Extending the clock tree
 This concept can scale up to nRnT SOM 4
17 September
2019
Multichannel
Phase Offset
Validation
17 September
2019
Measuring Phase
► Many ways to measure phase but two used ► Source signals
here  Must be high SNR
► Average instantaneous phase  Sinusoids
 Easy to visually understand when sample offset is
 𝑓 𝑥⃗, 𝑦⃗ = tan ∑ 𝑥̅ 𝑛 𝑦[𝑛] zero and phase limited to < 180
► Cross-Correlation  Noise
 Hard to visually interpret
 𝑓 𝑥⃗, 𝑦⃗ = tan max ℑ ℑ(𝑥⃗)ℑ(𝑦⃗)  Excite entire bandwidth
 ℑ is an FFT  Sample offset simple to interpret
 Sample delay argmax ℑ ℑ(𝑥⃗)ℑ(𝑦⃗)
 Peak is reasonable confidence measurement
17 September https://en.wikipedia.org/wiki/Cross-
2019 correlation#/media/File:Cross_correlation_animation.gif
Averaged Instantaneous Phase Hier Block
► Fast, easy to implement, works great with sinusoids
► Sensitive to sample offset
Phase angle
17 September
2019
Cross-Correlation Method Hier Block
► Slow relative to direct method
► Sample offset measured separately and captured
Correlation
Phase angle
Sample
Delay
17 September
2019
Measurement Setup
Device A
RX1
RX2
RX3
4-way Power Splitter
RX4
Device B
TX1
or
17 September
2019
Flow Graph: Averaged Instantaneous Phase
(sinewave_phase_est.grc)
https://github.com/analogdevicesinc/gr-iio/blob/grcon2019/demos/adrv9009zu11eg/sinewave_phase_est.grc
17 September
2019
Flow Graph: Averaged Instantaneous Phase
17 September
2019
Flow Graph: Cross-Correlation Method
(noise_phase_est.grc)
https://github.com/analogdevicesinc/gr-iio/blob/grcon2019/demos/adrv9009zu11eg/noise_phase_est.grc
17 September
2019
Flow Graph: Cross-Correlation Method
17 September
2019
Conclusions
► End-to-end deterministic latency and RF frequency and phase coherent
synchronization in scalable Multichannel Systems can be realized
 Using the latest generation of Integrated RF transceivers
 Multichip LO Phase Synchronization simply phased array beamforming
 RF Transceivers simplify Forced Spurious Decorrelation
 Combined Rx Channels improve System Dynamic Range
 Combined Tx Channels improve System Phase Noise
 Flexible clocking and synchronization topology
 Impedance controlled trace length matching
► Phase offsets can be measured, avoided or compensated

► GNU Radio is a very effective tool to build, model, analyze and visualize complex
multichannel SDR systems
17 September
2019
Ahhh, technology. We can't find that page.
Thanks
Q&A
17 September
2019
References
[1] https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg
[2] https://www.analog.com/en/technical-articles/understanding-layers-in-jesd204b-specification.html
[3] https://www.analog.com/en/analog-dialogue/articles/jesd204c-primer-part1.html
[4] https://www.analog.com/en/technical-articles/synchronizing-sample-clocks-of-a-data-converter-array.html
[5] https://www.analog.com/en/technical-articles/rf-transceivers-enable-forced-spurious-decorrelation-in-digital-beamforming-
phased-arrays.html
[6] https://www.analog.com/en/technical-articles/system-level-lo-phase-noise-model-for-phased-arrays-with-distributed-phase-
locked-loops.html
17 September
2019

Michael Hennerich - Multichannel Phase Coherent System

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Michael Hennerich - Multichannel Phase Coherent System

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Multichannel phase

 Phase array techniques are common

 Important System Factors:

 MIMO or Phased-MIMO RADAR

 Electronic Signals Intelligence (ELINT)

 Important Signal Chain Factors

► Analog or Digital phase shifters provide directionality

► Array can be 2-dimensional

► Can also utilize antenna polarization

► After Rx phase and amplitude calibrations: 0

 Rx system is time and amplitude aligned -20

Combined Rx Channels In Phased-Arrays Improve System Dynamic Range!

► After Tx amplitude and phase calibrations:

► Improvements rely on uncorrelated channels -110

 10log(𝑁) phase noise improvements/channel

Combined Tx Channels In Phased-Arrays Improve System Phase Noise!

 Full Tx signal chains

 On-chip PLLs allow for complete system solution Tx Output DAC

 On-chip microprocessors for system calibrations

 Multiple Rx & Tx channels available on-chip LNA VGA1 IF Amp

 Can serve as backbone to phased-array systems Rx PLL

► Built-in calibration algorithms Balun

 Facilitate system-level calibrations Rx2

 Spurious rejection algorithms Clock

► JESD204 interface Balun

► Integrated Dual Rx and Dual Tx

► Integrated Clock Generation

ADRV9009-ZU11EG RF SOM : $7999 ► Power Modules

JESD 204B ADC/DAC

Multichip Synchronization (MCS)

IIO buffer sample JESD 204B ADC/DAC

Aapplication Layer Sync JESD204B Deterministic Latency RF Phase Sync

 Low-voltage differential signal (LVDS) >

► Designed as high-speed serial data link ► 2008: JESD204A

► Does either A2D or D2A conversion

► Implements digital signal processing

► Link consist of multiple independent lanes

● Parameters are used to describe the link and lane configuration

Code Group Synchronization Initial Lane Alignment Sequence User Data

Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames Multi-Frame = K Frames

K=K28.5 code group synchronization comma character

► Receiver de-asserts SYNC

Code Group Synchronization Initial Lane Alignment Sequence User Data

K=K28.5 code group synchronization comma character

► Propagating data over the link takes time

► Some systems/algorithms are latency sensitive

► Each JESD204B device generates an internal local multi-frame clock (LMFC)

► SYSREF is used as a synchronization signal

JESD 204B ADC/DAC

Multichip Synchronization (MCS)

IIO buffer sample JESD 204B ADC/DAC

Aapplication Layer Sync JESD204B Deterministic Latency RF Phase Sync

► RF phase synchronization is a new

► SOM can be factory calibration with measure

©2019 Analog Devices, Inc. All rights reserved.

 The LO phase synchronization method addresses the initial PLL

 In a beamforming/MIMO system, there is a system level antenna

Stage 1 Clock IC N/2

Stage 1 CLOCK (N/2)2

Risk of unwanted Signal Coupling Yes Lower Risk

► Multiple HMC7044 can be synced

 Peak is reasonable confidence measurement

► Phase offsets can be measured, avoided or compensated