3 Study unit 3

3 Logic gates

Overview of this study unit

In this study unit we focus on the operation, application and troubleshooting of logic
gates. The relationship between the input and output waveforms of a gate using timing
diagrams is thoroughly covered.

Learning outcome for this study unit

After completing this study unit, you should be able to

•• identify the different types of logic gates available and discuss their functionality

Assessment criteria for this study unit

•• The various types of logic gates are identified and discussed.
•• The different types of logic gates are identified and their digital functions explained.
•• The truth tables of the various logic gates are identified and drawn correctly
Introduction

Logic devices, as the name suggests, carry out logical functions. Logic devices all have
inputs and outputs, and their output states are dependent upon the conditions applied
to the inputs. The devices that carry out basic logic functions are often referred to as
“gates”.

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3.1 The NOT or inverter gate

A A
Figure 3.1
The NOT gate

Figure 3.1 shows a NOT gate as it is sometimes referred to. The gate basically inverts
the input, so that, if the input was a 1, the output would be a 0, and if the input was a
0, the output would be a 1.

3.2 The AND gate

A
X
B
Figure 3.2
The AND gate

Figure 3.2 shows an AND gate. In order to understand the functions of this gate, refer
to the truth table below.

Input A Input B Output X

0 0 0

1 0 0

0 1 0

1 1 1

In order for the output to go high both inputs must also be high.

3.3 The OR Gate

A
X
B
Figure 3.3
The OR gate

The OR gate is shown in figure 3.3. An OR gate gives a High output whenever there
is a high on any or all of the inputs, as in the truth table below.

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Input A Input B Output X

0 0 0

1 0 1

0 1 1

1 1 1

3.4 The NAND gate

A
B X
Figure 3.4
The NAND gate

A NAND gate (as illustrated in fig 3.4) is in effect a combination of two gates, namely
a NOT gate and an AND gate – hence the name.

Input A Input B Output X

0 0 1

0 1 1

1 0 1

1 1 0

From the truth table above we can see that output X is simply an inverted AND gate.
The symbol of the NAND gate is shown in figure 3.4 above.

3.5 The NOR gate

A
X
B
Figure 3.5
The NOR gate

A NOR gate (illustrated in fig 3.5) is in effect a combination of two gates, namely a
NOT gate and an OR gate.

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Input A Input B Output X

0 0 1

0 1 0

1 0 0

1 1 0

The truth table above shows that the X output is simply an inverted OR gate.

3.6 The XOR gate (exclusive-OR)

A
X
B
Figure 3.6
The XOR gate

An XOR gate (illustrated in fig 3.6) is an exclusive or gate in which the output shows
whether the inputs A and B are the same or different. Therefore, if the two inputs have
the same value, output X will be low. If the two inputs have a different value, output
X will be high.

That is one way of looking at it another way is that it works like an OR gate except in
the last case where both inputs are High then the output is Low.

Input A Input B Output X

0 0 0

1 0 1

0 1 1

1 1 0

The truth table above shows that we get a logic low output when the two inputs are the
same, and a logic high output when the inputs are different. It can therefore be used
to test for equality.

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3.7 The XNOR gate (exclusive-NOR)

A
X
B
Figure 3.7
The XNOR gate

Figure 3.7 illustrates an inverted XOR gate. The output, X, is the exact opposite of a
XOR, as can be seen in the truth table below.

Input A Input B Output X

0 0 1

1 0 0

0 1 0

1 1 1

3.8 Integrated circuits (ICs)

7400

The 7400 IC in figure 3.8 is a Quad 2-input NAND Gate. That is consisting of 4-two
input NAND gates.

Before this can be utilised, one has to apply power to the IC.
Pin 14 is Vcc (5 volts) and pin 7 is GND (0Volts).
We then apply either a high (5 volts) or a low (0 volts) to the inputs of the gate and
monitor the output by means of LEDs or a logic probe.
14 VCC

11
13

12

10

7400
5
1

GND 7

Figure 3.8
Quad 2 input NAND IC

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7402

The 7402 in figure 3.9 is a quad 2-input NOR gate.

Pin 14 is Vcc and pin 7 is ground.

14 VCC

13

12

11

10

7402
5
1

7
GND
Figure 3.9
Quad 2 input NOR IC

7404

The 7404 in figure 3.10 is a hex inverter containing 6 complement gates.

14 VCC

13

12

11

10

7402
5
1

7
GND

Figure 3.10
A NOT gate IC

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7408

The 7408 in figure 3.11 is a quad 2-input AND gate

14 VCC

11
13

12

10

7408
5
1

GND 7
Figure 3.11
Quad 2 input AND IC

7432

The 7432 in figure 3.12 is a quad 2-input OR gate.

14 VCC

13

12

11

10

7482
5
1

7
GND

Figure 3.12
Quad 2 input OR IC

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7486

The 7486 in figure 3.13 is a quad 2-input XOR gate.

14 VCC

13

12

11

10

7486
5
1

7
GND
Figure 3.13
Quad 2 input XOR gate IC

3.9 Nomenclature of ICs

When looking at an IC, you will see that there are often other letters around and be-
tween the numbers. These letters all have meaning, as can be seen in the figure below.

SN 74 ALS 00 N

Package type

Logic Function (Quad 2 input Nand)

Logic Family (Advanced Low-power Schottky)

74 series TTL

Manufacturer (Texas Instruments)

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Identifying the pin numbers

DIP package in figure 3.14

1 2 3

Figure 3.14
This numbering method is used for these packages:

•• DIP (dual in-line package)

•• DIL (dual in-line)
•• SDIP (shrink dual in-line package)
•• SO (small outline)
•• SOIC (small outline integrated circuit)
•• SOJ (small outline J-leaded)
•• SOP (small outline package)
•• SSOP (shrink small outline package)
•• TSOP (thin small outline package)
The pins on an IC are not numbered, so we have to establish which pin is which, as in
figure 3.14. There are two common ways of identifying pin number 1. The first is a dot
over pin 1, and the second is a semicircle. When the IC is rotated so that the semicircle
is on the left of the IC, the bottom left pin under it is pin 1.

The pins are then numbered anti-clockwise.

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ACTIVITY 3.1
For the set of input waveforms in figure 3.15 below, determine the output for the gate
shown and draw the timing diagram.

Figure 3.15

ACTIVITY 3.2
Assume that an enable signal has the waveform shown in figure 3.16 below; assume
that waveform B is also available. Devise a circuit that will produce an active-HIGH
reset pulse to the counter only during the time that the enable signal is LOW

Figure 3.16

myUnisa activity
Log on to myUnisa and go to “Announcements”. Select the announcement that is
study unit 3 and do the self-assessment activity.

References
Refer to the chapter “Logic gates” in the prescribed book, Digital fundamentals, by Floyd.

Experiment
Objective:

To familiarise yourself with the operation of the basic logic elements of the OR gate
and the AND gate, as well as the use of the logic probe.

Components required:

7400 quad 2-input NAND gate

7402 quad 2-input NOR gate
AD2004 analogue/digital trainer
Logic probe

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Procedure:

Build the circuit as shown below:

Remember to identify the pin numbers on the IC as indicated below. Once you have
identified pin 1, you proceed in an anti-clockwise direction as you number the pins.
Example: The pin directly to right of pin 1 would be pin 2, then pin 3, etc.

The wiring of the two circuits is critical and any mistake will cause an error to occur.
The first IC to the left is the 7400 quad 2-input NAND gate. If you refer to data sheets
on the last page of this guide, you will see that there are four NAND gates in a 7400
and we only need to use one. It is also very important to note that the ICs need power,
that is 5V on pin 14 (Vcc), shown in red, and 0V on pin 7 (Gnd). Not all ICs are the
same, so it is important to check the data sheets. The inputs to the 7400 are shown
in blue (pins 13 and 12) and the output in green (pin 11).

The second IC to the right is a 7402 quad 2-input NOR gate. Again we must apply
power to pins 14 and 7 before the IC will function. The inputs to the IC are shown in
yellow and the output in purple. It is now time to build the circuit as shown, and to
establish whether it is working using the truth tables associated with these gates.

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Results of experiment

Name: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Student no: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Results for the NAND gate

Complete the tables below.

Switch 8 Switch 7 Pin 13* Pin 12* Pin 11* LED 8

0 0

0 1

1 0

1 1

* Note these pins should be checked using the logic probe and the results
(high = 1 or low = 0) recorded in the table.

Results for the NOR gate

Complete the tables below.

Switch 2 Switch 1 Pin 11* Pin 12* Pin 13* LED 1

0 0

0 1

1 0

1 1

* Note these pins should be checked using the logic probe and the results
(high = 1 or low = 0) recorded in the table.

Do your results correspond to the theory? _ _ _ _ _ _ _ _ _ _ _ _

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Experiment
Objective:

To familiarise yourself with the operation of a basic combinational circuit.

Components required:

Development board
ICs: 74LS02
74LS00

Procedure:

Build the circuit for the following expression. In order to determine the input and
output pins to the gates, refer to the data sheets on the last page of this study guide.

F = (A+B) . C

A
F
B
C

Results of experiment

Name: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Student no: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

On the breadboard below, draw a wiring diagram to show how you built the circuit.
(Work in pencil in case you make a mistake.)

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Complete the truth table below.

A B C F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

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