Polysilicon Resistor Stability Under Voltage Stress

for Safe-Operating Area Characterization

C. Kendrick, M. Cook, J.P. Gambino*, T. Myers*, J. Slezak**, T. Hirano***, T. Sano***, Y. Watanabe***, K. Ozeki***

ON Semiconductor, 1900 South County Trail, 02818, East Greenwich, RI, USA
* ON Semiconductor, 23400 NE Glisan St., 97030, Gresham, OR, USA
** ON Semiconductor, 1.máje 2594, Roznov pod Radhostem, 756 61, CZ
*** ON Semiconductor, 1-1-1, Sakata, Oizumi-Machi Ora-Gun, Gunma, 370-0596, JP
phone: +1 (401) 886-3352, email: chris.kendrick@onsemi.com

Abstract—High resistance polysilicon resistors have been [7], [9]-[10], silicon diffusion [8]. However, there have been
characterized by DC and pulsed I-V sweep measurements, only a limited number of reports on their resistance stability and
resistance vs. temperature, and DC and pulsed voltage reliability [9]-[10], [14], and how such characterization can be
stress/measurement cycling. The combination of these used to predict safe-operating area (SOA).
measurements along with resistor linearity and electro-migration
rules are used to determine the maximum safe-operating area. It
is shown that the resistance shifts at high current conditions
cannot be explained by electromigration alone, and are instead
attributed to migration of dopants, Si, or hydrogen, either singly
or in combination, both due to high self-heating. The results are
used to create voltage and current checks within SPICE models
allowing for robust design at maximum operating conditions. IR-
OBIRCH physical analysis was performed and shows asymmetric
changes to the resistor head regions.

Index Terms-- polysilicon resistor, resistance stability, safe-

operating area.

I. INTRODUCTION
Polysilicon resistors are widely used in precision analog and
HV power integrated circuit technologies for voltage
references, analog-to-digital conversion, and various other uses
where a higher voltage resistor is required. Unsilicided p-type
polysilicon resistors provide high sheet resistance, and low
voltage and temperature coefficients for convenient circuit
design over a range of product conditions.
There are a number of mechanisms that can affect the
resistance of polysilicon resistors, including mechanical stress
(from the package), self-heating that causes a non-permanent
change in resistance, and electrical degradation that causes a
permanent change in resistance. Mechanical stress effects can
be minimized by optimizing assembly and/or by using resistor
“trimming” with fuses, whereby the final resistor value is
adjusted [1]. Self-heating effects that cause a non-permanent
change in resistance can be measured and modelled knowing
the power dissipated in the resistor, the thermal conductivity of
the surrounding materials, and the temperature coefficient of
resistance of the polysilicon (which varies with doping) [2-5].
Electrical stressing of polysilicon resistors can cause a
permanent change in the resistance, and must be characterized
for reliability [6]-[11]. The permanent changes in resistance
have been attributed to various mechanisms, shown in Fig. 1,
including dopant diffusion (into or out of grain boundaries)
[11]-[13], hydrogen diffusion (into or out of grain boundaries
Figure 1. Schematic of polysilicon resistor degradation mechanisms, (a) dopant
migration or Si migration, (b) metal migration from contacts, and (c) hydrogen
migration. Note that the migration mechanism could either be ion drift in the
electric field or electromigration (EM) due to momentum transfer from electron
motion.
II. EXPERIMENT
A. Resistor fabrication
The p-type high-resistance polysilicon resistors are
fabricated on an 180nm BCD process with 12-40V LDMOS
optimized for low specific on-resistance. The technology was
specifically developed for high power applications requiring
highly efficient power conversion with minimal power losses.
Some application examples include switch-mode power
supplies, Power over Coax, gate drivers, and DC-DC converter
applications.
Fig. 2 shows that the resistor is constructed of 250nm thick
polysilicon over shallow-trench isolation (STI), uses a silicide-

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block mask, and a specific low dose BF2 implant to achieve a In addition, the resistance at low current density
high sheet resistance of 1KΩ/sq. Contact to the resistor is made (V=100mV) was measured from 25oC to 300oC (Fig. 4). Using
to the head of the resistor in a CoSi2 region. a model based on [20], and references therein [16]-[19], we
infer that the temperature rises as high as 450oC before failure.

Figure 3. Current vs voltage and Resistance vs. voltage for polysilicon resistors
Figure 2. High resistance polysilicon resistor (a) layout, and (b) cross section. under DC sweep measured at 30oC; (a) 3 μm x 10 μm resistor and (b) 1.5 μm x
3.6 μm resistor. The black arrow indicates the voltage at which there is
B. Characterization catastrophic failure.
The polysilicon resistors have been electrically
characterized by DC I-V measurements, pulsed I-V vs. time,
Resistance vs. temperature, and DC and pulsed voltage
stress/measurement cycling. These measurements were
performed on two different resistor sizes; 3μm x 10μm and
1.5μm x 3.6μm, and gave similar results.
After stressing the resistors, failing regions of the devices
were localized using the Optical Beam Induced Resistance
Change (OBIRCH) technique [15]. The failing location was
then extracted using a focused ion beam (FIB) cut. Images of
the fail were acquired using transmission electron microscopy
(TEM).

III. RESULTS AND DISCUSSION

The DC I-V characteristics for both poly resistor sizes are
shown in Fig. 3. As voltage is ramped the resistance changes
significantly until catastrophic failure is reached at ~19V and
~8.8V, for the larger resistor and the smaller resistor,
respectively. We attribute this resistance change to self-heating
due to high power dissipation (~3.7mW/μm2). Boron-doped
polysilicon resistors typically have a negative temperature
coefficient of resistance, which is thought to be due to
thermionic emission, thermionic-field emission, and hopping
conduction due to trapping of holes in the grain boundaries.
[16]-[19].
Figure 4. Resistance vs temperature for polysilicon (3 μm x 10 μm). The
resistance decreases with temperature
The voltage and resistance vs. time is shown in Fig. 5 for a
20μs voltage pulse with amplitude of 17V and 8V for the larger
resistor and smaller resistor, respectively. The rise time is
approximately 200ns, however, the resistance value settles to a
constant value over ~5μs. This is the time over which
temperature comes to equilibrium due to self-heating.

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 20 4 overlap with the DC curve (Fig. 7b), both indicating a quasi-
voltage DC degradation behavior. Pulsed I-V characteristics vs. time
show little overshoot and a settling/self-heating time is ~5μs for

Resistance (kOhm)
15 3 this voltage stress, which is approximately equal to the lowest
resistance
pulse width used during reliability testing. It is noted that the
Voltage (V)

10 2 current per contact exceeded the electromigration (EM) current

limits during reliability stress. However, because the
contribution of contact/head resistance to total resistance is
5 1 <1% it is unlikely that 10% change in total resistance can be
due to contact/head resistance changes alone.
(a) W = 3μm, L = 10μm
0 0
000.0E+0
9 5.0E-6 10.0E-6 15.0E-6 20.0E-6 25.0E-64
Time (s)
8
voltage
7

Resistance (kOhm)
3
6
Voltage (V)

5
resistance 2
4
3
2 1
1 (b) W = 1.5μm, L = 3.6μm

0 0
000.0E+0 5.0E-6 10.0E-6 15.0E-6 20.0E-6 25.0E-6
Time (s)

Figure 5. Voltage and Resistance vs. time for a 17V, 20μs voltage pulse on
polysilicon resistors measured at 30oC; (a) 3 μm x 10 μm resistor and (b) 1.5
μm x 3.6 μm resistor.

For resistor stability testing we use wafer-level stress-

measure-stress test routine at 30oC on single devices. Fig. 6
shows the percent of resistance shift increase under different
DC voltage stresses, where higher stress voltages cause
increased degradation. We know there is significant self-
heating at these bias conditions, however the temperature is
expected to drop to 30oC well before the interim resistance
measurements are made.
Figure 6. Percent increase of resistance vs. time for a 3μm x 10μm polysilicon
resistor for 13V, 15V, 17V, and 18V continuous DC stress.
Pulsed voltage stress at a constant voltage amplitude of 17V
voltage stress is compared to DC conditions in Fig. 7a. The
degradation curves at 1% duty cycle and different frequencies
approach the same value. Also, when pulsed degradation
curves are adjusted for total accumulated stress time they
Figure 7. (a) Percent resistance increase vs. time for pulsed 17V voltage stress
at different duty cycle and frequency, and (b) adjusted for total stress
accumulated time.
Failure analysis was conducted on the 3μm x 10μm resistors
that were stressed at 3 different conditions; Un-stressed, a 0-
20V DC sweep resulting in an open circuit, and a 17V DC stress
resulting in a 25% resistance increase. Fig. 8 shows the IR-
OBIRCH signal images for these three conditions. The un-
stressed sample in Fig 8a shows symmetric OBIRCH signals in
the resistor head regions, while the open circuit sample in Fig
8b shows damage to the left-side head of the resistor. The 17V
stress sample shown in Fig. 8c-d shows that the OBIRCH signal
strengths are different for opposite bias polarity, indicating
some physical difference between the left and right head
regions.
Scanning Transmission Electron Microscopy (STEM) images
indicate no observable difference between an unstressed
resistor and a resistor stressed to a 25% resistance increase (Fig.
9). A likely mechanism for the 25% resistance increase is
hydrogen depassivation at grain boundaries due to self-heating
of the resistor (~ 450oC) and due to drift of hydrogen in electric
field [5,9]. For samples that are stressed to failure, it is likely
that there is significant migration of material resulting in voids
in the structure.

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 1.0E+07
t10%
1.0E+05 t1%
1.0E+03 Expon. (t10%)
Expon. (t1%)

TTF (years)
1.0E+01
0.2 yrs DC
1.0E-01

1.0E-03

1.0E-05
Figure 8. Backside IR-OBIRCH images, (a) no stress, (b) 0-20V DC sweep
which causes an open circuit, (c) 17V DC stress with 25% resistance increase 1.0E-07
with Vds = +4.0V, and (d) same sample 17V DC stress with Vds = -4.0V. 0.0 0.5 1.0 1.5 2.0
Current Density (mA/um)
Figure 10. Extracted TTF for 1% and 10% increase of resistance vs. current
density.

the device dimensions and bias conditions. For instance, several

maximum duration times can be specified for several maximum
voltage and/or current SOA limits, that are convenient to
implement based on existing measurement data.
TABLE I. INPUT FOR SOA SPICE MODEL CHECKS AT DIFFERENT DUTY
CYCLES.

Figure 9. Bright field STEM cross-section images of poly resistors with (a) no
stress and (b) 17V DC stress with 25% resistance increase. There is no
observable difference between the two samples. IV. CONCLUSION
From the degradation data in Fig. 6 and 7 we extract the High resistance polysilicon resistors have been electrically
time-to-failure (TTF) at 1% and 10% resistance shifts. These characterized by DC I-V measurements, pulsed I-V vs. time,
are plotted in Fig. 10 vs. the current density at stress conditions. Resistance vs. temperature, and DC and pulsed voltage
Using an exponential fit allows us to predict the TTF for lower stress/measurement cycling. The combination of these
current density at various duty cycles and arbitrary frequency, measurements along with resistor linearity and electro-
shown in Table I. migration vs. current density are used to determine the
maximum safe-operating area. These data have further been
Fig. 11 shows the linearity of the high-resistance polysilicon used to create voltage and current density checks within SPICE
resistor vs. current density where a conservative SOA has been models allowing for robust design at maximum operating
set at 100 μA/μm for <0.5% change in resistance. Although conditions. No structural changes are observed in resistors
such linearity may be required for demanding analog functions, stressed with up to a 25% resistance increase, suggesting that
this criteria can be too limiting for many applications. Relaxing the degradation is due to hydrogen depassivation of grain
linearity to 5-10% brings the current density in the range of boundaries.
resistance shift and EM limitations.
Incorporating all resistor current density limitations into a
SPICE model SOA check can be achieved by utilizing standard
commands in SPICE simulators such as assert in Spectre. There
are numerous supported arguments of the command, and the
arguments enable users to tailor the SOA checks to meet
specific needs. Even expressions can be utilized to take into
account electrical properties depending on

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Figure 11. 1KΩ/sq. poly resistor linearity vs. current density for (a) 0.45μm and
(b) 2.7 μm width resistors. For some analog circuits, resistor linearity of better
than 0.5% is required.
ACKNOWLEDGMENT
The authors thank the staff of the ON Semiconductor
Gresham wafer fab for assistance with processing the wafers.
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