HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
• Single 3.3±0.3V power supply Note) • Auto refresh and self refresh

• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms

• JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock - 1, 2, 4 or 8 for Interleave Burst

• Data mask function by UDQM or LDQM • Programmable CAS Latency ; 2, 3 Clocks

• Internal four banks operation

ORDERING INFORMATION

Part No. Clock Frequency Power Organization Interface Package

HY57V641620HGT-5/55/6/7 200/183/166/143MHz
HY57V641620HGT-K 133MHz
HY57V641620HGT-H 133MHz
Normal
HY57V641620HGT-8 125MHz
HY57V641620HGT-P 100MHz
HY57V641620HGT-S 100MHz 4Banks x 1Mbits
LVTTL 400mil 54pin TSOP II
HY57V641620HGLT-5/55/6/7 200/183/166/143MHz x16

HY57V641620HGLT-K 133MHz
HY57V641620HGLT-H 133MHz
Low power
HY57V641620HGLT-8 125MHz
HY57V641620HGLT-P 100MHz
HY57V641620HGLT-S 100MHz

Note : VDD(Min) of HY57V641620HG(L)T-5/55/6 is 3.135V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.8/Dec. 02 1
 HY57V641620HG
PIN CONFIGURATION
VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 VDDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 VSS
LDQM 15 0.8mm pin pitch 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock
rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

BA0,BA1 Bank Address
Selects bank to be read/written during CAS activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

A0 ~ A11 Address
Auto-precharge flag : A10

Row Address Strobe,

RAS, CAS and WE define the operation
RAS, CAS, WE Column Address Strobe,
Refer function truth table for details
Write Enable

LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Rev. 0.8/Dec. 02 2
 HY57V641620HG
FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh logic Internal Row

& timer counter

CLK 1Mx16 Bank 3

Row active Row 1Mx16 Bank 2

CKE Pre

X decoders
Decoders 1Mx16 Bank 1
CS X decoders 1Mx16 Bank 0
State Machine

X decoders
RAS DQ0

Sense AMP & I/O Gate

X decoders
Memory DQ1

I/O Buffer & Logic

CAS refresh Cell
Array
WE Column Column
Active
Pre
UDQM Decoders DQ14
DQ15
LDQM Y decoders

Column Add
Bank Select Counter

A0 Address
A1 Registers
Address buffers

Burst
Counter

A11
BA0
CAS Latency
BA1 Mode Registers Data Out Control Pipe Line Control

Rev. 0.8/Dec. 02 3
 HY57V641620HG
ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Ambient Temperature TA 0 ~ 70 °C

Storage Temperature TSTG -55 ~ 125 °C

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD 1 W

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA=0 to 70°C)

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1,2

Input High Voltage VIH 2.0 3.0 VDDQ + 2.0 V 1,3

Input Low Voltage VIL VSSQ - 2.0 0 0.8 V 1,4

Note :
1.All voltages are referenced to VSS = 0V
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3VNote2, VSS=0V)

Parameter Symbol Value Unit Note

AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise / Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL 50 pF 1

Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V

Rev. 0.8/Dec. 02 4
 HY57V641620HG
CAPACITANCE (TA=25°C, f=1MHz)

Parameter Pin Symbol Min Max Unit

Input capacitance CLK CI1 2 4 pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS, CI2 2.5 5 pF

CAS, WE, UDQM, LDQM

Data input / output capacitance DQ0 ~ DQ15 CI/O 2 6.5 pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 Ω

Output Output

50pF
50pF

DC Output Load Circuit AC Output Load Circuit

DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3VNote3)

Parameter Symbol Min. Max Unit Note

Input Leakage Current ILI -1 1 uA 1

Output Leakage Current ILO -1 1 uA 2

Output High Voltage VOH 2.4 - V IOH = -4mA

Output Low Voltage VOL - 0.4 V IOL = +4mA

Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6

Rev. 0.8/Dec. 02 5
 HY57V641620HG
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3VNote5, VSS=0V)

Speed
Parameter Symbol Test Condition Unit Note
-5 -55 -6 -7 -K -H -8 -P -S

Burst length=1, One bank active

Operating Current IDD1 100 95 90 85 85 85 80 80 80 mA 1
tRC ≥ tRC(min), IOL=0mA

Precharge Standby IDD2P CKE ≤ VIL(max), tCK = min 2 mA

Current
in Power Down Mode IDD2PS CKE ≤ VIL(max), tCK = ∞ 2 mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= min
IDD2N Input signals are changed one time 15 mA
Precharge Standby
during 2clks. All other pins ≥ VDD-
Current
0.2V or ≤ 0.2V
in Non Power Down Mode
CKE ≥ VIH(min), tCK = ∞
IDD2NS 12 mA
Input signals are stable.

IDD3P CKE ≤ VIL(max), tCK = min 6 mA

Active Standby Current
in Power Down Mode
IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCK

= min
IDD3N Input signals are changed one time 30 mA
Active Standby Current during 2clks. All other pins ≥ VDD-
in Non Power Down Mode 0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞

IDD3NS 20 mA
Input signals are stable.

CL=3 170 160 150 150 150 150 120 120 120 mA 1
Burst Mode Operating tCK ≥ tCK(min), IOL=0mA
IDD4
Current All banks active CL=2 NA NA NA NA 120 mA

Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 160 mA 2

1 mA 3
Self Refresh Current IDD6 CKE ≤ 0.2V
400 uA 4

Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V641620HGT-6/7/K/H/P/S
4.HY57V641620HGLT-6/7/K/H/P/S

Rev. 0.8/Dec. 02 6
 HY57V641620HG
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-5 -55 -6 -7 -K -H -8 -P -S
Parameter Symbol Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

CAS Latency =
tCK3 5 5.5 6 7 7.5 7.5 8 10 10 ns
3
System clock 100
1000 1000 1000 1000 1000 1000 1000 1000
cycle time 0
CAS Latency =
tCK2 10 10 10 10 7.5 10 10 10 12 ns
2

Clock high pulse width tCHW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1

Clock low pulse width tCLW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1

CAS Latency =
tAC3 - 4.5 - 5 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns
3
Access time
2
from clock
CAS Latency =
tAC2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns
2

Data-out hold time tOH 1.5 - 2 - 2 - 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns

Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Address hold time tAH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

CKE hold time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Command hold time tCH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1.5 - 1.5 - 1.5 - 1 - 1 - 2 - ns

CAS Latency =
tOHZ3 3 6 ns
CLK to data 3
output in high 5.0 5.4 5.4 5.4 5.4 5.4 6 6
Z-time CAS Latency =
tOHZ2 3 6 ns
2

Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate

Rev. 0.8/Dec. 02 7
 HY57V641620HG

AC CHARACTERISTICS II

-5 -55 -6 -7 -K -H -8 -P -S
Symbo
Parameter Unit Note
l
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Operation tRC 55 - 55 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns
RAS Cycle
Time
Auto Refresh tRRC 60 - 60 - 60 - 63 - 65 - 65 - 68 - 70 - 70 - ns

RAS to CAS Delay tRCD 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns

100 100
RAS Active Time tRAS 38.5 100K 38.5 100K 42
K
42 120K 45 120K 45 120K 48
K
50 120K 50 120K ns

RAS Precharge Time tRP 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns

RAS to RAS Bank Active

Delay
tRRD 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns

CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK

Write Command to Data-In

Delay
tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK

Data-In to Precharge
Command
tDPL 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK

Data-In to Active Command tDAL 5 - 5 - 5 - 4 - 4 - 4 - 5 - 3 - 3 - CLK

DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK

DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK

MRS to New Command tMRD 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK

CAS Latency tPROZ 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK

Precharge to =3 3
Data Output
Hi-Z CAS Latency tPROZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK
=2 2

Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK

Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK 1

Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms

Note :
1. A new command can be given tRRC after self refresh exit

Rev. 0.8/Dec. 02 8
 HY57V641620HG
DEVICE OPERATING OPTION TABLE

HY57V641620HG(L)T-5

CAS Latency tRCD tRAS tRC tRP tAC tOH

200MHz(5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 4.5ns 1.5ns
183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns

HY57V641620HG(L)T-55

CAS Latency tRCD tRAS tRC tRP tAC tOH

183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns
143MHz(7ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns

HY57V641620HG(L)T-6

CAS Latency tRCD tRAS tRC tRP tAC tOH

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

HY57V641620HG(L)T-7

CAS Latency tRCD tRAS tRC tRP tAC tOH

143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

HY57V641620HG(L)T-K

CAS Latency tRCD tRAS tRC tRP tAC tOH

133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

HY57V641620HG(L)T-H

CAS Latency tRCD tRAS tRC tRP tAC tOH

133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

Rev. 0.8/Dec. 02 9
 HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM

HY57V641620HG(L)T-8

CAS Latency tRCD tRAS tRC tRP tAC tOH

125MHz(8ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 3CLKs 6ns 3ns
83MHz(12ns) 3CLKs 3CLKs 6CLKs 9CLKs 2CLKs 6ns 3ns

HY57V641620HG(L)T-P

CAS Latency tRCD tRAS tRC tRP tAC tOH

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns

HY57V641620HG(L)T-S

CAS Latency tRCD tRAS tRC tRP tAC tOH

100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.8/Dec. 02 10
 HY57V641620HG
COMMAND TRUTH TABLE

A10/
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR BA Note
AP

Mode Register Set H X L L L L X OP code

H X X X
No Operation H X X X
L H H H

Bank Active H X L L H H X RA V

Read L
H X L H L H X CA V
Read with Autoprecharge H

Write L
H X L H L L X CA V
Write with Autoprecharge H

Precharge All Banks H X

H X L L H L X X
Precharge selected Bank L V

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

A9 Pin High
Burst-READ-Single-WRITE H X L L L L X
(Other Pins OP code)

Entry H L L L L H X

Self Refresh1 H X X X X
Exit L H X
L H H H

H X X X
Entry H L X
L H H H
Precharge
X
power down H X X X
Exit L H X
L H H H

H X X X
Entry H L X
Clock
L V V V X
Suspend
Exit L H X X

Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation

Rev. 0.8/Dec. 02 11
 HY57V641620HG
PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720) 10.262(0.4040)
10.058(0.3960)

0.150(0.0059) 1.194(0.0470)
0.050(0.0020) 0.991(0.0390)

0.400(0.016) 5deg 0.597(0.0235) 0.210(0.0083)

0.80(0.0315)BSC 0deg 0.406(0.0160) 0.120(0.0047)
0.300(0.012)

Rev. 0.8/Dec. 02 12