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A new algorithm for a high-modulation frequency and high-speed digital lock-in amplifier

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 Measurement Science and Technology

Meas. Sci. Technol. 27 (2016) 015701 (6pp) doi:10.1088/0957-0233/27/1/015701

A new algorithm for a high-modulation

frequency and high-speed digital lock-in
amplifier
G L Jiang1, H Yang1,2, R Li1 and P Kong3
1
School of Optical-Electrical and Computer Engineering, Shanghai Key Lab of Modern Optical System,
Engineering Research Center of Optical Instrument and System, Ministry of Education,
University of Shanghai for Science and Technology, Shanghai 200093, People’s Republic of China
2
School of Chemical Engineering, The University of Adelaide, Adelaide, SA 5005, Australia
3
Foundation department, Shanghai Medical Instrumentation College, Shanghai 200093,
People’s Republic of China

E-mail: yangusst@yeah.net

Received 21 February 2015, revised 16 October 2015

Accepted for publication 3 November 2015
Published 25 November 2015

Abstract
To increase the maximum modulation frequency of the digital lock-in amplifier in an online
system, we propose a new algorithm using a square wave reference whose frequency is an
odd sub-multiple of the modulation frequency, which is based on odd harmonic components
in the square wave reference. The sampling frequency is four times the modulation frequency
to insure the orthogonality of reference sequences. Only additions and subtractions are
used to implement phase-sensitive detection, which speeds up the computation in lock-in.
Furthermore, the maximum modulation frequency of a lock-in is enhanced considerably. The
feasibility of this new algorithm is tested by simulation and experiments.

Keywords: digital lock-in amplifier, modulate frequency, phase-sensitive detector

(Some figures may appear in colour only in the online journal)

I. Introduction in general microprocessors. A lock-in capable of high-speed

Lock-in amplifiers (LIAs) have been widely used in science
and engineering as a useful weak signal detection instrument
[1–3]. Based on the theory of correlation detection, it mea-
sures the phase and magnitude of low-level periodic signals,
even when these signals are buried in noise. LIAs work ideally
like a narrow-band filter, allowing the frequencies of interest
to pass while ignoring all other frequencies simultaneously.
Originally, LIAs were made of analogue electronics, which
had good performance in most applications but also exhib-
ited instability, gain error, and thermal shifting. Consequently,
much attention has been paid to digital lock-in amplifiers
(DLIAs), which, by contrast, have much better performance
in certain aspects.
DLIAs have been extensively studied, with several reviews
of the field [4–6]. However, it is time-consuming to perform
the multiplications between the signal and the reference wave
and high-modulation frequency measurements is very desir-
able. Some studies have already considered high-performance
minimal-computation algorithms to reduce the time-consump-
tion of digital signal processors. Li et al proposed an algo-
rithm that combines oversampling and the lock-in amplifier
[7]. They configured the sampling frequency as a multiple of
four of the modulation frequency, and the continuous sampled
values are averaged to produce four points in every period of
the signal. Therefore, it eliminates almost all multiplication
operations and remarkably reduces the number of addition
operations, resulting in an easier implementation of the algo-
rithm. Masciotti et al considerably reduced the computation
time of multi-frequency DLIAs by using matrix multiplica-
tion on a personal computer [8].
However, none of them have considered the high require-
ments of the modulation frequency and response time in
online systems, such as cable capacitance measurement [9].

0957-0233/16/015701+6$33.00 1 © 2016 IOP Publishing Ltd Printed in the UK

Meas. Sci. Technol. 27 (2016) 015701 G L Jiang et al

The input signal i(t ) that is produced after the excitation

signal passes through an unknown system, which would
modify the magnitude and phase of the signal but also add
noise, n(t), to it, is described in equation (2),
i(t ) = A sin(ω 0t + ϕ ) + n(t )
(2)
The LIA amplifies this signal to a level adequate for detec-
tion and multiplies it by the orthogonal reference components,

Ri(t) = i(t ) × rs(t )

Figure 1. Diagram of a cable capacitance measurement system. ∞


=
2A
π
∑ 2n 1− 1 cos [2(1 − n)ω t + ϕ]0
In cable manufacturing, on-line and high-speed measurement n=1
∞
of cable capacitance in water is needed to monitor the capaci-
tance of the product, as shown in figure 1. The measurement −
2A
π
∑ 2n 1− 1 cos [2nω t + ϕ] + n (t )
0 s (3)
range of cable capacitance is 0–400 pF m−1, and the current n=1

flowing through the capacitor is generally i = uωc (u and ω

are the amplitude and angular frequency of the modulation Rq(t) = i(t ) × rc(t )
signal, and c is the value of the cable capacitance). Therefore, ∞
n+1
a high modulation frequency (>100 KHz) is needed to make

=
2A
π
∑ (2−n1−) 1 sin [2(1 − n )ω 0t + ϕ]
the current i suitable for the gain amplifier. For a cable moving n=1
∞
through the detection area, with a side length of 20 mm and at n+1
a line speed of 50 m s−1, more than 2500 cable capacitance +
2A
π
∑ (2−n1−) 1
n=1
sin [2nω 0t + ϕ] + nc(t ) (4)
values should be measured in 1 s. A real-time system requires
a quick response from the LIA, while the high modulation where rs(t ) and rc(t ) are the in-phase and quadrature refer-
frequency produces a large amount of data, which decreases ences, and ns(t ) and nc(t ) represent the functions of noise.
the response of the LIA. Figure 1 shows a schematic diagram All of the ac components would be filtered out using a low-
of a cable capacitance measurement system. pass filter, only keeping the dc component ideally. Thus, the
In this work, we suggest a new algorithm to increase the two signals X and Y, which correspond to the real and imagi-
speed and maximum modulation frequency of a DLIA based nary parts of the input signal, are obtained,
on an odd harmonics modulation frequency. The modulation
2A
frequency, fm, is 2k  −  1 times that of the square reference X = Ri(t ) * hL (t ) ≈
(5) cos(ϕ )
signal, fr. Because the Fourier component of the square refer- π
ence signal has odd harmonics, it will produce a single dc term 2A
containing the amplitude and phase of the input component at Y = Rq(t ) * hL (t ) ≈
(6) sin(ϕ )
π
that frequency. The algorithm considerably improves the max-
imum modulation frequency of the DLIA for a general pro- Therefore, the phase and magnitude of the input signal can be
cessor and reduces the time-consumption. The computations computed easily from measurements of the X and Y signals.
in this algorithm are only additions and subtractions, with no
multiplication operations, which makes the algorithm easier II.B. Improved lock-in amplifier
and faster to be implemented. The feasibility of the algorithm
was tested by simulations and experiments. Traditional LIAs work with a fixed frequency of reference that
is equal to the modulation frequency. However, this article
proposes a method that uses as a reference a square wave
II. Lock-in amplifier basics whose frequency is an odd sub-multiple of the modulation fre-
quency. Because the reference frequency is much lower than
II.A. Standard lock-in amplifier
the modulation frequency, the burden of the microprocessor
A classic orthogonal vector lock-in amplifier consists of an can be reduced and the response of the system would be faster.
excitation signal, two orthogonal reference signals, a phase- Then, the response of the phase-sensitive detector as in (3)
sensitive detector, and a low-pass filter. The reference signals and (4) would be changed,
used in LIAs can be sinusoidal or square signals. In the latter
Ri′ (t ) = i ′(t ) × r s′ (t )
case, the square reference is sensitive to its odd harmonics, but ∞
the time-consumption is lower and it is easier to implement [5].
The Fourier expansion of the square reference signal is =
2A
π
∑ 2n 1− 1 cos{ [ω
n=1
m + (2n − 1)ωr ]t + ϕ}
given by ∞
∞
−
2A
∑ 2n 1− 1 cos{ [ω − (2n − 1)ωr ]t + ϕ} + ns′ (t )
4 1
∑
m
r (t ) =
(1) sin [(2n − 1)ω 0t ] π n=1
π n = 1 2n − 1  (7)

2
Meas. Sci. Technol. 27 (2016) 015701 G L Jiang et al

sequence should be M also, although it is only one period. The

orthogonal reference sequences S[n] and C[n] can be gener-
ated by a microprocessor synchronously,
S [n] = {1, 1,  1, 1}M , {−1, −1,  − 1, −1}M
(13) 2 2

C [n] = {−1, , −1}M , {1, 1,  1, 1}M , {−1, , −1}M (14)

4 2 4

Figure 2. Diagram of the signal processing in the DLIA.
Therefore, the output of phase-sensitive detection can be
R′q(t ) = i ′(t ) × r ′c(t )
simplified as,
∞ ⎡ M − 1⎤
Ri [n] = I [n] × S [n] = I [0] + I [1] +  + I ⎢
⎣ 2 ⎥⎦
n+1
=
2A
π
∑ (2−n1−) 1 sin{ [ωm + (2n − 1)ωr ] t + ϕ} 
⎡M⎤ ⎡ M + 1⎤
n=1

−I⎢ ⎥−I⎢
⎣ 2 ⎥⎦
∞
⎣2⎦
n+1 −  I [M ] (15)
+
2A
π
∑ (2−n1−) 1
n=1
sin{ [ωm − (2n − 1)ωr ] t + ϕ} + n′c(t )


⎡ M − 1⎤
(8)
Rq [n] = I [n] × C [n] = I [0] − I [1] −  − I ⎢
Here, ωm and ωr are the angular frequencies of the modula- ⎣ 4 ⎥⎦
tion signal and reference signal. Likewise, the ac frequencies  ⎡M⎤ ⎡ M + 1⎤ ⎡ 3M − 1 ⎤
+I⎢ ⎥+I⎢
⎣ 4 ⎥⎦
+ I⎢
are filtered by a low-pass filter, ⎣4⎦ ⎣ 4 ⎥⎦
1 2A ⎡ 3M ⎤ ⎡ 3M + 1 ⎤
−I⎢
⎣ 4 ⎥⎦
−I⎢
⎣ 4 ⎥⎦
X ′ = Ri′ (t ) * hL (t ) ≈
(9) × cos(ϕ ) −  − I [M ] (16)
2k − 1 π

Notice that M/4 must be an integer number, as otherwise the

1 2A
Y′ = R′q(t ) * hL (t ) ≈
(10) × sin(ϕ )
2k − 1 π onal. Therefore, the sampling frequency must be constrained
Although, the dc components X ′ and Y′ have 1/2k − 1 attenua-
tion (i.e. the Signal to Noise Ratio (SNR) declines to 1/2k − 1)
compared to those produced with the traditional LIAs, as seen
in equations (9) and (10), the phase and magnitude of the
input signal can still be easily computed,
π tion frequency fm, and the number of sampled points M is
A = (2k − 1) ×
(11) X′2 + Y ′2
2 20 × (2k − 1). Figures 3(a) and (b) show the in-phase wave-
⎛Y′ ⎞
ϕ = tan−1⎜ ′ ⎟
(12)
⎝X ⎠
III. Implementation of the proposed DLIA
III.A. High-modulation frequency for the DLIA
Figure 2 shows the signal processing of the DLIA, which
can be easily implemented in a general microprocessor. The
discrete input sequence I[n] is produced by an analogue-to-
digital converter, which takes M samples of the input signal
i(t ) at a sampling frequency fs. Then, this discrete signal is
multiplied with the orthogonal reference sequences S[n] and
C[n] for the phase and magnitude discrimination.
In this DLIA, the sampling frequency fs is N times the
modulation frequency fm, which is 2k  −  1 times the refer-
ence frequency fr. Sampling a single computing period, there
would be M points that equal (2k  −  1)  ×  N. This means
that these M sampled points embody 2k  −  1 periods of the
input signal, and the total number of points in the reference
two reference sequences S[n] and C[n] can never be orthog-
by
fs = 4h × fm , 1 ⩽ h,
(17)
where h is an integer.
Figure 3 shows the in-phase waveform of phase-sensitive
detection of traditional DLIAs and the novel proposed DLIA.
The sampling frequency fs is twenty times the modula-
forms (Ri1[n] and Ri2[n]) of the proposed DLIA (k  =  3) and the
traditional DLIA with the same sampled points. Figure 3(c)
and (d) are their main frequency-domain components (on the
x-axis, f refers to fr). Figure 3 shows that the proposed DLIA
can effectively improve the maximum modulation frequency
for the same reference frequency.
From Equations (13) and (14), the multiplication operation
has been replaced completely in this orthogonal vector arith-
metic by addition and subtraction operations. Moreover, the
burden of microprocessor computation and memory has been
reduced considerably because the reference frequency is lower
than the modulation frequency, and the reference sequence no
longer needs to be saved. Thus, the time consumption of com-
putation is reduced greatly, while the maximum modulation
frequency in real-time measurement is improved.
The modulation frequency and number of computation
operations in a phase-sensitive detector of the newly proposed
DLIA design and the classic DLIA algorithm are shown in
table 1. The condition is that the signals are sampled at the
same sampling frequency fs in q periods, and the total number
of sampled data points is M as well. Along with the increase
of the modulation frequency and sampling periods, the

3
Meas. Sci. Technol. 27 (2016) 015701 G L Jiang et al

Figure 3. In-phase waveform of the phase-sensitive detector in the proposed DLIA, where the number of sampled points is 100. (a) The
waveform of the in-phase component Ri1[n] in this proposed DLIA, taking fm = 5 fr. (b) The waveform of the in-phase component Ri2[n]
in a traditional DLIA, fm = fr. (c) The frequency-domain of the in-phase component in this proposed DLIA, taking fm = 5 fr. (d) The
frequency-domain of the in-phase component in a traditional DLIA, fm = fr.

Table 1. The modulation frequency and computational cost in a ⎛ df ⎞

H ⎜ f = s ⎟ = 0, d ≠ [0, nN ]
⎝ M⎠
phase-sensitive detector. (21)
The classic This newly
DLIA algorithm proposed DLIA The number d is an integer. The frequency response of the
filter is shown as follows,
Number of multiplications 2M 0
Number of additions
The modulation frequency
2(M  −  1)
f0
2(M  −  1)
(2k − 1)f0
H( f ) =
1
sin Mπ f −jπ(M − 1)f
s
e
( ) f

( )
(22) fs
M sin π f
fs
computational cost of this algorithm is much lower than that
of the classic algorithm. When M is larger than ten, the bandwidth is approximately
0.443fs /M . Because the ability of noise attenuation in an LIA
relies on the bandwidth of the low-pass filter, it is feasible to
III.B. Digital low-pass filter use a very narrow-bandwidth low-pass filter to reduce noise
It is well known that, for white noise, the optimum finite by improving the filter length M. However, this narrow band-
impulse response (FIR) filter is a simple averaging filter that width low-pass filter demands a longer measurement time.
has equal coefficients at each point [10] Therefore, a trade-off between short measurement and high
noise reduction must be found for each application.
1 Figure 4 shows the frequency response of a 100-point aver-
hL [n] = .
(18)
M aging filter and the frequency domain of the signals Ri1[n]
Thus, the X[n] and Y[n] signals are given by and Ri2[n] after passing the filter at the same condition as for
figure 3. Notice that the frequencies to which the unwanted
1 1 2A components in the DLIA have been shifted are also frequencies
X [n] = Ri [n] ×
(19) ≈ × cos(ϕ )
M 2k − 1 π at which the filter’s frequency response is zero. This means that
the X[n] and Y[n] signals will be free from these distortions. The
1 1 2A calculation formula of phase and magnitude can be obtained as,
Y [n ] = R q [n ] ×
(20) ≈ × sin(ϕ )
M 2k − 1 π π
A = (2k − 1) ×
(23) X [n]2 + Y [n]2
Generally, M is also called the integral time and is equal to the 2
number of sampled points in a measuring period. For the sam- ⎛ Y [n ] ⎞
pling frequency fs, an M -point averaging filter has a frequency ϕ = arctan ⎜ ⎟
response of zero as follows,
(24) ⎝ X [n ] ⎠

4
Meas. Sci. Technol. 27 (2016) 015701 G L Jiang et al

Figure 4. The procedures of the averaging filter remove the ac component and obtain the dc component in the DLIA. (a) Frequency
response of the 100-point averaging filter. (b) Frequency components of the Ri1[n] signal overlaid on the averaging filter frequency response.
(c) Frequency components of the Ri2[n] signal overlaid on the averaging filter frequency response.

IV. Experimental validation
IV.A. Simulation
To validate the feasibility of the proposed algorithm, a series
of simulations were carried out on a personal computer by
LABVIEW. For the simulation test, the reference frequency
was always set to 10 KHz, the modulation frequency was
2k  −  1 times the reference frequency, the sampling frequency
was twenty times the modulation frequency and the input
signal was a sine wave of zero initial phase with added white
noise. Different ratios of the modulation frequency and refer-
ence frequency are generated by changing the value k for a
comparison between the actual value and the calculated one.
The calculated results are shown in the following table 2.
The results in table 2 show that the calculated amplitude
does not depend on the ratio 2k  −  1 between the modulation
frequency and reference frequency. This means that a DLIA
can work with an input signal for which the frequency is
higher than the frequency in the square reference signal. The
simulation result well-validated the feasibility of the proposed
algorithm and confirmed the result of the theoretical analysis.
IV.B. Experiment
To validate the proposed DLIA with experimental data, a dig-
ital LIA based on TMS320F28335 digital signal processing
(DSP) was implemented. The experimental test was carried
out with a fixed reference frequency fr = 20 KHz, and the

5
Meas. Sci. Technol. 27 (2016) 015701
Table 2. The calculated results of different amplitudes and ratios (2k  −  1) between the modulation frequency and reference frequency.
The actual amplitude (v) k  =  1 k  =  2
0.001 00 0.001 04 0.001 15
0.010 00 0. 009 99 0. 010 25
0.100 00 0. 100 13 0. 099 94
0.500 00 0. 500 61 0. 500 46
1.000 00 1. 000 96 1. 000 95
Table 3. The number of outputs in a traditional DLIA and the proposed DLIA with different reference frequencies, which are all measured
within 1 s.
Traditional DLIA k  =  1 k  =  2
3 3 3 3
1.5 × 10 2.2 × 10 2.6 × 10
sampled points in each measurement period were the same.
The modulation frequency fm = (2k − 1)fr was varied by
changing the value of k, while the sampling frequency was
20 times higher, i.e. fs = 20 fm. The excitation signal was
passed through a capacitance with a known value of 10 pf.
The responses of this system were measured by the traditional
DLIA and the proposed DLIA. Then, we count their output
numbers in a measurement time of 1 s. Obviously, more output
numbers represent a higher-speed measurement and also a
better real-time measurement. The numbers of the outputs are
shown in the following table 3.
As mentioned in the introduction, the measurement of cable
capacitance requires a modulation frequency of more than 100
KHz, and more than 2500 cable capacitance values should be
measured in 1 s. Consequently, it is convenient to judge whether
a DLIA meets the response speed of the system by counting
the number of output values in a second. The results in table 3
show that the traditional DLIA cannot meet the requirement
of modulation frequency (100 KHz) and measurement time,
while the proposed DLIA can meet both requirements by
using k ⩾ 3. Therefore, the modulation frequency of DLIA is
improved greatly compared to traditional DLIA at the same ref-
erence frequency. Furthermore, the response speed of a DLIA
can be improved by increasing the value of k. Thus, the pro-
posed algorithm can effectively improve the maximum modula-
tion frequency of an LIA in a real-time measuring system.
V. Conclusions
In this paper, a new algorithm for a high-modulation frequency
and high-speed DLIA was proposed. The algorithm simplifies
the orthogonal vector arithmetic in a DLIA because the multi-
plication operation has been replaced completely by the addi-
tion and subtraction operations. Thus, the speed was improved
remarkably. Furthermore, it also reduces the burden of general
microprocessor memory as the reference sequence does not
need to be saved. Finally, the novel algorithm improves the max-
imum modulation frequency of a lock-in because the frequency
of the reference signal is lower than the modulation frequency.
However, this results in a reduction of the SNR by a factor of
(2k  −  1). Further study is required to avoid this reduction.
In a word, the novel DLIA is capable of high speed and high
6
G L Jiang et al
The calculated amplitudes
k  =  3 k  =  4 k  =  5
0.009 73 0.001 23 0.001 01
0. 009 92 0. 009 93 0.010 30
0. 100 31 0. 100 22 0. 099 92
0. 500 68 0.500 11 0.500 17
1. 001 32 1.001 01 1.001 02
k  =  3 k  =  4 k  =  5
3
3.0 × 10 3.3 × 10 3.5 × 103
modulation frequency and is able to be implemented in a general
microprocessor to measure the responses of systems that have
a very high demand on the modulation frequency in real-time.
Acknowledgments
This work has been supported by the National Natural Science
Foundation of China (11572201), the Innovation Program of
Shanghai Municipal Education Commission (15ZZ072), and
the Hujiang Foundation of China (C14002).
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