RECENT DEVELOPMENTS IN PANEL LEVEL PACKAGING

Tanja Braun, Mathilde Billaud, Hannes Zedel, Lutz Stobbe, Karl-Friedrich Becker, Ole Hoelck,
Markus Wöhrmann, Lars Boettcher, Michael Töpper, R. Aschenbrenner
Fraunhofer Institute for Reliability and Microintegration
Gustav-Meyer-Allee 25, 13355 Berlin, Germany
tanja.braun@izm.fraunhofer.de

Steve Voges, Klaus-Dieter Lang, Martin Schneider-Ramelow

Technical University Berlin, Microperipheric Center
Gustav-Meyer-Allee 25, 13355 Berlin, Germany

ABSTRACT
Panel Level packaging (PLP) is one of the latest packaging
trends in microelectronics. Besides technology
developments towards heterogeneous integration also
larger substrates formats are targeted. Fan-out Wafer Level
manufacturing is currently done on wafer level up to
12”/300 mm and 330 mm diameter respectively. For higher
productivity and therewith lower costs, larger form factors
are introduced. Instead of following the wafer level
roadmaps to 450 mm, panel level packaging might be the
next big step. Upscaling of technology when moving from
wafer to panel level as well as the use or adaptation of
existing large area tools and materials as e.g. from Printed
Circuit Board (PCB) or Liquid Crystal Display (LCD)
manufacturing is not possible. Additionally, the missing
standardization in sizes is another challenge. Considered
panel dimensions ranges from 300x300 mm² to
457x610 mm³ or 510x515 mm² up to 600x600 mm² or even
larger.
The paper will describe recent developments along the
INTRODUCTION
Panel Level Packaging (PLP) is one of the latest trends in
microelectronics packing. One driver of course is lowering
cost by increasing the packaging size from wafer to larger
panel formats and therewith increasing the number of
packages manufactured in parallel. Additionally, PLP has
the opportunity to adopt processes, materials and
equipment from other technology areas. Printed Circuit
Board (PCB), Liquid Crystal Display (LCD) or solar
equipment is manufactured on panel sizes and offer new
approaches also for Fan-out Panel Level Packaging
(FOPLP).
For Fan-out Wafer and Panel Level Packaging two basic
process flows are encountered: The “Mold first” and the
“RDL first” approach. For the “Mold first” process a face-
down and a face-up option exist. Both variants are already
applied in mass production. Process flows of all options are
summarized in Figure 1.
M old first RDL first
f ace-dow n f ace-up

process chain including materials for carrier selection, Apply thermal release tape on carrier Apply temporary bond layer on carrier Apply release layer on carrier

encapsulation and redistribution layer as well as the related Face-dow n die assembly on carrier Face-up die assembly on carrier RDL (e.g. thin film, PCB based, …)

process and equipment options. Especially the Die assembly on carrier

redistribution layer (RDL) application offers a variety of Wafer/ panel overmolding Wafer/ panel overmolding

technology options. In addition, main challenges as Wafer/ panel overmolding

Carrier release M old back grinding and RDL
warpage, die shift and panel handling in PLP will be
discussed. RDL (e.g. thin film, PCB based, …),
balling, singulation Carrier release, balling, singulation
However, for industrialization also the understanding of the Carrier release and singulation

cost structure and cost opportunities are important – also

referring to the different technology options. Therefore, a
highly granular cost model is introduced and application
scenarios are presented.
Key words: Panel Level Packaging, die shift, warpage,
cost modelling, cost analysis
Figure 1. Fan-out Wafer/Panel Level Packaging process
flow options.
“Mold first” face-down starts with die assembly on an
intermediate carrier followed by overmolding and
debonding of the molded wafer/panel from the carrier. The
redistribution layer (RDL), typically based on thin film
technology, is finally applied on the reconfigured molded
wafer/panel. The face-up approach also starts with die
assembly on a carrier with a temporary adhesive layer. But
here dies have a Cu-bump and are placed face-up on the
carrier. After overmolding a backgrinding step opens
access to the Cu-bumps of the dies again. The redistribution

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is applied and finally the wafer is released from the carrier
and diced for package singulation.
The “RDL first” process is comparable to an advanced flip
chip on flex assembly. Here the redistribution layer is
applied first of all on an intermediate carrier and the
bumped dies are assembled by chip to wafer bonding on the
RDL. Afterwards the assembly is underfilled and
overmolded and the molded wafer including RDL is
released from the carrier.
Besides different processing with pros and cons as e.g. cost,
yield and flexibility also the final package structures show
differences (s. Figure 2)
M old first
f ace-dow n f ace-up
EM C
EM C
Chip
Chip EM C
Cu Pillar polym er FC Bum p
RDL RDL
Figure 2. Fan-out Wafer/Panel Level Package
structures from different process flow options
“Mold first” face-down has the shortest interconnect
with a direct plated via. This may lead to best high electrical
performance at higher frequencies due to lowest loss
especially when chip to chip connection is considered.
“Mold first” face-up needs a Cu pillar in combination with
a plated via and “RDL first” even a soldered interconnect.
Additionally, the last two options also have an additional
polymer/underfill layer between die and RDL which may
influence performance and reliability.
For all the different Fan-out approaches there are
activities running worldwide on panel sizes. Several
companies including NEPES, POWERTECH, SAMSUNG
Electro-Mechanics, DECA Technologies or ASE have
already announced to work on processes ready for high
volume manufacturing [1][2][3][4].
COST MODELLING
A main motivation for PLP is to lower packaging cost. In
order to estimate cost advantages from panel level
packaging Fraunhofer IZM developed a cost modelling
approach based on the individual process steps (process
flow model) in combination with production scenarios
(business case). This bottom-up approach has been
necessary due to the lack of actual production data.
The process flow model considers in each individual
process step the particular equipment and materials that are
related to it. Partial costs are allocated to each process step
covering investment costs of equipment, R&D, clean room
and operational costs such as materials, clean room,
facility, labor, and electricity.
In a first step, a complete reference PLP process was
modeled based on available data from the technology
development phase and test trials. Data gaps were
compensated by reasonable assumptions. Furthermore, the
available equipment and process parameters determined
facility conditions such as space and cleanroom class
requirements, as well as labor and throughput time. This
allows for a very detailed cost calculation for a defined
process flow. Aiming to get more realistic cost estimates,
the next step in the cost modelling is the scaling of the
production to large scale business scenarios. In this step,
panel and package dimensions as well as cost-relevant
design aspects such as the number of dies and RDLs are
considered. Also, the production volume and geographical
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location are taken into account. This allows modeling of
realistic orders of magnitude of related cost data. The
following Figure 3 sums up the principle elements of the
cost modeling approach.
Dat a Input Dat a Input Dat a Input
package & panel design t ech & process f low business case
RDL first Dat abases Process f low m odel Cost m odel
Equipment , M at erial, Act ivit y based process logical connect ion of
Facilit y, Locat ion st ep sequence t echnical & business case
Chip
UF
Figure 3. Principle elements of the cost modeling
RDL
approach
COST ANALYSIS
The first application of the cost modelling based on a
“Mold first” reference process flow showed plausible
results. A sensitivity analyses led to improvements of the
model by adjusting the granularity on some cost items.
Moreover, the relatively high granularity of the cost model
(from a technical point of view due to the bottom-up
process flow simulation) allows a broad range of cost
analyses that can be used for the identification of cost
optimization strategies. There are a few major aspects
influencing the overall cost structure. We can generally
distinguish fixed and dynamic cost factors:
ƒ Fixed cost factors derive from the package design, the
panel size, the principle process flow (e.g. Mold first or
RDL first), and the production location.
ƒ Dynamic cost factors are related to the specific
technology, equipment, material selection, yield and
production capacity. These specific process parameters
have a strong influence on the process quality and
therefore the cost relevant yield estimate. Considerable
influences have for instance the carrier selection and the
die shift compensation.
Because of the variety of technologies, equipment and
material options the “best” and most cost-effective solution
is not easy to select – even not taken technical challenges
and possible limitations for PLP into account. However, the
cost modelling indicated that the above mentioned “fixed
cost factors” have considerable impact on the overall cost.
In this paper, we will present an example of cost analysis
and then the influence of some fixed and dynamic cost
factors.
Example of cost analysis
An aggregated example of cost modelling for a high
volume PLP production is shown on the Figure 4. In this
case, the packages are 15x20 mm² and include 6 chips (the
die cost is not included in this model). The production on
457x610 mm² panels is located in Taiwan. We assumed a
high volume PLP production, so that every 3 min a new
panel is launched into the production line (the machine park
consists of 170 machines). This leads to a total production
of 170k panels/year, i.e. 133 Mio. packages per year. The
process flow includes 3 redistribution layers (RDL) with
laser direct imaging (LDI) as lithography technology. In
total, the cost per cm² is estimated to be around $0.17. This
first model does not include yield, taxes, benefits,
automated handling or testing phases. However, this is
already a sufficient estimation to identify the relevant
parameters to compare WLP and PLP. For example, Figure
4 indicates that the material cost represents more than half
of the total annual costs. The investments into the
machinery represents only 15%.
Figure 4. Aggregated annual cost analysis for a high
volume PLP production (170K panels/year, i.e. 133
Mio. packages per year)
Influence of fixed cost factors
Since the material prices and amounts are so significant for
the global costs, the initial cost analysis shifted its focus to
the issues of identifying more optimal panel formats in
correlation to package dimensions and design, in order to
minimize materials waste.
There are no standard panel sizes until now. As an example,
Figure 5 shows an overview of typical panel sizes used in
PCB and LCD manufacturing in comparison to standard
wafer sizes, demonstrating already here the high variety.
This leaves us the possibility to choose the optimized
format that enables a minimum area loss, and thus a
minimum materials loss. In order to study the relation of
panel and package dimensions on the productivity, we
present in the following some calculations regarding
optimal panel area utilization for wafer and various panel
sizes.
Area [m m ²]
700.000
600.000
500.000
400.000
21“ x24“
300.000 21“ x21“
515x510 mm² 18“ x24“
200.000
18“ 12“ x18“
100.000
12“
8“
0 6“
Waf er PCB
Figure 5. Existing wafer and panel sizes.
Wafer and Panel Area Utilization
In order to reduce the cost per package and to minimize the
amount of materials wasted, we first developed an area
utilization model only based on geometric parameters for
panels and wafers. We can therefore calculate the ratio
between the actual area used for the packages and the
unused area (where the materials are lost). The set of
parameters, shown on the Figure 6, includes:
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ƒ The substrate dimension (panel’s height and width or
wafer diameter)
ƒ The package dimensions (square or rectangular)
ƒ The package orientation (vertically or horizontally-
oriented, which is required only for a rectangular panel,
but not for square panels or wafers)
ƒ The edge exclusion which defines the exclusion zone at
the edge of a wafer and a panel
ƒ The package-to-package distance
ƒ The space loss due to fiducials
The area utilization (AU) can then be defined by:
‫ ܽ݁ݎܽ݁݃ܽ݇ܿܽ݌‬ൈ ݊‫ݏ݁݃ܽ݇ܿܽ݌݂݋ݎܾ݁݉ݑ‬
‫ ܷܣ‬ൌ
‫ܽ݁ݎܽ݁ݐܽݎݐݏܾݑݏ‬
The Gross Die per Panel (GDP) is simply the number of
packages per row multiplied by the number of packages per
column. In the case of rectangular panels and packages, the
GDP is calculated for both orientations (long package edge
along the long panel edge or along the short panel edge),
and the retained GDP is the highest of these two options.
The Gross Die per Wafer (GDW) can be calculated
according to the model shown in [5]:
ߨ ή ሺܴ௘௙௙ െ ͲǤʹͻ ή ሺ‫ ܪ‬൅ ܹሻሻ;
 ൌ
‫ܣ‬
with Reff the effective radius (physical radius minus the
edge exclusion), H the package height, W the package
width and A the package area.
GEN4
GEN3
GEN2
GEN1
Figure 6. Area utilization model on panel and on wafer
LCD By varying both package height and width from 1 to 50 mm
with a step of 1mm, the AU was calculated on different
panel sizes and on a 300mm wafer. Figure 7 shows the
number of package dimension combinations that allows
certain area utilization thresholds (≥95%, ≥90% or ≥85%).
In this case, the fixed parameters are 3 mm edge exclusion,
110 µm package-to-package distance and 4 packages lost
due to fiducials for both wafer and panel. The wafer does
not enable an AU superior to 90%, the highest AU is only
88%. The biggest square package allowing a high AU on
wafer (≥85%) is 11x11 mm². For bigger packages, the AU
drops up to 45%. On the contrary, panels lead to a very high
area utilization: AU≥95% becomes possible without
package size limitation. We can also notice that rectangular
panels are better suited than square ones since the package
formats are often rectangular and the orientation can be
adapted to reach the most effective layout. The rectangular
panels 457x610, 650x550 and 650x750 mm² show a
superior area utilization for the majority of package
dimensions.
Influence of dynamic cost factors
Concerning the impact of “dynamic cost factors” on global
costs, we present two examples: the number of chips per
package and yield.
On the Figure 8 the impact of chips number per package on
cost per area is described as function of the package size.
The significant cost increase for smaller packages and
thereby with higher number of dies per wafer/panel is
predominantly caused by the assembly efforts (assembly
duration and machinery associated). This increase can be
lowered by implementation of assembly equipment with
higher UPH (units per hour).
3,0

2,5

relative cost per area

2,0

1,5

1,0

0,5

Figure 7: Number of package dimension combination 0,0

2 3 4 5 6 7 8 9 10 11 12 13 14 15
allowing high area utilization on wafer and panels (for edge length (quadratic package size) [mm]

different panel sizes) 610x457 mm² - 1 Chip 610x457 mm² - 3 Chips 457x305 mm² - 1 Chip
457x305 mm² - 3 Chips 300 mm Wafer - 1 Chip 300 mm Wafer - 3 Chips

Table 1Error! Reference source not found. translates this
area utilization (AU) in amount of epoxy molding
compound (EMC) lost for different package sizes during
the production of 15 million packages (selected business
scenario). The number of packages on wafer and panels
were calculated according to the method above mentioned.
Assuming that around 100 g of EMC are required for a
300 µm layer on a 457x610 mm² panel, the amount of
EMC lost for the whole production is calculated. The loss
represents more than 2 tons for a 30x30 mm² package on
wafer. This loss can be decreased by around 77% by PLP.
The best area utilization on panel is achieved with
20x16 mm² packages, and the amount of EMC loss is on
panel minimized by 83%. EMC is only one example (one
of the most expensive material used in FOPLP), but a low
utilization rate generates material waste at every step.
In conclusion, PLP represents a considerable opportunity
to reduce material waste and substantially supports a more
cost-effective production by higher area utilization.
Figure 8: Cost comparison of 300 mm wafer to 457x305
mm² and 457x610 mm² panel sizes for packages with 1
and 3 chips
About the impact of yield on costs, since the PLP processes
are still under development, it is highly difficult to estimate
a yield for a panel production. However, assuming a 100%
yield for a wafer production, we can calculate the minimum
yield that a panel production must achieve to reach still a
lower price than on wafer. Table 2 indicates that lower
yields are possible on panel than on wafer without leading
to higher costs. The cheaper the chip is, the lower the yield
on panel is required to compete with wafer. With bigger
packages, the number of packages/substrate decreases
which also reduces the yield potential on panel. To sum up,
even if the yield on panel is lower than on wafer, depending
on the package size and the die cost, the price per package
might still be more competitive on panel than on wafer due
to its high throughput.

Table 1. Impact of low area utilization on epoxy Table 2. Yield influence on cost calculation for panel
molding compound (EMC) waste for a production of 15 level packaging
Mio. packages

TECHNOLOGY STATUS & CHALLENGES PLP

There are some key challenges for FOPLP which have to
be taken into account when scaling technology from wafer
to panel level and discussing material and equipment
options. However, these challenges are not new and have
also to be solved on wafer sizes but getting more severe
when moving to larger panels [6].

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 Wit hout com pensat ion
200 200 200

150 150 150

100 100 100

[mm]

y-axis assembled [mm]

y-axis assembled [mm]

y-axis assembled [mm]

50 50 50 0.3000

0 0 0
0.2600
-50 -50 -50

-100 -100 -100 0.2200

-150 -150 -150

0.1800
-200 -200 -200

-250 -200 -150 -100 -50 0 50 100 150 200 250 -250 -200 -150 -100 -50 0 50 100 150 200 250 -250 -200 -150 -100 -50 0 50 100 150 200 250
0.1400
x-axis assembled [mm] x-axis assembled [mm] x-axis assembled [mm]

Wit h com pensat ion 0.1000

200 200 200
0.06000
150 150 150

100 100 100

0.02000
y-axis target [mm]
y-axis target [mm]

y-axis target [mm]

50 50 50

-0.02000
0 0 0

-50 -50 -50

-0.06000
-100 -100 -100

-150 -150 -150 -0.1000

-200 -200 -200

-250 -200 -150 -100 -50 0 50 100 150 200 250 -250 -200 -150 -100 -50 0 50 100 150 200 250 -250 -200 -150 -100 -50 0 50 100 150 200 250
x-axis target [mm] x-axis target [mm] x-axis target [mm]

Figure 9. Die shift comparison for different reconfigured wafer and panel sizes

The next paragraphs will focus on a “Mold first” face down When moving from wafer to larger panel sizes the effects
approach. But most of the challenges described may be also do not change but the elongations get significantly larger
a topic for “Mold first” face up or “RDL first”. with the different process steps and the system becomes
more sensitive to material inhomogeneities or temperature-
Die Shift time deviations during processing. Well matched materials,
Die shift describes the effect of chip movement after highly accurate equipment and well controlled processes
placement during compression molding, debonding and are needed to handle die shift and the overall tolerance
cooling of the reconfigured panel. Dies are placed at room chain.
temperature on the carrier with attached thermal release A die shift example for a reconfigured 200 mm wafer and
tape (TRT). The carrier is then heated up to mold 457x305 mm² and 610x457 mm² with the same layout is
temperature. Here the assembly expands mainly with the shown in Figure 9. Die shift evaluation is given with and
CTE of the carrier material. During molding and therewith without die shift compensation. All formats show a linear
curing of the epoxy molding compound (EMC) the dies are shift behavior with comparable die shift factors. This
fixed in the EMC. During cross linking of the EMC the allows a compensation with a good die position accuracy
material shrinks, leading to a change in volume of the after molding. But it is also visible that a shifting up to
molded panel. After debonding the reconfigured panel is 300 µm occurs without compensation at the panel edges
cooled down dominated by the CTE of the EMC. Due to which can be not neglected and must be corrected.
the different CTEs of the materials involved in combination However, with decreasing die pad sizes, pitch and number
with the temperature profile of the different process steps of IOs this is still a challenge as this demands even higher
dies will shift from their originally assembled position. In chip placement accuracy after molding.
addition to the described effect, also a sliding of the dies An option to overcome the die shift and high accuracy die
during molding can occur depending on size and adhesion placement problem is the approach of maskless processing.
of the dies on the release tape and the flow behavior of the LDI (Laser Direct Imaging) is often used for the fabrication
EMC and the related forces on the dies during compression of organic substrates and hence ready for large panel
molding. processing. Key advantage is that no masks are involved in
The final die position in the reconfigured panel is a key the process. The design data is directly concerted to the
factor for the overall process reliability and resulting yield. writing head of LDI. This opens the possibility to an
With the redistribution layer (RDL) dies are electrically adaptive lithography mode which has been already
connected. Here the µvias of the first dielectric layer have published in 1986 [7][5]. Here a fast AOI (automated
to meet the die pads. Has the die shifted compared to the optical inspection) in combination with the maskless
designed or defined place, the µvia will not or only partially processing is used for die connection and rewiring. This
fit on the die pad. gives the opportunity to tolerate larger die misplacement by
The linear die shift can be compensated with an assembly adapting the layout to the real die positions. Therefore, the
adaptation. Dies are assembled at the “wrong” place and layouts for LDI processing can be automatically adapted
shift to the “correct” position during molding. However, according to measured die positions. Although these
the general placement tolerance of the assembly equipment process steps are maskless they can be highly productive.
and a random shift during molding cannot be compensated State of the art LDI equipment will take about 1 min for a
with that method. Here half the difference between pad and 457x305 mm² panel.
µvia size defines the acceptable tolerances.

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 Ø200 m m 305 x 457 m m ²
-50 0 50 mm
-80
-60
-40
-20
0
20
40
60
80
mm
Figure 10. Warpage comparison for different reconfigured wafer and panel sizes without RDL
Warpage
Warpage is also mainly based on the CTE differences of
the carrier, EMC and the embedded die and the chemical
shrinkage of epoxy mold as described above for the die
shift. Besides the material properties for warpage also the
geometries have a significant influence. This includes
carrier thickness, mold thickness, die thickness and overall
silicon content but also the lateral panel dimensions. Which
means with larger panel sizes also the warpage will
increase. As with larger panel sizes also the panel weight
increases, gravity will have an influence on warpage. In
Figure 10 an example for warpage of 457x305 mm² and
610x457 mm² reconfigured panels and a 200 mm wafer
after debonding is given. All examples are fully
comparable concerning layout, materials and process. Only
the processing area is different. For this constellation, the
resulting tunnel shape is comparable for them and the
warpage is in the same range. However, in detail the wafer
shows a slightly higher maximum value than the panels and
here explicitly for the larger panel which indicates that
gravity reduces in this case the warpage of the panel.
During material selection and process optimization the goal
is not to reduce the warpage to be close to zero but to
control the warpage during the entire process flow
including redistribution layer (RDL) application and
balling in an acceptable range. This would allow reliable
handling and controlled stress for the assemblies.
Handling
Fan-out Wafer Level Packaging (WLP) based on Fan-In
WLP infrastructure with established high-volume
manufacturing and handling equipment. Here only
adaptation for handling molded wafer as e.g. the
acceptance of wafers with higher warpage was needed.
When moving to panel sizes, this infrastructure is still
missing especially for handling molded panels. Automatic
handling of PCBs and LCDs exists but will possibly need
larger modifications. Compared to PCBs or glass, molded
panels are more brittle, self-bending and warped or bended.
Many process steps especially during RDL application as
e.g. sputtering or plating require a clamping or at least a
fixation of the panel. This is extremely challenging as
mechanical fixation of the warped panel at the edges easily
leads to cracking and breaking of the panel.
When moving to thinner panels in the range below 400 µm
a support might be required during RDL processing to
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457 x 610 m m ²
mm
6
-300 -200 -100 0 100 200 300 mm
5.5
-200
5
-150
4.5
-100 4
-50 3.5
0 3
50 2.5
100 2
150 1.5
1
200
0.5
mm 0
NM
flatten and stiffen the mold panel. Suitable technologies
have to be developed, either adapted from temporary wafer
handling or new concepts as e.g. frame handling have to be
evaluated.
Redistribution Layer
Compared to Fan-in processing Fan-out RDL application is
a big challenge. A silicon wafer is nearly flat, has accurate
die positions structured by front-end processes, consist of
well-known materials and is described by defined
standards. In contrast reconfigured wafers or panels are
warped, bended and or twisted, have inaccurate die
placement and die shifting due CTE mismatch, EMC
shrinkage, mold flow and show a surface topography and
temperature limitation. In addition all these properties and
geometries change with time, temperature and humidity as
polymers do age.
For redistribution layer manufacturing on reconfigured
panels a wide variety of different dielectric materials and
lithography options exists, bringing different approaches
from wafer level processing and PCB as well as LCD
manufacturing together. This offers on the one hand a lot
of opportunities also in lowering cost but on the other hand
there is the challenge to find the best suited overall process
solution.
Related to the trend to larger panel sizes the use of liquid
photo-patternable dielectric polymer materials becomes
less attractive regarding the material consuming spin
coating process. Dry film dielectric materials are more cost
effective as they imply less material waste and the lack of
baking processes to evaporate inherent solvent which is
necessary for liquid materials. The well-developed PCB
lamination equipment could be used for the lamination of
the dielectric on large panels. The dry film could be applied
by a hot roll process at atmosphere or by a vacuum
laminator. Vacuum lamination is here especially useful for
substrates with higher topography. However, also liquid
dielectric application for large panels as slit coating or even
spin coating from LCD and solar panel manufacturing are
available on the market.
The most common exposure tools for wafer bumping/wafer
level packaging are mask aligners and 1X steppers (as
opposed to reduction steppers that are used in the front
end). 1X steppers are projection systems that image a 1:1
projection of the reticle onto the wafer. Steppers expose the
wafer with multiple shots. Maximum field size is about
20x40 mm². Therefore, multiple shots are necessary to [8] K. Best, G. Singh, R. McCleary; Advanced Packaging Lithography
and Inspection solutions for next generation FOWLP-FOPLP
expose the complete area. Mask-based stepper technology processing; Proc. of ICEPT 2016, Wuhan, China.
is available from LCD manufacturing for large panels and [9] M. Arendt; High throughput UV Projection Scanner with optimized
fine structuring down to 2 µm lines and spaces and below performance for FOWLP Applications; Advanced Packaging
[8]. Full-field projection scanner patterning is also Forum, Semicon Taiwan 2017, Taipeh, Taiwan.
adaptable to large panel formats [9]. Excimer laser ablation [10] H. Hichri, S. Fujishima, S. Lee, M. Arendt, S. Nakamura; Fine Line
is another option for fine line structuring which can be also Routing and Micro via Patterning in ABF Enabled by Excimer Laser
Ablation; Proc. of IMAPS 2017, Raleigh, NC, USA;
used in combination with non-photosensitive dielectric https://doi.org/10.4071/isom-2017-TP44_011 of IMAPS 2017.
materials [10].
However, the challenge for all mask-based lithography
approaches lies in the capability to handle warped and bent
reconfigured panels in combination with inaccurate die
positions. LDI (Laser Direct Imaging) as described above
is another lithography option also to overcome the die shift
challenge with an adaptive patterning.

SUMMARY & OUTLOOK

Fan-out Wafer Level Packaging is one of the latest
trends in microelectronics packaging. Besides the
developments towards higher integration larger rectangular
formats are considered for lowering packaging cost.
However, when moving to Panel Level Packaging some
technical challenges have to be solved. This includes topics
like die shift, warpage, handling of large and fragile panels
or the missing panel size standardization. A simple
upscaling of existing FOWLP technology is not feasible.
But PLP offers also new technical opportunities for fan-out
packaging by using equipment and materials from other
branches as PCB, LCD or Solar. This may even influence
the Wafer Level Packaging industry.
PLP also offer significant cost advantages by parallelizing
process steps, higher area utilization of packages on
rectangular panel formats than on round wafer shapes and
lower material waste. The introduced comprehensive cost
model can help to analyze and therewith optimize
packaging cost with view to geometry optimization,
material and equipment selection as well as process
management. Combining cost modelling with a design and
process selection tool could also support the development
of tailor-made application and package cost effective
solutions.

REFERENCES
[1] J. Azémar; Fan-Out Packaging - Wafer and panel technologies and
market trends; Panel Level Packaging Symposium, 29.11.2017,
Berlin, Germany.
[2] J. H. Kim, Y.-M. Park, Y. T. Kwon, JK Lee, S. H. Lee; Fan-out WLP
technology as Sensor Packaging Solution; Proc. of IWLPC 2017;
San Jose, California, USA.
[3] D. Fann, D. Fang, J. Chiang, K. Huang; Fine Line Fan-out Package
on Panel Level; Proc. of ICEP 2017, Yamagata, Japan.
[4] T. Olson; Transforming Electronic Interconnect - Breaking through
historical boundaries; SiP Embedded Forum, Semicon Taiwan 2017,
Taipeh, Taiwan.
[5] D.K. de Vries; Investigation of gross die per wafer formulas; IEEE
Transactions on Semiconductor Manufacturing ( Volume: 18, Issue:
1, Feb. 2005.
[6] T. Braun; K.-F. Becker ; O. Hoelck; R. Kahle; M. Wöhrmann; L.
Boettcher; M. Töpper; L. Stobbe; H. Zedel; R. Aschenbrenner; S.
Voges; M. Schneider-Ramelow; K.-D. Lang; Panel Level Packaging
- A View Along the Process Chain; 2018 IEEE 68th Electronic
Components and Technology Conference (ECTC); San Diego, Ca.,
USA.
[7] C. Eichelberger, R. Wojnarowski, W. Kenneth “Adaptive
lithography system to provide high density interconnect”,
US4835704A.

Proceedings of the International Wafer-Level Packaging Conference 2018

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