REPRINT

BIT RATE GENERATOR AND

RAW DATA CONDITIONER

September 1961
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 SCR-440
.INSTRUMENTS
TID-4500 (16th E d . )

SANDIA CORPORATION R E P R I N T

B I T R A T E G E N E R A T O R AND
RAW DATA CONDITIONER

by

S. C. S t e e l y

S e p t e m b e r 196 1
 SUMMARY

A p h a s e lock loop s y s t e m , which d e r i v e s r e l i a b l e phase and frequency information under

a d v e r s e signal- to-noise conditions, is employed in c o l o r television, t e l e m e t r y r e c e i v e r s , and
d i s c r i m i n a t o r s . 'l'his type of c i r c u i t h a s been utilized t o d e r i v e bil r a l e lrequency and phase
f r o m a nonreturn to z e r o PCM signal under a d v e r s e signal-to-noise r a t i o s .

This information is derived by having a p h a s e lock loop lucked to the bit r a t e . . This
"a p r i o r i " knowledge of t i m e and phase of possible bit change is utilized by sampling p u l s e s
which o c c u r in each bit interval. By using a p p r o p r i a t e pulse width and pulse delay c i r c u i t s , the
timing and width of the sampling p u l s e s c a n be optimized f o r low signal-to-noise r a t i o s .

This p a p e r p r e s e n t s a qualitative description of the bit r a t e g e n e r a t o r and raw data condi-

tioner. A comparison is m a d e between t h e operation of this phase lock loop and the g e n e r a l
operation of a conventional phase lock loop. Included in the paper is a description of the t e s t -
ing technique and possible s o u r c e s of e r r o r .
 TABLE O F CONTENTS

Page

SUMMARY 2

Description

Low P a s s F i l t e r
Limiting
~ r o s s o t r e ; Detector
P h a s e Lock Loop
Sampling

Comparison of this P h a s e Lock with a conventional P h a s e Lock Loop

Evaluation of Bit Rate.Generator and Raw Data Conditioner

REFERENCES

LIST O F ILLUSTRATIONS

Figure Page
-
1 -- Bit r a t e generator and raw data conditioner 5

2 - - Two-section low p a s s filter 6

3 - - ~ k a averaging
k circuit 7

4 - - P h a s e lock loop 7'

5 -- Sampling gate 8

6 -- Gated phase detector output 9

'I -- P h a s e lock loop f i l t e r proportional plus integral c u r ~ l r u l11e1wul.k 10

8 -- T e s t setup f o r evaluation bit r a t e generator and raw data conditioner 11

9 - - Graphical analysis of noise 12

10 -- Signal-to-noise v e r s u s percentage e r r o r with alternating z e r o s and' ones 12

f o r information
 BIT RATE GENERATOR AND
RAW DATA CONDITIONER

Description

The bit r a t e generator and raw data conditioner (Fig. 1) consists of a low p a s s filter, l i m i t e r s ,
a c r o s s o v e r detector, a phase lock loop, pulse shaping circuits, a sampling gate, and an integrator
Schmitt t r i g g e r combination. The low p a s s f i l t e r r e j e c t s noise components above the information
band width. L i m i t e r s a r e used to give steep slopes to the input nonreturn-to-zero information signal.
The c r o s s o v e r detector furnishes a pulse input to the phase lock loop f o r each positive and negative
slope of the nonreturn-to-zero information. The phase lock loop derives the bit r a t e of the input in-
formation. P u l s e shaping circuits give p r o p e r width and delay to sampling pulses applied to the
sampling gate. The sampling gate s a m p l e s the input nonreturn-to-zero information during each bit
interval to determine if a one o r z e r o is present. A final determination a s to whether the sampling
gate saw ones o r z e r o s is made by the integrator Schmitt t r i g g e r combination.

INFORMATION
INTE -
GRATOR TRIGGER

INFO I
IN ' r
PULSE
t
PULSE
LOW
-+ PASS
FIRST
LIMITER
SECOND
LIMITER ' THIRD
LIMITER
SAMPLING WIDTH +DELAY +
FILTER
4
ONE SHOT ONE SHOT
-
6 -b
EMITTER LOOP
vco
AVERAGING . FOLLOWER VER
DETECTOR
HASE
DETECTOR
FILTER -b FLU'
FLOPS -
t
E T E
OUT
j

Fig. 1 - - Bit r a t e generator and raw data conditioner

Low Pass F i l t e r

The purpose of the lm p a s s f i l t e r on the input of the bit r a t e generator and raw data conditioner
is to f i l t e r out a s much of the noise component f r o m the information a s possible. T o accomplish this
filtering, a two-section low p a s s f i l t e r (Fig. 2) was designed. The f i l t e r h a s a 2 db insertion l o s s
with the fundamental of the bit r a t e (10 cycles), one db down from the flat portion of the curve. At
20 cycles the curve is 9 db down, and a t 30 cycles it is down by 2 2 db.

., '
 Fig. 2 - - Two-section low p a s s f i l t e r

Limiting in the bit r a t e generator and raw data conditioner is accomplished about the algebraic
mean of the positive and negative peaks of the nonreturn-to-zero input. This type of limiting is quite
essential because the phase lock loop utilizes the positive and negativc olopcj (hei-einalter called Lhe
c r o s s o v e r s ) f o r i t s input information, requiring that the z e r o s and ones have equal time durn.tinn.

Limiting about the algebraic mean of the peaks is accomplished by the u s e of a. peak averaging
circuit (Fig. 3) which consists of a positive peak detector and a negative peak detector. These peak
detectors consist of a diode and a n RC network. The diodes rectify the incoming signals, and the
direction of the diodes in the circuit determines whether the detector is a positive o r nega.tive peak
deteclor. The capacitors in the peak detectors have a rclatively short tiliie cunsta.nt for charging t o
the peaks and a long time constant f o r discharging, approximately 0.02 second f o r charge and seven
seconds f o r discharge. T h e output of the two peak detectors a r e added a c r o s s a r e s i s t i v e summing
network, essentially giving the algebraic mean of these two outputs.

The output of the peak averaging circuit is utilized to. hias t h e f i r s t limiter, thus dotormining
the level a t which limiting occurs even though the bias of .the discriminator may drift.

C r o s s o v e r Detector

The c r o s s o v e r detector detects a l l positive and negative slopes of the limitcd input and gives a
gating pulse output f o r each slope. This detection is accomplished by using differentiating circuits
to detect the slopes and a one shot multivibrator t o furnish the gating pulse output. The output of the
c r o s s o v e r detector is then used a s a gating pulse f o r the phase detector.

P h a s e Lock LOOD

The phase lock loop (Fig. 4) is a n electronic servomechanism, consisting of a gated phase.
detector, a filter, and a'voltage controlled oscillator (VCO). In the gated phase detector the phase
 250 fl 1OOK

e.
I e
0

250 Cl
B. 10OiK
1C

Fig. 3 -- P e a k averaging circuit

GATED SIX
----bPHASE
DETECTOR
LOOP
FILTER b VCO ----, FLIP
FLOPS
-
r

. Fig. 4 -- p h a s e lock loop

of the r e f e r e n c e signal from the VCO is compared with the phase of the signal from the c r o s s o v e r
detector and gives an output proportional to the phase difference.of the two signals. The loop f i l t e r
is' essentially an integrating network, controlling the frequency of the voltage controlled oscillator
in o r d e r to keep the reference signal in synchronism with the input information signal.

The loop provides memory by virtue of voltage stored on the capacitor in the loop filter. This
voltage r e p r e s e n t s a "best guess" of the present bit r a t e and is retained f o r s o m e time even without
the presence of any new c r o s s o v e r s on the input.

A transistorized 1.3 kc standard telemetry s u b c a r r i e r VCO is used chiefly because of .its

stable frequency c h a r a c t e r i s t i c s and high inpu impedance. The VCO is biased to operate a t 1280
te
cycl.es p e r second, necessitating division by 2 'to a r r i v e a t the proper bit reference-of 20 bits, p e r
second. To accomplish the division, s i x flip-flops a r e used, thus giving 20 cps a s a reference f r e - .
quency to compare with the c r o s s o v e r s of the 20 bit p e r second information in the phase detector.
The 20 cps reference frequency is a l s o used a s a bit r a t e out~jutto furnish reliable bit r a t e informa-
tion f o r decoding purposes.

Sampling

The information signal is sampled a t the sampling gate (Fig; 5) by comparing the input'infoi-ma-
.tion. ( e l) with sampling pulses during each bit interval. The sampling pulses (e2) a r e developed by
'using a pulse delay and pulse .width circuit to shape and space the bit r e f e r e n c e from the phase lock
loop.
 Fig. 5 -- Sampling gate

The sampling gate is an AND gate that must have positive inputs ( e l and p 2 ) i n o r d e r t o give a
positive output (eg). Experimental r e s u l t s proved that under noise the best a n s w e r s were given when
the sampling pulses were approximately one-third the width of a bit interval. The final decision made
is whether a one o r z e r o was present during each bit interval.

During t e s t s run on the bit r a t e generator and raw data conditioner, it wa.s nnticed that errors
made under heavy noise by the previously mentioned sampling p r o c e s s were caused partially by ran-
dom noise pulses in the input nonreturn-to-zero information signal. Ta reduce this type nf e r r o r a n
integrating network and Schmitt trigger were added. . These were adjusted s o that the output of the
sampling gate had to be above an optimum amplitude and/or 'duration before i t would trigger the
Schmitt trigger.

Comparison of this P h a s e Lock Loop with a

Conventional P h a s e Lock Loop

In a conventional phase lock loop, a continuous comparison of input signal with reference signal
is being made. This continuous comparison is not possible in the bit r a t e generator and raw data
conditioner because the only input information supplied this phase lock loop is the c r o s s o v e r s of non-
return-to-zero information. Depending upon the type of information being transmitted, t h e r e a r e
possibilities of quite a few s t r i n g s of ones o r zeros. Uuring this time t h e r e is no information being
supplied to the phase lock loop, and i t n'iust be capable of remembering the bit r a t e frequency f o r
that interval. The phase lock loop must a l s o have a capability of fairly rapid correction of phase
when the c r o s s o v e r s a r e present.

The long memory and rapid correction requirements a r e met by the u s e of a gated phase detec-
tor. The correcting voltage is applied to the integrating low p a s s f i l t e r only when c r o s s o v e r s a r e
available on the input.
 The gated phase detector consists of two AND gates. The c r o s s o v e r s t r i g g e r both of the AND
gates. One of the AND gates gives a positive correction, and the other gives a negative correction.
When these two outputs a r e summed together a net output is given (Fig. 6).

REF
INPUT TO
PHASE
DETECTOR - - -
CROSSOVER
INPUT - A

OUTPUT
NO CORRECTION
VOLTAGE APPLIED

REFERENCE
INPUT '

CROSSOVER
-
INPUT

OUTPUT

NET P O S I T ~ ~ E

C
k -1
REFERENCE
INPUT

-
,

-
I

-
I

CROSSOVER.
INPUT '. i

OUTPUT
NET NEGATIVE
COR.RECTION APPLIED*

Fig. 6 -- Gated phase detector output

The integrated value of the output of the phase detector is the control voltage applied to the
VCO. The control voltage is therefore proportional t o the phase difference between the bit r a t e and
the r e f e r e n c e frequency. The design of a phase lock loop f i l t e r in a conventional phase lock loop
using a proportional plus integral control network2 (Fig. 7) concerns calculations involving W N , the
resonance frequency of the system i n the absence of any damping; 6 , the r a t i o of actual t o critical
da~fipiilg;aull R, the loop gain constant. According to Gruen,' the'equations f o r the t i m e constants
in the f i l t e r a r e a s follows:
 Big. 7 -- P h a s e lock loop filter proportional plus
int~grnlrnntrnl n e t w n r k -. . -.

Note that both t i m e constants a r e a function of the gain constant K. Gruen4 a l s o s t a t e s that the gain
constant is directly proportional to the output of the phase detector. In the bit r a t e generator and
the raw data conditioner, the loop gain constant is a , v a r i a b l e due t o the fact that the c r o s s o v e r input
f r o m the phase detector is not periodic o r continuous but usually is quite random.

Also complicating the design of this phase lock loop f i l t e r is the fact that corrections into the
loop f i l t e r a r e being gated, and thus the phase detector i s , a n open circuit when c r o s s o v e r s a r e not
present.

Basically, the loop f i l t e r s e r v e s a s a proportional plus integral control network during the
t i m e that the phase detector is gated by the c r o s s o v e r s and is a storage network between the c r o s s -
overs. The capacitor in the loop f i l t e r h a s to be l a r g e enough to hold the VCO a t the desired f r e -
quency f o r the maximum interval of all ones o r zeros. R I and Rz have practically no effect during
the storage t i m e and thus affect only T, and T2 during the gating of the phase detector.

In this section.of the paper t h e r e h a s been no attempt to present a n anaiytic diSCUSSlOn Of the
phase lock loops. F u r t h e r information will be found in a r t i c l e s by C. E. ~ i l c h r i e s t ,W.
~ J. G r ~ e n , ~
and D. ~ i c h m a n . 5

Evaluation of Bit Rate Generator and

Raw Data Conditioner

The bit r a t e generator and raw data conditioner was evaluated by measuring the signal to noise
r a t i o s of the input signal and then comparing these ratios with the percentage of e r r o r s on the output.

The test setup (Fig. 8 ) required 5 3.9 kc VCO which was modulated with an information signal.
A noise. signal was added to the output of the VCO. The 3.9 kc VCO was chosen because i t s frequency
l i e s in a region where the available noise generator h a s a flat white noise output. A 10-cps sine wave
was used f o r the information because the available t r u e HMS m e t e r s were only reliable above 5 cps.
If a random input signal had been used, a considerable part of the information RMS voltage would have
been present in the 0.5 cps portion of the frequency spectrum.

The sum of the VCO output and noise was then used a s an input t 0 . a phase lock loop discrimina-
t o r which demodulates.this sum and gives the information plus noise a s an output. According to
i lack' the output of the discriminator presents a triangular noise spectrum.
.
!N -
INFORMATION VCO
3 . 0 KC
PHASE LOCK
LOOP
DISCRIMINA-
TOR
.C
BIT RATE
GENERATOR
- )AND
*
RAW DATA
CONDITIONER

Fig. 8 -- T e s t setup f o r evaluating bit r a t e generator

and r a w data conditioner

All of the signal to noise m e a s u r e m e n t s were taken with th'e aid of an active f i l t e r on the output
of the discriminator. The 3 db.point of this'filter.was a t 10; 5 cps, and the s k i r t of the f i l t e r had a
55 db p e r decade rolloff above 10 cps. This f i l t e r was used to r e s t r i c t the noise that was present to
the band of the information channel which is considered to b e f r o m 0 to 10 cps.

The signal to noise m e a s u r e m e n t s a r e in e r r o r f o r t h r e e reasons. One r e a s o n is that a por-

tion of the RMS noise voltage used i n t h e signal to noise calculations was due to components of noise
above the 0 to 10 cps information band. Also, the noise between 7 and 10 cps was attenuated by the
active low p a s s filter, thus giving a n inaccurate reading of the noise in this region. Another r e a s o n
f o r e r r o r is that the 10 c p s information signal was a l s o attenuated by the active low p a s s f i l t e r by
2.4 db. Another consideration might have been the RMS m e t e r response below 5 cps; however, the
3-db point of the RMS m e t e r is a t 2. 5 cps, thus giving a s m a l l total e r r o r due t o s m a l l noise ampli-
tudes out of the discriminator from 0-2. 5 cps.

A graphical analysis was made of the noise voltage and noise power spectrum t o determine the
e r r o r in the signal to noise measurements. The measured noise voltage was obtained by assuming
a triangular noise voltage spectrum out of the discriminator. Using this triangular noise voltage a s
an input, the output of the active low p a s s f i l t e r was determined (Fig. 9). The noise power spectrum
a t the RMS m e t e r was obtained by squaring the points on the noise voltage graph. T h e noise power
spectrum from 0 to 10 c p s at the input of the bit r a t e generator and raw data conditioner was obtained
by squaring the triangular noise voltage spectrum. The r a t i o of the a r e a s of these two power spec-
t r u m curves gives an e r r o r of measurement of 3.1 db. Adding the 3.1-db correction f o r noise to the
signal-to-noise measurements would b c cquivalent to using o l ~ l ythe noise present f r o m O to 10 cps.
By adding both the 3. 1-db correction f o r noise and the 2.4-db correction f o r signal, a total c o r r e c -
tion of 5. 5 db was obtained.

The r e s u l t s of these corrected m e a s u r e m e n t s (Fig. 10) showed that with a signal-to-noise r a t i o

of 15 db o r g r e a t e r t h e r e were practically no e r r o r s . A 1-percent e r r o r r a t e o c c u r r e d a t approxi-
mat.ely 12.5 db signal-to-noise ratio. A 10-percent error r a t e o c c u r r e d with a signal-to-noise r a t i o
of 7 db.
 5 0- - 100
45' - 90

40- /NOISE POWER SPECTRUM ON INPUT - 80

OF BIT RATE GENERATOR AND RAW DATA
CONDITIONER UP TO 10 CPS
35 - - 70

30-
SPECTRUM AT
- 50

VOLTAGESPECTRUM
- 30

- 20

- 10
SPECTRUM
0 5 10 15 . 20 25 30 35
FREQUENCY (CPS)
. . . .. .
' Ftg. 9 -- Graphical'arialysis 'bf noise

Fig. 1,O -- Signal-to-noise versus percentage error \with

alternating zeros and ones for information
 REFERENCES

[ I ] Black, H. S., Modulation Theory, D. Van Nostrand Company, Inc., Ne)u York, N, Y.,
F e b r u a r y 1960,-pp. 223-224.

,
[21 Brown, G. S t , and Campb,ell, Dt P, Princip1,e.s gf .Servome,qhani.sms, - J ~ h nWi1,ey and S ~ n , s
Publishing Co,. , ,ly.ew.Yol?k, N, Y., 1 9 4 8 , ' ~ ~129.51.211;---'----u
;- - -- '
--,-

[3] GiJchri~st, @, E. , '!Appllcati,on of the .Phase-Locked ,Lapp f.0 Tel,em,et_1:;ya s a Dis,crjmin,atoy? ,oy
Tracking ' i l t e r , ' ' ' l ~ ~ Tr.ansacti0n.s on Telsmetry and R , e m ~ t eC,ontr,ol, J u n e 1258, pp, 2$-33,
, .- - - - .- - -. - . . ..- . -. .. .,

[4.] Grusn,W. ,a,, -.The,ory

11
.of AFC Sync?xgnSzat.ion," Bp,oce~e,di.ngs
--.. ..
of thg
...
I.R E , August 1953,
,
pp. 1043- 10.48,
&

[5] Richman, D., "Color-Carrier Reference P h a s e Synchron~zationAccuracy in NTSC Color T e l e

vision," Proceedings of the IRE, January 1954, pp, 106- 133.
-
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