A Single-Source Switched-Capacitor Based 13-Level Sextuple Boost Inverter With Reduced Component Count and Low THD

Received: 9 August 2022 Revised: 26 February 2023 Accepted: 27 March 2023 IET Generation, Transmission & Distribution
DOI: 10.1049/gtd2.12840
ORIGINAL RESEARCH
A single-source switched-capacitor based 13-level sextuple boost

inverter with reduced component count and low THD
Md Reyaz Hussan1 Adil Sarwar1 Mohammad Tayyab1,2 Mohd Tariq1,3

Farhad Ilahi Bakhsh4 Akbar Ahmad5
1
Department of Electrical Engineering, Z. H. Abstract
College of Engineering and Technology, Aligarh
A switched-capacitor-based 13-level inverter with a lesser number of components is pre-
Muslim University, Aligarh, Uttar Pradesh, India
2
sented in this article. The 13-level single-phase AC output voltage is achieved with a voltage
Department of Electrical Engineering, Integral
University, Lucknow, Uttar Pradesh, India
gain of 6 by including a single DC source, 11 switches, 4 capacitors, and 3 diodes in the pro-
3
posed converter. The self-voltage balancing is achieved for various types of load without
Department of Electrical and Computer
Engineering, Florida International University, the need for complex control schemes and auxiliary circuits. The proposed topology does
Miami, Florida, USA not require a back-end H-bridge to generate negative polarity. This leads to a reduction
4
Department of Electrical Engineering, NIT in voltage stresses across the switches. Thus, total standing voltage (TSV) and the overall
Srinagar, Srinagar, Jammu and Kashmir, India cost of the proposed topology are reduced as compared to the state-of-the-art topologies
5
Faculty of Science and Information Technology, reported in the literature. Furthermore, an Improved Nearest Level Modulation (INLM)
Mianz International College, Male, Maldives scheme is used to improve the power quality of the output voltage. Using the proposed
scheme, the Total Harmonic Distortion (THD) of the output voltage is reduced to 5.08%.
Correspondence
The power loss analysis for various elements of the proposed converter is also included. A
Akbar Ahmad, Mianz International College, Faculty
of Science and Information Technology, Male, comparison with recent topologies in reference to various performance parameters is car-
Maldives. ried out. In addition to the simulation study, a laboratory prototype is prepared to validate
Email: akbar@micollege.edu.mv
the efficacy of the proposed converter.
1 INTRODUCTION voltage increases, these traditional MLIs suffer from a number

of drawbacks, including the requirement for more components,
Multilevel Inverters (MLIs) for power conversion in renewable such as clamping diodes in diode clamped MLIs, flying capaci-
energy generating systems (REGS) such as photovoltaic (PV), tors in FC-MLIs, and additional DC sources in CHB-MLIs [8].
fuel cells, and wind turbines have gained significant appeal [1]. Also, diode clamped and FC-MLIs need complicated control
Improved power quality, high efficiency, higher operating volt- algorithms to balance capacitor voltage, and traditional MLIs
age, low dv/dt, reduced switch stress, and improved harmonic do not have any way to boost voltage [9, 10].
profile has led to the increase in demand for MLIs in various A thorough investigation of switched-capacitor (SC) based
industries, high-frequency AC power distribution, flexible AC multilevel inverters (SCMLI) is being done in order to over-
transmission system devices (FACTs), UPS systems, and electric come the above-discussed drawbacks of conventional MLIs. By
vehicles [2, 3]. MLIs were first introduced in 1962 [4]. The MLI’s using a suitable combination of capacitors and switches, higher
main goal is to develop an output voltage that is closer to a sine voltage levels can be generated. As a result of this, a significant
wave. Using a DC voltage source and multiple switching devices reduction in the number of DC sources can be achieved [11].
that are correctly coupled and controlled, the proper voltage Additionally, capacitor voltages are self-balanced by utilizing the
waveform is produced [5]. The literature contains numerous series-parallel balancing technique, thus eliminating the need for
MLIs based on the connection pattern of switching devices. complex control algorithms or auxiliary circuits to balance the
In general, there are three types of MLI topologies: diode- capacitor voltages. Mak and Ioinovici were the first to intro-
clamped MLI, cascaded H-bridge (CHB) MLI, and flying duce SCMLI in the year 1998 [12]. Since then, a lot of high-gain
capacitor (FC) MLI [6, 7]. As the number of levels in the output SCMLI topologies have come into the picture.
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2 HUSSAN ET AL.
Taking the thirteen-level (13L) topologies with a single DC

source into consideration, the authors in [13] are able to gen-
erate the required levels with a voltage gain of six. Although
the voltage stress over all 29 switches is limited to the input
voltage, the number of switches is rather significant. Vishal
and Varsha presented a 13L inverter using fifteen switches and
three capacitors with a maximum switch stress of three times
the input voltage [14]. A novel K-type 13L SCMLI topology is
proposed in [15], using fourteen switches and four capacitors,
but the voltage gain is only 1.5, and the total standing voltage
(TSV) is also high. By using fifteen switches, the authors in
[16] have presented six times boosted 13L inverter. The num-
ber of switches is further reduced to thirteen in [17–19]with
a gain of six, and the maximum switch stress is six times the
input voltage. The maximum switch stress increases as the num-
ber of switches are reduced. The topology described in [20]
has the fewest switches of the 13L topologies. It has a gain of
six, but its TSV is a little higher, which makes the overall cost
go up. FIGURE 1 Circuit topology of the proposed 13L SCMLI.
A cost-effective 13-level SCMLI topology with a low switch
count and high voltage gain is presented in this article. The TABLE 1 Switching table for the proposed 13L topology.
major contribution of the proposed topology and modulation
method are as follows: Switches Capacitors
S1,2 S3,4 S5,6 S7,8 S9,10 S11 C1 C2 C3 C4 Vout

∙ The proposed topology utilizes only one DC source, 11
10 10 01 10 01 0 D D C D +6Vdc
switches, and 4 capacitors for its operation at a voltage gain
of 6. 01 10 01 10 01 1 C D NC D +5Vdc
∙ Five pairs of switches are complementary, thus reducing the 01 01 01 10 01 0 NC NC NC D +4Vdc
number of driver circuits and complexity. 10 10 10 10 01 1 D D NC C +3Vdc
∙ TSV is also the lowest at 29 compared to other similar 01 01 10 01 01 0 NC NC NC D +2Vdc
topologies.
10 01 10 01 01 1 D C NC D +Vdc
∙ Since the proposed topology is self-balancing, no additional
10 10 10 01 01 0 NC NC NC C +0
sensor circuits or capacitor voltage balancing methods are
required. 10 10 01 10 10 0 NC NC C NC -0
∙ An Improved Nearest Level Modulation technique has been 10 01 01 10 10 1 D C D NC −Vdc
implemented to improve the output quality by minimizing the 10 10 01 10 10 0 NC C D NC −2Vdc
THD. 01 01 10 10 10 0 D D C NC −3Vdc
∙ It also has inductive load ability. These features make it suit-
01 01 10 01 10 0 NC NC D NC −4Vdc
able for low-voltage source applications such as PV and fuel
01 10 10 01 10 1 C D D NC −5Vdc
cells.
10 10 10 01 10 0 D D D C −6Vdc
The circuit configuration, its analysis, capacitors’ self-voltage
*C—Charge, D—Discharge, NC—No Change.
balancing, capacitor selection, and comprehensive comparative
analysis of the proposed topology with recent single-source 13L
topologies are discussed in Section 2. An Improved Nearest 2.1 Circuit description
Level Modulation (INLM) technique is presented in Section 3.
Section 4 discusses the power loss analysis. Section 5 dis- The circuit diagram of the proposed 13L SCMLI topology along
cusses simulation and experimental results for various loading with the maximum blocking voltage (MBV) of the switches
conditions. The article finishes with Section 6. is shown in Figure 1. It consists of a single DC source, four
capacitors, three power diodes, and only eleven switches. The
conduction diagram showing the different current paths and
2 PROPOSED 13L SCMLI TOPOLOGY the switching states of all the switches are shown in Figure 2
and Table 1, respectively. Red lines, green lines, black lines, and
Circuit description, its working principle, capacitor selection cri- blue lines with dots represent the capacitor discharging path
teria, and comparative analysis of the proposed topology have as well as conducting devices, the capacitor charging path, the
been discussed in this section. non-conducting path, and the path for reverse current in case
HUSSAN ET AL. 3
(a) (b) (c)
(d) (e) (f )
(g)
FIGURE 2 Conduction states for different modes of operation.
of inductive loading, respectively. Output levels are the same for 2.2 Working principle and self-voltage
resistive as well as inductive loads. Switch pairs (S1 , S2 ), (S3 , S4 ), balancing
(S5 , S6 ), (S7 , S8 ), and (S9 , S10 ) are complementary, which results
in a reduction in the number of drivers and complexity as well. Figure 2 and Table 1 demonstrate the conduction paths (includ-
Peak inverse voltage (PIV) for the switches S7 and S8 are lim- ing reverse current for inductive loads) and distinct switching
ited to half of the output voltage, thus eliminating the need for states for different levels, respectively. The proposed topology
a backend H-bridge. has thirteen switching states in a cycle (6 positive, 6 negative,
and a zero). The capacitors C1 /C2 and C3 /C4 are charged close
4 HUSSAN ET AL.
FIGURE 4 13L output voltage with inverted negative cycle showing

LDTs of different capacitors.
FIGURE 3 Voltage stresses on different components for each levels.

a DC source. Capacitors C1 and C2 are charged up to +Vdc via
the source. Through the series connection of C1 , C2 , and the
to Vdc and +3Vdc , respectively, to generate the thirteen levels supply, capacitors C3 and C4 are charged to +3Vdc . The charg-
at the output with a voltage gain of 6. ing and discharging time intervals for C1 , C2 , C3 , and C4 are
In state 1, zero output voltage is obtained, and C4 is charged shown in Figure 4. For evaluating the optimum value of capac-
to +3Vdc by the series connection of C1 , C2 , and the DC source. itors, the longest discharging time (LDT) of the capacitors is to
In state 2, capacitor C2 is in parallel to the DC source through be calculated [21–23]. The total discharge of capacitor C1 during
the switches S1 , S3 , S4 , S11, and diode D1 and charged to Vdc , as the LDT interval [t6 , T/2−t6 ] is computed using the following
shown in Figure 2a. In this state, capacitors C1 and C4 are linked formula:
in series with the DC source, resulting in a voltage across the T
−t6
load of +1Vdc . Only C4 is in series with the source during state 2
3, supplying +2Vdc to the load, as shown in Figure 2b. In state 4, 1

ΔQC 1 = iL (t ) dt (1)
only C4 is being discharged to the load, reflecting +3Vdc at the 2𝜋 f ∫
t6
load. Also, C4 is being charged to +3Vdc using C1 , C2, and the
DC source, which are connected through S1 , S3 , S5, and D3 . C4 where f represents the output voltage frequency, and iL is
(charged to +3Vdc ) is in series with the DC supply during state the load current. The total discharge of C2 for the longest
5, delivering +4Vdc to the load. C2 and C4 are in series with the discharging interval [t5 , T/2−t5 ] can be expressed as:
source in state 6, reflecting +5Vdc to the load. C1 is connected
to the DC source in parallel and charged to Vdc via S2 , S3 , S11, T
−t5
and D1 . C1 , C2, and C4 are in series with the source in state 1 2
ΔQC 2 = iL (t ) dt (2)
7, resulting in a voltage of +6Vdc across the load. Also, C3 is 2𝜋 f ∫t
5
being charged to +3Vdc by the series connection of C1 , C2 , and
the DC source. Switches S1 , S2 , S3 , S4, and S11 are experiencing As C3 and C4 have the same LDTs, the total discharge of C3
voltage stress of Vdc , while switches S5 , S6 , S7 , and S8 withstand and C4 for the longest discharging interval [t4 , T/2−t4 ] can be
voltage stress of 3Vdc , and the voltage stress across the switches expressed as:
S9 and S10 are +6Vdc as shown in Figure 3. It also gives voltage T
−t4
stresses on each switch for all thirteen levels. The sum of all the 1 2
ΔQC 3 = ΔQC 4 = iL (t ) dt (3)
switch stresses at any level is not more than 18 × Vdc, which 2𝜋 f ∫t
4
reflects the good performance of the proposed SCMLI.
Through the capacitors’ parallel connection to the source and From Equations (1), (2) and (3), the values of C1 , C2 , C3 and C4
in series with the load at different times, the four capacitors’ can be calculated as:
voltages are self-balanced to their appropriate voltage levels. As
T
the time constant and total parasitic resistance of the charg- −t6
1 2
ing loops are marginal, the capacitors’ time to get fully charged C1 = iL (t ) dt (4)
2𝜋 f ∗ ΔVC 1 ∫t
during any voltage level is always available. 6
T
−t5
1 2
C2 = iL (t ) dt (5)
2.3 Selection of capacitors 2𝜋 f ∗ ΔVC 2 ∫t
5
T
−t4
The proposed SCMLI topology generates a 13-level output 1 2
C3 = C4 = iL (t ) dt (6)
voltage by employing four capacitors (C1 , C2 , C3 , and C4 ) with 2𝜋 f ∗ ΔVC 2 ∫t
4
HUSSAN ET AL. 5
FIGURE 5 Modulation strategy. (a) Simple NLC scheme for n-levels. (b) Improved nearest level modulation for n-levels.
TABLE 2 Comparison with similar SCMLI topologies.
Total
MBV volume
Ref. NL Ndc Nsw Ndr ND NC (− Vdc ) TSVpu TCV CF Ncd VG Pout (W) (mm3 ) P.D (W/mm3 ) THD (%)
[13] 13 1 29 16 5 5 1 4.83 5 6.85 8 6 750 135,370.5 5.54 × 10−3 —

[14] 13 1 15 12 0 3 3 5 5 5.0 7 6 550 67,935.9 8.09 × 10−3 9.73
[15] 13 1 14 11 0 4 3 6 1.5 5.1 4 1.5 1000 91,653.2 1.09 × 10−2 5.31
[16] 13 1 14 12 1 3 3 5.5 5 5.23 7 6 250 69,686.3 3.59 × 10−3 —
[17] 13 1 13 11 2 3 6 6.5 5 5.62 6 6 150 70,236.9 2.14 × 10−3 3.98
[18] 13 1 13 13 2 3 6 5.33 5 5.0 7 6 1000 98,436.7 1.02 × 10−2 —
[19],1st topology 13 1 13 9 2 3 3 5.5 5 5.0 7 6 345 81,436.7 4.24 × 10−3 —
[19],2nd topology 13 1 12 6 4 3 3 6 5 5.1 6 6 340 76,425.5 4.45 × 10−3 —
[20] 13 1 10 5 4 4 6 6 5 4.92 5 6 500 88,654.8 5.64 × 10−3 11
[26] 17 1 10 8 5 5 8 5.875 13 5.18 5 8 217 107,098.5 2.03 × 10−3 3.97
[27] 11 1 9 7 4 4 6 6.2 8 5.73 5 5 225 87,166.8 2.58 × 10−3 6.8
[28] 17 2 10 6 2 2 8 5 4 3.41 5 8 1600 51,767.4 3.01 × 10−2 4.5
[24] 17 2 18 14 2 4 2 6 2 5.41 5 2 800 94,082 8.50 × 10−3 —
[P] 13 1 11 6 3 4 6 4.83 8 4.69 5 6 550 66,904 8.61 × 10−3 5.08
*Nsw , Ndr , ND , NC , Ncd , VG , MBV, TSV, TCV, CF, P.D, L, M , H, [P], THD: Indicates the number of switches, drivers, diodes, capacitors, conducting devices in the highest level, voltage
gain, maximum blocking voltage (switch stress) across switches, total standing voltage, total capacitor voltage, cost function, power density, low, medium, high, the proposed topology, and
output voltage total harmonic distortion.
By taking the allowable value of ∆Vc , the most appropriate (CF) play a crucial part. The proposed topology contains 11
value of circuit capacitors is determined by solving Equa- switches, the fewest after the one in [20]. Thus, the proposed
tions (4), (5), and (6). Capacitors C1 and C2 have optimal values topology and the topology presented in [20] have high power
of 2085 and 2617 µF, respectively. Capacitors C3 and C4 have density (D). Topologies presented in [13–16, 24] have low power
equal values of 3195 µF (Figure 5). density as their switch count is high. All the compared topolo-
gies have a gain of 6 except [15] which has a gain of 1.5. Total
standing voltage (TSV), the sum of maximum voltage stresses
2.4 Comparative study across all switches [25], is the minimum for the proposed topol-
ogy and the one in [13]. Additionally, switch pairs (S1 , S2 ), (S3 ,
Table 2 gives the quantitative results of comparison with the S4 ), (S5 , S6 ), (S7 , S8 ), (S9 , S10 ) are complementary in nature,
recently presented similar SCMLI topologies. The compared reducing the number of drivers. As stated earlier, the maxi-
parameters include the number of switches (Nsw ), number of mum voltage stress across the switches is at the highest level.
levels (NL ), number of drivers (Ndr ), number of diodes (ND ), Hence, the number of conducting devices in the highest level
number of capacitors (NC ), total standing voltage (TSV), maxi- (NCD ) is an important parameter that affects conduction loss.
mum blocking voltage (MBV), cost function (CF), number of The NCD for the proposed topology is also minimum. MBV is
conducting devices in the highest level (NCD ), voltage gain the maximum blocking voltage of the switches. When the num-
(VG ), power density (P.D), and total capacitor voltage (TCV). ber of switches is reduced and the gain is high, MBV increases.
Among these, the number of switches (Nsw ) and cost function MBV for the proposed topology and the topologies presented
6 HUSSAN ET AL.
in [17, 18, 20] is six times the input voltage. MBV for the topol- in the improved nearest level modulation technique, a variable
ogy presented in [26] is 8 since it has a gain of 8 and the number parameter g replaces the constant DC value of 0.5 (used in
of switches is less, that is, 10 for the generation of 17 levels. conventional NLM). The value of g can range from 0 to 1. A
But it has 5 capacitors to be balanced. Its normalized TSV is code is run to identify the value of g that corresponds to each
5.875 while that for the proposed topology is 4.83 (29/6). A m (in steps of 0.01) and results in minimum THD. Its imple-
similar topology is presented in [27], which generates 11 levels mentation strategy is shown in Figure 5b. The flowchart of
with quintuple voltage boosting using only 9 switches. MBV is the improved NLM strategy is shown in Figure 6. The THD
6 and the normalized TSV is 6.6. A novel basic unit has been expression for different levels has been derived from the general
given in [28]. By using this basic unit authors are able to gen- expression given in [30]. The MATLAB library’s inbuilt function
erate 17 levels utilizing 2 sources, 10 switches, and 2 capacitors. ‘min’ is used to determine the value of g at which the output
Its normalized TSV is 5. The topology presented in [24] is able voltage had the lowest THD. These (m,g) data sets are then
to generate 9 and 17 levels using single unit and 2 units in cas- plotted to determine the mathematical relationship between
caded fashion, respectively. For generating 17 levels it requires 2 them.
sources, 18 switches and 4 capacitors. Its normalized TSV is 6. ( 5)
Cost function (CF) is defined as [19], g = 2.5m − 2.1 form > (8)
6
(Nsw + Ndr + ND + NC + TSV + TCV ) ∗ Ndc ( 2 5)
CF = (7) g = 2.63m − 1.79 for < m < (9)
NL 3 6
( 1 2)
CF is also the lowest for the proposed topology at 4.69. g = 2.78m − 1.44 for < m < (10)
2 3
Power density of the proposed topology and the topologies
( 1 1)
compared in this section are calculated as [29]:
g = 2.85m − 1.02 for < m < (11)
3 2
( ) Pout (W )
Power density W∕mm3 = (8) Using these equations for having minimum output waveform
Total volume (mm3 ) THD, the value of g can be found for any modulation index m.
Figure 7 shows a THD comparison of the 13L output voltage
where Pout and total volume represent the output power and
of the proposed topology at different modulation indices for
total volume of the respective topologies. In order to calculate
the INLM and conventional NLM techniques.
the total volume of each topology, the volumes of individ-
ual energy storage components such capacitors and inductors
(inductor core), as well as the volumes of the power switches
4 POWER LOSS ANALYSIS
and power diodes employed, were collected from the datasheets
of those components and then added numerically. Total volume
Switches, diodes, and capacitors all contribute to the power loss
of the proposed topology is lowest after that of the topology
of the proposed topology [31]. Two major losses are switch-
presented in [28]. Hence, power density of the proposed topol-
ing loss and conduction loss. Switching losses occur due to
ogy is higher than most of the compared topologies as given in
the switch’s non-ideal behaviour, which can be calculated by
Table 2.
approximating the voltage and current to be linear during the
turn-on and turn-off periods. Power loss during turn-on, is
calculated by Equation (12) as:
3 IMPROVED NEAREST LEVEL
MODULATION (INLM) TECHNIQUE ton
PS , on, k = f v (t ) i (t ) dt
This section describes an improved NLM technique for improv- ∫
ing the output waveform’s quality, specifically its THD. The 0
implementation method for the 13-level inverter has been ton ( )( )
VS ,k Ik 1
established here. In the conventional nearest-level modulation = f t − (t − ton dt = fVS ,k Ik . (12)
)
∫0 ton ton 6
technique, the level varies when the reference sinusoidal wave
n−1
value msin(𝜔t ), where m is the modulation index and n is Power loss during turn-off, is calculated by Equation (13) as:
2
the output voltage level, crosses the constant DC values of
to f f
0.5, 1.5, 2.5, 3.5,… (n−1)/2+0.5 as shown in Figure 5a. The
n−1 PS , o f f , k = f v (t ) i (t ) dt
MLI changes its state from 0 to V as msin(𝜔t ) exceeds 0.5. ∫0
2
The switching state corresponding to 2 V is activated when the ( )( )
reference
to f f
VS ,k Ik′ ( )
= f t − t − to f f dt
ave
n−1
msin(𝜔t ) exceeds 1.5, and the level switches from ∫0 to f f to f f
2
V to 2V. All the output levels are generated in the same
1
way. Figure 5a depicts the NLM implementation plan. Here, = fV I ′t (13)
6 S ,k k o f f
HUSSAN ET AL. 7
FIGURE 6 Flowchart of the proposed improved nearest level modulation technique.
be calculated by multiplying the number of ON (Non ) and OFF

(No f f ) switching states in a cycle with Equations (12) and (13)
respectively, yielding Equation (14):
( )
∑11 ∑Non ∑No f f
PS = PS ,on,km + PS , o f f , km (14)
k=1 m=1 m=1
The ton and toff are related to the switch used, whereas Vs,k
is dependent on the inverter circuit design. The proposed
topology has the least TSV (the sum of all Vs,k ) among the
compared ones, thus reducing the switching loss. Also, Non and
Noff are low for the proposed topology as S9 and S10 are either
FIGURE 7 THD comparison at different modulation indices. switched off or on in a complete half cycle, and other switches
(S5 , S6 , S7 , S8 ) also have less number of switching, resulting in
reduced switching loss.
where Ik and Ik′ represent the currents flowing through the kth The on-state resistances and the forward voltage drop across
switch at turn-on and before turn-off, respectively, f represents the devices in the load current path are the main causes of con-
the switching frequency, and Vs,k represents the voltage stress duction loss [32–36]. Maximum load current flows at maximum
across the switch. The switching loss of all eleven switches may levels, resulting in high voltage stress across the switches and
8 HUSSAN ET AL.
TABLE 4 Circuit parameters of the proposed SCMLI.
Parameters Simulation Hardware
Input voltage 50 V 50 V
IGBT IGBT 1200 V/25 A (FGA25N120)
Diode diode Diode 160D40R
Driver — 10–35 V/ ± 1.5 A (TLP 250)
Controller — TMS320F28379D
Output frequency 50 Hz 50 Hz
Capacitors: C1 2200 µF 2200 µF/60 V
FIGURE 8 Power loss distribution at different input voltages.
Capacitors: C2 3300 µF 3300 µF/60 V
TABLE 3 Calculation of losses and efficiency at an output power of C3 , C4 3300 µF/250 V
300 W. R–L Load 75 Ω- 100 mH 75 Ω–100 mH
Parameters Simulation
Switching and conduction losses (W) 7.792

Capacitor C1 (W) 0.412 dynamic load changes from 50 to 100 Ω, 50 to 50 Ω + 120 mH,
Capacitor C2 (W) 0.742 and 50 Ω + 120 mH to 50 Ω + 240 mH, respectively. The
Capacitor C3 (W) 0.1 results show that with a single 50 V supply, the proposed topol-
Capacitor C4 (W) 0.054 ogy can generate a 13-level output waveform. The results show
the stable performance of the proposed topology during the
Total losses (W) 9.1
step change on the output active and reactive powers. An induc-
Efficiency (%) 97
tor (L1 ) has been used just above the DC source as shown in
Figure 1, to charge the capacitors in a smooth way. It is remark-
able to note that the inductor place is common for the charging
maximum conduction loss. To minimize this effect, the num-
paths of all the four capacitors. Also, a power diode has been
ber of conducting devices (Ncd ) at the highest level should be
connected in parallel with the inductor to make sure that the cur-
kept to a minimum. Ncd of the proposed topology is 5, which
rents going in the opposite direction have a way to flow freely.
is lower than the other compared topologies except in [15] as
Because of this, the proposed topology can limit the amount of
given in Table 2 and discussed in Section 2. Thus, these two
current that flows through the capacitors when they are being
major losses have been reduced, increasing the overall efficiency
charged. Self-balancing of the capacitor voltages and reduced
of the proposed topology. PLECS software is used to determine
voltage ripple features are depicted in the waveforms shown in
the power loss across different components of the converter.
Figure 9d,e. Capacitors C1 and C2 are charged equal to the input
IGA30N60H3_IGBT thermal model of switch is taken for the
voltage, 50 V, and capacitors C3 , and C4 are charged near to
loss calculations. Figure 8 presents the power loss distribution of
thrice the input voltage. The THD of the voltage waveform is
different components at different input voltages. It is observed
5.08% for the INLM and 6.75% for the simple NLM at unity
that the losses increase as the input voltage is increases. The cal-
modulation index whereas it is 5.92% for INLM and 7.23%
culation of losses and efficiency at an output power of 300 W is
for the simple NLM at a modulation index of 0.9 as shown in
given in Table 3. Efficiency at other output power is calculated
Figure 9f,g.
in the same manner.
5 SIMULATION AND EXPERIMENTAL 5.2 Experimental results

VALIDATION
The proposed 13L SCMLI topology was experimentally verified
The simulation study and experimental validation of the using an experimental prototype, as shown in Figure 10. Com-
proposed topology has been discussed in this section. ponents and their specifications are given in Table 4. The circuit
consists of an insulated-gate bipolar transistor (FGA25N120).
A gate driver circuit based on the TLP-250 is used to generate
5.1 Simulation results gate signals for individual IGBTs. For the proposed inverter,
a digital signal processor (DSP), TMS320F28379D, is used to
In order to validate and examine the efficacy of the proposed send gating signals to the switches. The experimental THD of
inverter, a model of the thirteen-level is built in MAT- the proposed MLI is measured using a FLUKE 435 series II
LAB/Simulink with the parameters given in Table 4. The power quality and energy analyzer.
switches are assumed to be real. The internal resistance of the The output voltage and current waveform for a resistive load
capacitors is taken to be 36 mΩ. Figure 9a–c shows the sim- of 75 ohms are shown in Figure 11a. As the input DC voltage
ulation results for output voltage and output current for the is taken to be 50 V, the peak output voltage is nearly coming
HUSSAN ET AL. 9
FIGURE 9 Simulation results of the proposed topology. (a–c) Output voltage and output current for resistive load change, resistive to inductive load change,
and inductive load change. (d–e) Capacitor voltages and capacitor currents with an inductor in the charging loop. (f–g) output voltage THD for improved NLM and
simple NLM at m = 0.9.
out to be 300 V which verifies the voltage boosting of 6. Out- respectively. It can be observed that the capacitor voltages are
put voltage and current for an inductive load of R = 75 Ω, quite balanced and maintained at almost +Vdc and +3Vdc as
L = 100 mH are shown in Figure 11b. The current waveform is discussed in Section 2.
sinusoidal and lagging. Figure 11c,d show the output waveforms In addition, the proposed topology has been experimentally
along with voltage across the capacitors C1 , C2, and C3 , and C4, validated for dynamic load change and modulation index varia-
HUSSAN ET AL.
Continued
FIGURE 9
10
HUSSAN ET AL. 11
after some time. After a change in load, the output waveform is

observed to be stable. Output waveform when the modulation
index (MI) is changed from 1 to 0.8 to 0.6 has been shown in
Figure 11f. The number of levels decreases as MI is decreased.
Voltage stress across all the eleven switches for the same loading
conditions has been shown in Figure 11g–i. Switches S1 , S2 , S3 ,
S4 and S11 are experiencing voltage stress of almost Vdc , while
switches S5 , S6 , S7 , and S8 withstand voltage stress of +3Vdc . The
voltage stress across the switches S9 and S10 is +6Vdc which is
as per the theoretical analysis.
Additionally, the efficiency of the proposed inverter has been
measured from 50 to 1000 Ω of the pure resistive load, and the
results are displayed in Figure 12. At 400 W output power, the
highest efficiency achieved is relatively good at 97.3%.
6 CONCLUSION
FIGURE 10 Experimental test set-up for the proposed 13L topology.
Here, a 13-level sextuple boost inverter with reduced switch
count and self-voltage balancing capability of capacitors is pro-
tion. Figure 11e shows the output waveform when the inverter posed. To produce the desired 13-level sextuple single-phase AC
is tested for dynamic load change as the load is halved from 75 Ω output voltage, the proposed SC-MLI requires one DC source,
FIGURE 11 Hardware results of the proposed topology. (a) Output voltage and current for a resistive load of 75 Ω. (b) Output voltage and current for an
inductive load of R = 75 Ω, L = 100 mH. (c) Output voltage, current and voltage across capacitors C1 and C2 . (d) Output voltage, current and voltage across
capacitors C3 and C4 . (e) Output waveform for dynamic load change, (f) output waveform for modulation index change, (g) voltage stress across switches S1 , S2 , S3 ,
S4 , (h) voltage stress across switches S5 , S6 , S7 , S8 , (i) voltage stress across switches S9 , S10 , S11.
12 HUSSAN ET AL.
Mohammad Tayyab https://orcid.org/0000-0003-3764-3459

Mohd Tariq https://orcid.org/0000-0002-5162-7626
Farhad Ilahi Bakhsh https://orcid.org/0000-0001-6452-
512X
Akbar Ahmad https://orcid.org/0000-0002-2785-7296
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A Single-Source Switched-Capacitor Based 13-Level Sextuple Boost Inverter With Reduced Component Count and Low THD

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A Single-Source Switched-Capacitor Based 13-Level Sextuple Boost Inverter With Reduced Component Count and Low THD

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Received: 9 August 2022 Revised: 26 February 2023 Accepted: 27 March 2023 IET Generation, Transmission & Distribution

A single-source switched-capacitor based 13-level sextuple boost

Md Reyaz Hussan1 Adil Sarwar1 Mohammad Tayyab1,2 Mohd Tariq1,3

1 INTRODUCTION voltage increases, these traditional MLIs suffer from a number

IET Gener. Transm. Distrib. 2023;1–13. wileyonlinelibrary.com/iet-gtd 1

Taking the thirteen-level (13L) topologies with a single DC

S1,2 S3,4 S5,6 S7,8 S9,10 S11 C1 C2 C3 C4 Vout

(a) (b) (c)

FIGURE 2 Conduction states for different modes of operation.

FIGURE 4 13L output voltage with inverted negative cycle showing

FIGURE 3 Voltage stresses on different components for each levels.

3, supplying +2Vdc to the load, as shown in Figure 2b. In state 4, 1

TABLE 2 Comparison with similar SCMLI topologies.

[13] 13 1 29 16 5 5 1 4.83 5 6.85 8 6 750 135,370.5 5.54 × 10−3 —

FIGURE 6 Flowchart of the proposed improved nearest level modulation technique.

be calculated by multiplying the number of ON (Non ) and OFF

TABLE 4 Circuit parameters of the proposed SCMLI.

Parameters Simulation Hardware

Switching and conduction losses (W) 7.792

5 SIMULATION AND EXPERIMENTAL 5.2 Experimental results

after some time. After a change in load, the output waveform is

Mohammad Tayyab https://orcid.org/0000-0003-3764-3459

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