See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/357883318

Aquila Optimization Based Harmonic Elimination in a Modified H-Bridge

Inverter

Article in Sustainability · January 2022

DOI: 10.3390/su14020929

CITATIONS READS
4 174

8 authors, including:

Md Reyaz Hussan Mohammad Irfan Sarwar

Aligarh Muslim University Université Grenoble Alpes
16 PUBLICATIONS 67 CITATIONS 5 PUBLICATIONS 27 CITATIONS

SEE PROFILE SEE PROFILE

Adil Sarwar Mohd Tariq

Aligarh Muslim University Aligarh Muslim University
148 PUBLICATIONS 1,026 CITATIONS 205 PUBLICATIONS 1,191 CITATIONS

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Solar inverter View project

Power Systems View project

All content following this page was uploaded by Irfan Khan on 04 February 2022.

The user has requested enhancement of the downloaded file.

 sustainability
Article
Aquila Optimization Based Harmonic Elimination in a
Modified H-Bridge Inverter
Md Reyaz Hussan 1 , Mohammad Irfan Sarwar 2 , Adil Sarwar 1, * , Mohd Tariq 1, * , Shafiq Ahmad 3 ,
Adamali Shah Noor Mohamed 4 , Irfan A. Khan 5 and Mohammad Muktafi Ali Khan 1






Citation: Hussan, M.R.; Sarwar, M.I.;
Sarwar, A.; Tariq, M.; Ahmad, S.;
Shah Noor Mohamed, A.; Khan, I.A.;
Ali Khan, M.M. Aquila Optimization
Based Harmonic Elimination in a
Modified H-Bridge Inverter.
Sustainability 2022, 14, 929. https://
doi.org/10.3390/su14020929
Academic Editor: Alberto-Jesus
Perea-Moreno
Received: 13 December 2021
Accepted: 11 January 2022
Published: 14 January 2022
Publisher’s Note: MDPI stays neutral
with regard to jurisdictional claims in
published maps and institutional affil-
iations.
Copyright: © 2022 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Sustainability 2022, 14, 929. https://doi.org/10.3390/su14020929
1 Department of Electrical Engineering, Zakir Husain College of Engineering and Technology (ZHCET),
Aligarh Muslim University, Aligarh 202002, India; mreyazamu@gmail.com (M.R.H.);
mmakhan.eed@gmail.com (M.M.A.K.)
2 Grenoble Institute of Technology—Ense3, Université Grenoble Alpes, 38400 Grenoble, France;
irfanamu97@gmail.com
3 Industrial Engineering Department, College of Engineering, King Saud University, P.O. Box 800,
Riyadh 11421, Saudi Arabia; ashafiq@ksu.edu.sa
4 Electrical Engineering Department, College of Engineering, King Saud University, P.O. Box 800, Riyadh 11421,
Saudi Arabia; anoormuhamed@ksu.edu.sa
5 Department of Marine Engineering Technology in a Joint Appointment with the Department of Electrical and
Computer Engineering, Texas A & M University, Galveston, TX 77553, USA; irfankhan@tamu.edu
* Correspondence: adil.sarwar@zhcet.ac.in (A.S.); tariq.ee@zhcet.ac.in (M.T.)
Abstract: Multilevel inverters (MLIs) are capable of producing high-quality output voltage and
handling large amounts of power. This reduces the size of the filter while also simplifying the
circuitry. As a result, they have a wide range of applications in industries, particularly in smart grids.
The input voltage boosting feature is required to use the MLI with renewable energy. Moreover,
many components are required to get higher output voltage levels that add weight and cost to
the circuit. Numerous MLI topologies have been identified to minimize the losses, device count,
and device ratings. A seven-level modified H-bridge inverter with a reduced component count,
and reduced THD is presented in this paper. Two DC sources with six IGBTs have been used to
generate a seven-level output voltage, and the Aquila Optimizer (AO) has been implemented to get
the regulated output. MATLAB/Simulink environment has been used for designing the simulation
model. Furthermore, the simulation result has been validated in the laboratory on a hardware setup
using the DSP-TMS320F28335 Launchpad. With the reduced number of switching devices as well as
the dc supply, the size of the inverter is compacted and becomes more economical.
Keywords: cascaded H-bridge (CHB); multilevel inverter (MLI); aquila optimizer (AO); total har-
monic distortion (THD)
1. Introduction
During recent years, multilevel inverters gained popularity in various power electron-
ics and renewable energy applications. It is due to enhanced power quality, reduced filter
requirement, high modularity, and reduced device stresses [1]. Drives and grid integration
applications rely on inverters for their functioning. The multilevel inverters were proposed
to address the shortcomings of the traditional two-level inverter. Although conventional
two-level inverters are simple to construct, they have several drawbacks. Their application
is limited to a small power range due to high total harmonic distortion (THD), which
requires better filter design and higher blocking voltage rating devices to improve power
quality. The multilevel inverter produces a multi-stepped ac voltage from multiple dc
voltage levels. The flying capacitor, diode clamped, and cascaded H-bridge topologies are
the most common multilevel inverter topologies [1–4]. The flying capacitor MLI and diode
clamped MLI suffers from the uneven voltage distribution across the capacitor connected in
series. Moreover, in diode clamped MLI, the diode requirement increases with an increase
https://www.mdpi.com/journal/sustainability
Sustainability 2022, 14, 929 2 of 16

in the levels. For high voltage generation, the number of components also increases. Hence,
their use is limited only to low and medium-voltage industrial applications [5,6]. Cascaded
H-bridge MLI necessitates the use of multiple isolated dc sources.
In recent years, numerous fascinating topologies, such as topologies implemented
with quasi Z-source and transformers, have been proposed to overcome the shortcomings
of conventional MLIs [2]. Switched-capacitor using the series-parallel configuration in
multilevel inverters is becoming more popular these days [7,8]. H-bridge can be used
at the end of multilevel inverters to withstand the high voltage stress. To achieve a
compact topology with lower losses, higher total standing voltage, and reduced cost,
many topologies based on a smaller number of diodes, power switches, isolated dc sources,
and capacitors have been proposed [9,10]. The MLI structure should be typically flexible
and modular, with the ability to be cascaded or arranged in such a way to get a boosted and
approximate the sinusoidal output voltage with a large number of levels. Voltage boosting
is not possible with commercially available multilevel inverters. For converters designed
to use in renewable energy systems, voltage boosting capability will be critical because
the voltage generated by fuel cells and PV panels is insufficient and must be boosted to
use for grid integration [9]. Some MLI topologies have small voltage gain. Moreover, the
MLIs have several dc voltage sources. The MLI’s size, cost, and complexity are reduced
by reducing the component count [11,12]. Hence, switching capacitors were introduced in
MLIs to achieve the above-said objective. As a result, recent research has focused on the
Switched Capacitor (SC) MLI, which is a promising voltage booster while using the fewest
dc sources only [13]. Switched Capacitor MLIs have inherent voltage boosting capabilities.
SCMLIs work on the principle of charging and discharging the capacitor to a certain voltage
value using some techniques. While using the capacitor as a substitute for dc power supply,
balancing the capacitor voltage is challenging [14–17].
Different optimization techniques are being used in the area of microgrid and power
systems. Authors in [18] proposed a hybrid optimization for microgrids based on a cyber-
physical power system (CPPS). In recent years, multilevel inverters (MLI) topologies have
been widely adopted in renewable energy system applications due to higher harmonics dis-
tortion in conventional inverters [19]. A lot of work has been done on H-bridge multilevel
inverters [20]. Controlling the output voltage in an MLI and simultaneously reducing the
harmonic content has been an area of research. Different modulation schemes have been
proposed for the same. Basically, the schemes can be divided into low and high-frequency
modulation schemes. Low-frequency modulation schemes include nearest level control,
selective harmonic elimination, selective harmonic mitigation, etc., while high-frequency
modulation schemes include phase and level shifted PWM schemes. Low-frequency
schemes have the advantage of lower switching loss and consequently higher efficiency.
This work uses the Aquila Optimizer (AO) algorithm to solve the SHE equations in
the seven-level modified H-bridge inverter. The AO is a population-based optimization
algorithm inspired by Aquila’s natural behavior while grabbing prey [21]. The Aquila
are known to use four different hunting strategies, each with its own set of characteristics
and the capacity of most Aquila to switch between them rapidly and intelligently. High
soar with a vertical stoop, contour flight with brief glide attack, low flight with a slow
downward attack, and walking and grabbing prey are those strategies that the Aquila
used while hunting. These features were included in the algorithm developed for solving
the optimization problems. Since SHE is also an optimization problem, authors have
used it to optimize the SHE equations for the seven-level modified H-bridge inverter. The
topology taken in this paper is the modified H-bridge inverter, which has reduced switching
components and no separate diodes. Consequently, the cost and size of the inverter are
reduced. Two dc sources have been used to generate a seven-level output voltage. Output
waveforms obtained from the simulation and hardware setup verify the effectiveness of
the proposed algorithm.
This paper is divided into six sections. While Section 1 was Introduction, discussion
and comparison of the seven-level modified H-bridge multilevel inverter with other well-
Sustainability 2022, 14, 929 3 of 16

established topologies is made in Section 2. Aquila Optimizer is explained in Section 3

and its formulation for the SHE problem. The simulation results are given in Section 4.
The hardware results are discussed in Section 5, and the conclusion part is presented in
Section 6.

2. Seven Level Modified H-Bridge Inverter

Multilevel inverters (MLIs) are extensively employed in renewable energy applications
for power conversion due to their attractive features, such as the need for fewer dc sources,
less dv/dt stress, and output voltage resembling the sine wave. Cascaded H-bridge
inverters have gained special attention because of their symmetrical structure, modularity,
and ease of control. The requirement for many dc sources is the major disadvantage of the
CHB-MLI. However, cascaded H-bridge multilevel inverters outperform the Neutral point
diode clamped and flying capacitors due to their modularity. Nevertheless, this required
many dc sources, which resulted in several issues, including increased volume and price.
The H-bridge inverter has been modified by adding one additional battery source
to the second leg and two more switches in opposite directions between two legs. Many
inverters exist for producing seven-level output. Table 1 illustrates the comparison of
some popular multilevel inverters with the proposed inverter for the component count
and the control complexity. It is noteworthy that the proposed converter with self-voltage
balancing property has fewer component counts and has no control complexity. There
are two possible connections of the battery source to generate the seven levels of output,
the series adding and the series-opposing connection. Figure 1 shows the series-opposing
connection, while Figure 2 shows the series adding.

Table 1. Components count for different single-phase seven-level multilevel inverters.

Clamped Active Total Parts Complexity of

Inverter Type DC Source Capacitor
Diode Switches Count Control
CHB symmetrical 3 0 0 12 15 Low
CHB asymmetrical 2 0 0 8 10 Low
NPC with voltage control 1 6 10 12 29 Very high
NPC without Voltage control 6 0 10 12 28 Low
FC14, x FOR PEER REVIEW
Sustainability 2022, 1 5 0 12 18 High 4 of 16
Modified H bridge 2 0 0 6 8 Very low

S5

S1 S3

V1 =2E Load V2 =E

S4 S2

S6

Figure 1. Series Opposing Connection.

S5

S1 S3

V1 =3E Load V2 =E
 S4 S2

S6
Sustainability 2022, 14, 929 4 of 16

Figure 1. Series Opposing Connection.

S5

S1 S3

V1 =3E Load V2 =E

S4 S2

S6

Figure 2.
Figure 2. Series Adding
Adding Connection.
Connection.

In
In the
the first
first connection,
connection, thethe maximum
maximum output output voltage
voltage is the the addition
addition of of both
both voltage
voltage
sources.
sources. The input voltage ratio is 2:1 to to generate
generate the the seven
seven equal
equal voltage
voltage steps.
steps. If the
the
battery V equals 2E and the V equals E, the possible output levels are
battery V11 equals 2E and the V22 equals E, the possible output levels are (0, +E, +2E, +3E and (0, +E, +2E, +3E and
0, –E, −
0, –E, −2E, −3E).IfIfone
2E, −3E). oneof ofthe
thebattery
batterysources
sourcesisis replaced
replaced by by the
the capacitor, charging is not not
possible.
possible. TheTheinput
inputvoltage
voltageis is
low lowas as
compared
compared to theto second
the second connection
connectionto obtain the same
to obtain the
output voltage.
same output The maximum
voltage. The maximumoutputoutput
voltagevoltage
equals equals
the higher input voltage
the higher source (V1)
input voltage in
source
the
(V1)second
in the connection. The input
second connection. Thevoltage
input ratio
voltageis 3:1 to generate
ratio the identical
is 3:1 to generate voltage steps.
the identical volt-
If
agethesteps.
inputIfVthe
1 equals
input3EVand V2 equals
1 equals 3E and E, V
the possible
2 equals E, output levels output
the possible are (0, +E, +2E,are
levels +3E
(0,and
+E,
0, –E, − 2E, − 3E). The input voltage required is higher as compared
+2E, +3E and 0, –E, −2E, −3E). The input voltage required is higher as compared to the first to the first connection
to obtain thetosame
connection obtainoutput voltage.
the same outputIf the battery
voltage. source
If the battery(V2 )source
is replaced
(V2) iswith a capacitor,
replaced with a
charging is possible due to the same polarity of the battery and the
capacitor, charging is possible due to the same polarity of the battery and the capacitor. capacitor. The capacitor
charges, discharges,
The capacitor charges,and remains unaffected
discharges, and remains in different
unaffected switching states.
in different However,
switching the
states.
key challenge is balancing the charging and discharging voltage
However, the key challenge is balancing the charging and discharging voltage in one com- in one complete cycle.
If the cycle.
plete charging voltage
If the is greater,
charging voltagethe capacitor
is greater, thevoltage
capacitor rises until rises
voltage it reaches
until itthe battery’s
reaches the
maximum voltage (V1 = V2 = 3E). As a result, it will only generate
battery’s maximum voltage (V1 = V2 = 3E). As a result, it will only generate three three levels (0, +3E, and
levels
− 3E). If discharging is greater in one cycle, the capacitor voltage decreases until it becomes
(0, +3E, and −3E). If discharging is greater in one cycle, the capacitor voltage decreases
zero. It also generates only three levels, which are (0, +E, and −E). If the capacitor voltage
until it becomes zero. It also generates only three levels, which are (0, +E, and −E). If the
remains constant (E) at the end of the complete cycle after charging and discharging, it
capacitor voltage remains constant (E) at the end of the complete cycle after charging and
can be used instead of the battery to generate the output levels throughout the infinite
discharging, it can be used instead of the battery to generate the output levels throughout
cycle. The capacitor voltage can be kept constant by using closed-loop voltage control, but
the infinite cycle. The capacitor voltage can be kept constant by using closed-loop voltage
it will be very complicated. Moreover, it requires additional circuitry and becomes more
control, but it will be very complicated. Moreover, it requires additional circuitry and be-
expensive and bulkier. Therefore, self-balancing of the capacitor is required to overcome
comes more expensive and bulkier. Therefore, self-balancing of the capacitor is required
this complexity. Table 2 shows the various switching states and possible outputs in both
series adding and opposing connections. Figure 3 shows the conduction pattern for the
different switching states in series opposing connections.

Table 2. Switching states for series adding and opposing connection.

Switching Series Adding Series Opposing

S1 S2 S3 S4 S5 S6
States/Modes Output Output
I ON - ON - ON - 0 0
II ON ON - - ON - −(V2 ) = −E (V2 ) = E
III ON - ON - - ON (V1 + V2 ) = 3E (V1 − V2 ) = 2E
IV ON ON - - - ON (V1 ) = 2E (V1 ) = 3E
V - ON - ON - ON 0 0
VI - - ON ON - ON (V2 ) = E −(V2 ) = −E
VII - ON - ON ON - −(V1 + V2 ) = −3E −(V1 -V2 ) = −2E
VIII - - ON ON ON - −(V1 ) = −2E −(V1 ) = −3E
 IV ON ON - - - ON (V1) = 2E (V1) = 3E
V - ON - ON - ON 0 0
VI - - ON ON - ON (V2) = E −(V2) = −E
VII - ON - ON ON - −(V1 + V2) = −3E −(V1-V2) = −2E
VIII
Sustainability 2022, 14, 929 - - ON ON ON - −(V1) = −2E −(V1) = −3E 5 of 16

S5 S5 S5 S5

S1 S3 S1 S3 S1 S3 S1 S3

V1 Load V2 V1 Load V2 V1 Load V2 V1 Load V2

S4 S2 S4 S2 S4 S2 S4 S2

S6 S6 S6 S6

(a) Mode-I (b) Mode-II (c) Mode-III (d) Mode-IV

S5 S5 S5 S5
S1 S3 S1 S3 S1 S3 S1 S3

V1 Load V2 V1 Load V2 V1 Load V2 V1 Load V2

S4 S2 S4 S2 S4 S2 S4 S2

S6 S6 S6 S6

(e) Mode-V (f) Mode-VI (g) Mode-VII (h) Mode-VIII

Figure 3. Conduction pattern of series opposing connection: (a) Mode-I;

Mode-I; (b) Mode-II; (c) Mode-III;
(d) Mode-IV;
(d) Mode-IV; (e)
(e) Mode-V;
Mode-V; (f)
(f)Mode-VI;
Mode-VI;(g)
(g)Mode-VII;
Mode-VII;(h)
(h)Mode-VIII.
Mode-VIII.

3. Aquila Optimizer:
3. Aquila Optimizer: A A Metaheuristic
Metaheuristic Optimization
Optimization Algorithm
Algorithm
The
The Aquila
Aquila Optimizer
Optimizer(AO)
(AO)isisa apopulation-based
population-based optimization
optimizationalgorithm inspired
algorithm by
inspired
Aquila’s natural behaviors while grabbing prey [14]. It is one of the most popular
by Aquila’s natural behaviors while grabbing prey [14]. It is one of the most popular birds birds
of
of prey
prey in
in the
the Northern
Northern Hemisphere.
Hemisphere. It It is
is aa member
member of of the
the Accipitridae family, which
Accipitridae family, which
includes almost all birds. The Aquila are known to use four different hunting
includes almost all birds. The Aquila are known to use four different hunting strategies,strategies,
each
each with
with its
its own
own set
set of
of characteristics
characteristics and
and thethe capacity
capacity of
of most
most Aquila
Aquila to
to switch
switch between
between
them rapidly and intelligently.
them rapidly and intelligently.
• For hunting birds in flight, the first method, to high soar with a vertical stoop, is used,
in which the Aquila rises high above the ground. The Aquila enters a long, low-angled
glide once it has found prey, with speed increasing as the wings shut farther. The
Aquila must have a height advantage over its target for this approach to work. To
simulate a thunderclap, the wings and tail are unfolded just before the engagement,
and the feet are propelled forward to seize the prey.
• The second approach, the contour flight with brief glide attack, is considered as
Aquila’s most commonly employed method, in which the Aquila rises from the ground
at a low level. Whether the prey is running or flying, the prey is pursued carefully.
This strategy is ideal for hunting ground squirrels, breeding grouse, or seabirds.
• A low flight with a slow downward attack is the third method. In this case, the Aquila
dives to the ground and then attacks the prey one by one. The Aquila chooses its
target and lands on its neck and back, attempting to enter. This approach is used for
hunting slow prey like rattlesnakes, hedgehogs, foxes, and tortoises, as well as any
species that lacks an escape response.
• Walking and grabbing prey is the fourth approach, in which the Aquila wanders on
land and tries to draw its prey. It is used to remove the young of large prey animals
(such as deer or sheep) from the covered area.
 Sustainability 2022, 14, 929 6 of 16

Finally, Aquila is one of the most clever and skilled hunters, second only to humans.
The methodologies listed above served as the main motivation for the suggested AO
algorithm. The subsections that follow discuss how the AO models these processes.

3.1. Initialization of the Solution

The optimization rule in AO starts with the generation of a population of candidate
solutions (S) as shown in Equation (1), which is created stochastically between the problem’s
upper (UB) and lower (LB) bounds. In each iteration, the best-obtained answer is roughly
determined as the optimal solution.

S1,1 S1,j S1,m−1 S1,m

 
···

 S1,2 S2,j ··· S2,m 

 .. .. 
S=
 . . ... ... ... 
 (1)

S N −1,1 S N −1,j .. S N −1,m


··· . 
S N,1 S N,j S N, m−1 S N,m

where S signifies a set of current candidate solutions produced at random using Equation (2),
Si denotes the ith solution’s decision values (positions), N denotes the total number of
candidate solutions (population), and m denotes the problem’s dimension size.


Si,j = rand × UBj − LBj + LBj , i = 1, 2, . . . , N j = 1, 2, . . . , m (2)

where rand is the random number, UBj denotes jth upper bound, LBj denotes the jth lower
bound of the given problem.

3.2. Mathematical Modeling of AO

The suggested AO technique simulates Aquila’s hunting behavior, displaying each
phase of the hunt. As a result, the suggested AO algorithm’s optimization processes are
divided into four categories: high soar with a vertical stoop, contour flying with short glide
attack, exploitation inside a converging search space by low flight with slow descent assault,
and swooping by walk and grab prey. The AO algorithm can move from exploration steps
to exploitation steps utilizing its various behaviors. If t ≤ (2/3*T), exploration steps are
executed; otherwise, the exploitation steps are completed. The mathematical model7 of
Sustainability 2022, 14, x FOR PEER REVIEW of AO
16
is as follows:

3.2.1. Expanded Exploitation (S1 )

3.2.1. Expanded Exploitation (𝑆 )
The Aquila recognizes the prey area and chooses the ideal hunting area using the
firstThe Aquila
method (S1recognizes the prey
), which involves area soar
a high and with
chooses the ideal
a vertical hunting
stoop. areaexplores
The AO using the
the
first method
search ), which
arena(𝑆from involves
a high altitudea to
high soar withthe
determine a vertical
locationstoop.
of the Theprey.AO explores
This theis
behavior
search arena from
represented a high altitude
mathematically to determine
as Equation (3). the location of the prey. This behavior is
represented mathematically as Equation  (3). 
t
𝑡
t + 1) = S ( t ) × 1 −
S1 ((𝑡 (t) − Sbest(𝑡)
+ (S (𝑡) (t) ∗ rand) (3)
𝑆 + 1) = 𝑆best (𝑡) × 1 − T + (𝑆 M −𝑆 ∗ 𝑟𝑎𝑛𝑑) (3)
𝑇
where𝑆 S(𝑡
where 1 (+
t +1)1)isisthe
thesolution
solution obtained
obtained byby thethe
firstfirst
search procedure
search procedure 𝑆 for
S1 the
for next it-
the next
eration of of
iteration t. The
t. Thebest-obtained
best-obtainedsolution
solutiontill
tillthe
the tth
tth iteration is is S𝑆best (t(𝑡), whichrepresents
), which represents the
approximate
the approximate location
locationof the
of prey. The term
the prey. The (1 − Tt (1
term ) is−used
) istoused
control the number
to control of iterations
the number of
in the expanded
iterations search (exploration).
in the expanded The location
search (exploration). mean value
The location mean of value
the current
of the solutions
current
connected at the tth iteration is denoted
solutions connected at the tth iteration is denoted by S ( t ) , which is derived
M by 𝑆 (𝑡), which is derived using Equation (4). ‘t’
using Equa-
and ‘T’ represent the current iteration and the maximum number of
tion (4). ‘t’ and ‘T’ represent the current iteration and the maximum number of iterations, iterations, respectively.
‘rand’ is a random
respectively. ‘rand’ is value between
a random 0 and
value 1.
between 0 and 1.
1 N
== ∑
S M𝑆(t)(𝑡) ∑ 𝑆S (𝑡) (t), Ɐjj ==1,2,…,m
1, 2, . . . , m (4)(4)
N i =1 i
where N is the population size and m is the dimension size of the problem.

3.2.2. Narrowed Exploitation (𝑆 )

The Aquila circles over the target prey, prepares the land, and then attacks in the
second method (𝑆 ). Contour flying with a short glide attack is the name given to this
Sustainability 2022, 14, 929 7 of 16

where N is the population size and m is the dimension size of the problem.

3.2.2. Narrowed Exploitation (S2 )

The Aquila circles over the target prey, prepares the land, and then attacks in the
second method (S2 ). Contour flying with a short glide attack is the name given to this
technique. In preparation for the attack, AO narrowly investigates the intended prey’s
chosen region. The mathematical expression for this behavior is given in Equation (5).

S2 (t + 1) = Sbest (t) × Levy(dm) + SR (t) + (y − x ) ∗ rand (5)

where S2 (t + 1) is the result of the second search method’s next iteration of t. The dimension
space is dm, and the levy flight distribution function is Levy(dm), which is derived using
Equation (6). At the ith iteration, SR (t) is a random solution picked in the range of [1 N].

b×σ
Levy(dm) = a × 1
(6)
|c| β

where a is constant with a value of 0.01, b and c are random numbers between 0 and 1. σ is
obtained using Equation (7).
  
πβ
Γ (1 + β) × sin 2
σ=    β −1
 (7)
1+ β
Γ 2 ×β×2 2

where β is a constant with a fixed value of 1.5. In Equation (5), the spiral shape in the search
is represented by y and x, which are determined as follows.

y = r × cos(θ ) (8)

x = r × sin(θ ) (9)
where,
r = r1 + W × d1 (10)
θ = − α × d1 + θ1 (11)
3π
θ1 = (12)
2
r1 has a value between 1 and 20 for a specific number of search cycles, and W is constant
with a small value of 0.00565. ‘d1 ’ is integer values between 1 and the length of the search
space (m), α is a small constant term with a value of 0.005.

3.2.3. Expanded Exploitation (S3 )

When the prey location is precisely identified and the Aquila is ready to land and
strike, the third approach (S3 ) is used. The Aquila descends vertically with a preliminary
attack to detect the prey reaction. Low flying with gradual descent assault is the name
of this technique. AO uses the target’s specified area to go close to the prey and attack.
Mathematically this behavior can be expressed as in Equation (13).

S3 (t + 1) = (Sbest (t) − S M (t)) × γ − rand + ((UB − LB) × rand + LB) × δ (13)

where S3 (t + 1) is the solution of the third search method’s next iteration of t. Sbest (t) signifies
the prey’s approximate location till the ith iteration (the best-obtained solution), while S M (t)
denotes the current solution’s mean value at the tth iteration, which is determined using
Equation (4). Here, the exploitation adjustment parameters are set to a small value (0.1).
The lower bound of the given problem is denoted by LB, and the upper bound is denoted
by UB.
Sustainability 2022, 14, 929 8 of 16

3.2.4. Narrowed Exploitation (S4 )

When the Aquila approaches the prey in the fourth method (S4 ), the Aquila attacks
the prey over land based on their stochastic motions. This technique is known as “walk
and grab prey”. Finally, in the last spot, AO attacks the prey. Mathematically, this behavior
can be expressed as in Equation (14).

S4 (t + 1) = Q f × Sbest (t) − ( P1 × S(t) × rand) − P2 Levy(dm) + rand × P1 (14)

where S4 (t + 1) is the solution of the fourth search method for the following iteration of t.
The quality function Qf is used to balance the search techniques and is determined using
Equation (15). P1 represents multiple AO motions that are utilized to monitor the prey
during the flight and are formed using Equation (16). P2 shows decreasing values from 2 to
0, which represent the AO’s flight slope as it follows the prey during the trip from the first
(1) to the last (t) location, which is calculated using Equation (17). The current solution at
the tth iteration is S(t).
2×rand−1
Q f (t) = t (1− T )2 (15)
P1 = 2 × rand − 1 (16)
 
t
P2 = 2 × 1 − (17)
T
Q f (t) represents the quality function value for the tth iteration. A flowchart of the Aquila
algorithm has been presented in Figure 4.

3.2.5. Selective Harmonic Elimination using Aquila Optimizer

The selective harmonic problem can be developed using the following equations

3Vdc
H1 = [cos(α1 ) + cos(α2 ) + cos(α3 )] (18)
π
3Vdc
H5 = [cos(5α1 ) + cos(5α2 ) + cos(5α3 )] (19)
5π
3Vdc
H7 = [cos(7α1 ) + cos(7α2 ) + cos(7α3 )] (20)
7π
Hi represents the magnitude of the various harmonics in the output voltage. In order to
incorporate the THD minimization along with the harmonic elimination following objective
function is taken.
Vdc − H1 4 2
(50Hi )2
 
Obj = 100 +∑ (21)
Vdc 1
H1
where Vdc is the dc source voltage, H1 represents the fundamental voltage, Hi represents
the Fourier equations. The following constraint should also be included in the problem
formulation:
0 < α1 < α2 < α3 < π/2
 𝑉𝑑𝑐 −𝐻1 (50𝐻𝑖 )2
𝑂𝑏𝑗 = (100
𝑉𝑑𝑐
) + ∑21 𝐻1
(21)

where Vdc is the dc source voltage, H1 represents the fundamental voltage, Hi represents
the Fourier equations. The following constraint should also be included in the problem
formulation:
Sustainability 2022, 14, 929 9 of 16
0 < α1 < α2 < α3 < π/2

Figure4.4.Flowchart
Figure FlowchartofofAquila
AquilaAlgorithm.
Algorithm.

Figure
Figure5a5ashows
showsthe theplot
plotbetween
betweenTHD THDper perunit
unitand
andthethemodulation
modulationindexindexforforthe
the
Aquila optimizer as well as the Genetic algorithm and Differential evolution
Aquila optimizer as well as the Genetic algorithm and Differential evolution for the ob- for the objective
function mentioned
jective function in Equation
mentioned (21). Zoomed
in Equation view forview
(21). Zoomed modulation index above
for modulation 0.4above
index has
also
0.4 been shown
has also forshown
been better for
view. Aquila
better optimizer
view. Aquila is comparable
optimizer to both of them
is comparable andof
to both works
them
better in the better
and works regioninwhere MI is where
the region aroundMI 0.6,
is 0.5, and 0.6,
around less 0.5,
thanand 0.2.less
Figure
than5b represents
0.2. Figure 5b
the convergence
represents curve for thecurve
the convergence Aquilaforoptimizer
the Aquilaforoptimizer
four different modulation
for four differentindices. The
modulation
number of iterations taken is 1000. The parameters that have been
indices. The number of iterations taken is 1000. The parameters that have been takentaken in running thein
optimization code are shown in Table 3.
running the optimization code are shown in Table 3.

Table 3. Parameters used.

Differential
Sl. No. Genetic Algorithm Aquila Optimizer
Evolution
1 Population = 40 Population = 40 Population = 40
2 Mutation Rate = 0.01 Mutant Factor = 0.01 Alpha = 0.1, delta = 0.1, omega = 0.005
3 Crossover Rate = 0.6 Crossover Rate = 0.6 U = 0.0265, r0 = 10
 Table 3. Parameters used

Sl. No. Genetic Algorithm Differential Evolution Aquila Optimizer

1 Population = 40 Population = 40 Population = 40
Sustainability 2022, 14, 929 10 of 16
2 Mutation Rate = 0.01 Mutant Factor = 0.01 Alpha = 0.1, delta = 0.1, omega = 0.005
3 Crossover Rate = 0.6 Crossover Rate = 0.6 U = 0.0265, r0 = 10

(a)

(b)
Figure
Figure 5. 5.
(a)(a) Variation
Variation of of
THDTHDpuwith
withmodulation
modulationindex
indexfor
forAquila,
Aquila, GA,
GA, and
and DE
DE algorithm.(b)
algorithm. (b)Con-
Con-
pu
vergence curve for the Aquila Optimizer.
vergence curve for the Aquila Optimizer.

4. 4.Simulation
Simulation Results
Results
The
The simulation
simulation of the
of the modified
modified H-Bridge
H-Bridge inverter
inverter has done
has been been in
done ® /Simulink.
in MATLAB
MATLAB ® /Sim-

ulink.
The two The two voltage
unequal unequalsources
voltage(Vsources (VV
1 = 120 V, 1=
2 120
= 60V,
V)Vhave
2 = 60 V) have
been usedbeen used to
to produce produce
different
voltage levels.
different Thelevels.
voltage voltage source
The is in
voltage a 2:1 ratio,
source is in awhich produces
2:1 ratio, a seven-level
which produces output
a seven-level
voltage.
outputIGBTs have
voltage. beenhave
IGBTs used been
for the switches,
used for theand the pulse
switches, andgenerator
the pulseblock has generated
generator block has
the switching pulse. The simulation parameters are noted in Table 4. Simulation
generated the switching pulse. The simulation parameters are noted in Table 4. Simulation results
have been
results shown
have beeninshown
Figurein6.Figure
The different gating signals
6. The different gating have been
signals haveshown
been in Figure
shown in 6a.
Fig-
Figure 6bFigure
ure 6a. shows6b theshows
output voltage
the outputand output
voltage andcurrent
outputwaveform for a resistive
current waveform for a load of
resistive
50 ohms. Output voltage and current waveforms for an inductive load of R = 50 ohms and
L = 120 mH have been shown in Figure 6c. Figure 6d, e show the output waveforms for a
dynamic load change from a load of 100 ohms to 50 ohms and from 50 ohms to 100 ohms,
respectively.
 load of 50 ohms. Output voltage and current waveforms for an inductive load of
ohms and L = 120 mH have been shown in Figure 6c. Figure 6d, e show the output
Sustainability 2022, 14, 929 11 of
forms for a dynamic load change from a load of 100 ohms to 50 ohms and16 from 50
to 100 ohms, respectively.

Table
Table 4. Simulation 4. Simulation Parameters.
Parameters.
No.
S. No. Parameters/Components
S. No. Specifications
Parameters/Components No. of Components
Specifications
Compo
1. Voltage Source (DC) 60 V, 120 V Two
1. Voltage Source (DC) 60 V, 120 V Tw
2. Reference signal frequency 50 Hz
2. Reference signal frequency 50 HzOne On
− 3 Ω
Resistance (Internal) = 110 Resistance (Internal) = 110−3 Ω
3. Insulated-Gate Bipolar Transistor (IGBT)Insulated-Gate Bipolar = 110−5 Ω
Resistance (Snubber) Six
3. Resistance (Snubber) = 110−5 Ω Si
Capacitance
Transistor (Snubber) Cs = 0
(IGBT)
Capacitance (Snubber) Cs = 0
4. Load R = 50 Ω, 100 Ω, L = 100 mH One
4. Load R = 50 Ω, 100 Ω, L = 100 mH On

(a)

R=50

(b)

Figure 6. Cont.
Sustainability 2022, Sustainability
14, 929 2022, 14, x FOR PEER REVIEW 12 of 16 1

R= 50
L=100mH

(c)

R=100 R=50

(d)

R=50 R=100

(e)

Figure 6. OutputFigure
voltage6.and
Output voltage
current and
for (a) current
R-load for. (a)
of 50 R-load
. . (b) of 50ofΩR(b)
RL-load RL-load
= 50 ... , L =of100
R =mH
50 Ω, L=100
change
(c) change in load from in
R =load
100from
. . . toRR= =
100
50Ω. .to R =change
. (d) 50 Ω (d)inchange in load
load from R =from
50 . . R = 50
. to R= Ω100
to R. .=. 100 Ω (e)
in load from R = 100 Ω to R = 50 Ω.
(e) change in load from R = 100 . . . to R = 50 . . .

5. Experimental 5. Validation
Experimental Validation
The hardware implementation of the seven-level
The hardware implementation modified
of the H-bridge
seven-level has been
modified carried
H-bridge has been c
out to validate the proposed topology, which is shown in Figure 7. Six IGBTs (FGA25N120)
out to validate the proposed topology, which is shown in Figure 7. Six
of 1200 V and 25 A have beenof
(FGA25N120) used in V
1200 the setup.
and 25 ATLP-250 Optocoupler
have been used in theis used
setup.forTLP-250
the gateOptocou
driver circuit. Digital signal controller TMS320F28335 (Texas Instruments) has been
used for the gate driver circuit. Digital signal controller TMS320F28335 used to
generate the control signal for
Instruments) the
has IGBTs.
been usedTwo DC voltage
to generate the sources
control of 60 Vfor
signal and 120
the V have
IGBTs. Two DC v
been used to provide
sourcesthe
of power supply
60 V and 120 to the modified
V have been usedH-bridge inverter.
to provide Figure supply
the power 8 showsto the mo
 is resistive. For the same load, output waveform and voltage stresses across S2 and S6 are
shown in Figure 8b. Figure 8c shows the output voltage and output current for an
inductive load of R = 50 ohm, L = 100 mH. The output current is sinusoidal as the load is
inductive. The proposed topology has also been tested for dynamic load change, as shown
in Figure 8d,e for increasing and decreasing load, respectively. The results verify that the
Sustainability 2022, 14, 929 proposed inverter is stable in dynamic loading conditions. The harmonic profile 13 of
of16the
output voltage verifies that the fifth and seventh harmonics are eliminated, as shown in
Figure 8f. The components used in this experiment have been listed in Table 5.
the various experimental results. The output voltage, output current, and voltage stresses
Tableswitches
across 5. Experimental
S1 and Parameters.
S5 for a resistive load of 50 ohms are shown in Figure 8a. The peak
output voltage is about 180 V, which is the sum of the input voltage sources. The output
No. of
current
S. No.replicates the output voltage as the load isSpecifications
Components/Parameters resistive. For the same load, output
Components
waveform and voltage stresses across S2 and S6 are shown in Figure 8b. Figure 8c shows
the output Insulated-Gate Bipolar
voltage and output current for an inductive load of R = 50 ohm, L = 1006 mH.
1. FGA25N120
Transistor (IGBT)
The output current is sinusoidal as the load is inductive. The proposed topology has also
2.
been tested IGBTs Driver
for dynamic circuit as shown inTLP
load change, 250H,
Figure 8d,e±12
forV, 1A
increasing 6
and decreasing
3.
load, respectively. DSP
The Board
results TMS320F28335
verify that the (TexasisInstruments)
proposed inverter 1
stable in dynamic loading
conditions.
4. The harmonic profile of the output voltage
Power Supply 60 verifies
V, 120 Vthat the fifth and seventh
2
harmonics
5. are eliminated,
Loadas shown in Figure 8f. The components used
50 Ω, 100 Ω, L = 100 mH in this experiment
1
have been
6. listed in Table(Fundamental)
Frequency 5. 50 Hz _

DC Power
Digital Storage Supply
Oscilloscope

Power Electronic
Converter Bed Capacitor

Laptop
Driver Circuit
Load

Digital Signal
Processor
TMS320F28335

Figure
Figure 7. 7. Laboratory
Laboratory Experimental
Experimental Setup.
Setup.

Table 5. Experimental Parameters.

S. No. Components/Parameters Specifications No. of Components

Insulated-Gate
1. Bipolar Transistor FGA25N120 6
(IGBT)
2. IGBTs Driver circuit TLP 250 H, ±12 V, 1 A 6
3. DSP Board TMS320F28335 (Texas Instruments) 1
4. Power Supply 60 V, 120 V 2
5. Load 50 Ω, 100 Ω, L = 100 mH 1
Frequency
6. 50 Hz _
(Fundamental)
Sustainability 2022,
Sustainability 14, 14,
2022, 929x FOR PEER REVIEW 14 of1416
of 16

Vout
Vout
100V
100V

Iout Iout
10A 10A
Vs2
Vs1
100V
100V
Vs5
Vs6
100V
100V

(a) (b)

Vout
100V Vout
100V

Iout
R=25Ω R=50Ω
10A
Iout
10A

(c) (d)

Vout
100V

R=50Ω R=25Ω

Iout
10A

(e) (f)

Figure8.8.Output
Figure Output waveforms
waveforms (a)
(a)output
outputvoltage,
voltage,output
outputcurrent
currentandand
voltage stress
voltage across
stress S1, and
across S1 ,Sand
5

S5(b)
(b)output
output voltage, output
voltage, current
output and and
current voltage stressstress
voltage acrossacross
S2, andS2S,6 (c)
andoutput
S6 (c)waveform for an
output waveform
for an inductive load (d,e) output waveform for dynamic load change (f) harmonic profile of the
output voltage.
Sustainability 2022, 14, 929 15 of 16

6. Conclusions
A seven-level modified H-bridge inverter with a reduced component count and
reduced THD is presented in this paper. Two DC sources with six IGBTs have been
used to generate a seven-level output voltage, and the Aquila Optimizer (AO) has been
implemented to control the output voltage with a feature to eliminate 5th and 7th harmonics.
Simulation has been done in MATLAB/Simulink environment. The result shows that the
AO gives a better result for a range of modulation indices than many of the well-known
meta-heuristic algorithms like GA and DE. Comparison of the presented topology with
other well-established topologies has also been done. Experimental results obtained verified
the findings of the simulation and theoretical analysis.

Author Contributions: Conceptualization, M.R.H., A.S. and M.T.; Formal analysis, M.R.H., M.I.S.,
A.S., M.T. and I.A.K.; Funding acquisition, S.A. and A.S.N.M.; Investigation, M.R.H., M.I.S., A.S.,
M.T. and S.A.; Methodology, M.R.H., M.I.S., A.S., M.T. and S.A.; Supervision, A.S. and M.T.; Valida-
tion, M.M.A.K.; Writing—original draft, M.R.H. and M.I.S.; Writing—review & editing, A.S., M.T.,
S.A., A.S.N.M., I.A.K. and M.M.A.K. All authors have read and agreed to the published version of
the manuscript.
Funding: The authors extend their appreciation to King Saud University for funding this work
through Researchers Supporting Project number (RSP-2021/387), King Saud University, Riyadh,
Saudi Arabia.
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Not applicable.
Acknowledgments: The authors acknowledge King Saud University for funding this work through
Researchers Supporting Project number (RSP-2021/387), King Saud University, Riyadh, Saudi Arabia.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Sarwar, M.I.; Sarwar, A.; Farooqui, S.A.; Tariq, M.; Fahad, M.; Beig, A.R.; Alamri, B. A Hybrid Nearest Level Combined with
PWM Control Strategy: Analysis and Implementation on Cascaded H-Bridge Multilevel Inverter and its Fault Tolerant Topology.
IEEE Access 2021, 9, 44266–44282. [CrossRef]
2. Kumari, M.; Siddique, M.D.; Sarwar, A.; Tariq, M.; Mekhilef, S.; Iqbal, A. Recent trends and review on switched-capacitor-based
single-stage boost multilevel inverter. Int. Trans. Electr. Energy Syst. 2021, 31, e12730. [CrossRef]
3. Sarwar, A.; Sarwar, I.; Alam, S.; Ahmad, S.; Tariq, M. A Nine-Level Cascaded Multilevel Inverter with Reduced Switch Count and
Lower Harmonics. In Lecture Notes in Electrical Engineering; Springer: Singapore, 2019; Volume 553, pp. 723–738.
4. Raman, S.R.; Cheng, K.W.E.; Ye, Y. Multi-Input Switched-Capacitor Multilevel Inverter for High-Frequency AC Power Distribution.
IEEE Trans. Power Electron. 2018, 33, 5937–5948. [CrossRef]
5. Tayyab, M.; Sarwar, A.; Tariq, M.; Chakrabortty, R.K.; Ryan, M.J. Hardware-in-the-Loop Implementation of Projectile Target
Search Algorithm for Selective Harmonic Elimination in a 3-Phase Multilevel Converter. IEEE Access 2020, 9, 30626–30635.
[CrossRef]
6. Siddique, M.D.; Mekhilef, S.; Shah, N.M.; Sarwar, A.; Iqbal, A.; Tayyab, M.; Ansari, M.K. Low Switching Frequency Based
Asymmetrical Multilevel Inverter Topology with Reduced Switch Count. IEEE Access 2019, 7, 86374–86383. [CrossRef]
7. Hussan, R.; Sarwar, A.; Khan, I.; Tariq, M.; Tayyab, M.; Alhosaini, W. An Eleven-Level Switched-Capacitor Inverter with Boosting
Capability. Electronics 2021, 10, 2262. [CrossRef]
8. Fong, Y.C.; Raman, S.R.; Ye, Y.; Cheng, K.W.E. Generalized Topology of a Hybrid Switched- Capacitor Multilevel Inverter for
High- Frequency AC Power Distribution. IEEE J. Emerg. Sel. Top. Power Electron. 2020, 8, 2886–2897. [CrossRef]
9. Zamiri, E.; Vosoughi, N.; Hosseini, S.H.; Barzegarkhoo, R.; Sabahi, M. A New Cascaded Switched-Capacitor Multilevel Inverter
Based on Improved Series–Parallel Conversion with Less Number of Components. IEEE Trans. Ind. Electron. 2016, 63, 3582–3594.
[CrossRef]
10. Tayyab, M.; Sarwar, A.; Khan, I.; Tariq, M.; Hussan, R.; Murshid, S.; Alhosaini, W. A Single Source Switched-Capacitor 13-Level
Inverter with Triple Voltage Boosting and Reduced Component Count. Electronics 2021, 10, 2321. [CrossRef]
11. Hussan, M.R.; Sarwar, A.; Siddique, M.D.; Mekhilef, S.; Ahmad, S.; Sharaf, M.; Zaindin, M.; Firdausi, M. A novel switched-
capacitor multilevel inverter topology for energy storage and smart grid applications. Electronics 2020, 9, 1703. [CrossRef]
12. Taheri, A.; Rasulkhani, A.; Ren, H.-P. An Asymmetric Switched Capacitor Multilevel Inverter with Component Reduction. IEEE
Access 2019, 7, 127166–127176. [CrossRef]
Sustainability 2022, 14, 929 16 of 16

13. Talooki, M.F.; Rezanejad, M.; Khosravi, R.; Samadaei, E. A Novel High Step-Up Switched-Capacitor Multilevel Inverter with
Self-Voltage Balancing. IEEE Trans. Power Electron. 2021, 36, 4352–4359. [CrossRef]
14. Ye, Y.; Cheng, E.K.W.; Liu, J.; Ding, K. A Step-Up Switched-Capacitor Multilevel Inverter with Self-Voltage Balancing. IEEE Trans.
Ind. Electron. 2014, 61, 6672–6680. [CrossRef]
15. Sandeep, N.; Yaragatti, U.R. A Switched-Capacitor-Based Multilevel Inverter Topology with Reduced Components. IEEE Trans.
Power Electron. 2018, 33, 5538–5542. [CrossRef]
16. Ahmad, A.; Anas, M.; Sarwar, A.; Zaid, M.; Tariq, M.; Ahmad, J.; Beig, A.R. Realization of a Generalized Switched-Capacitor
Multilevel Inverter Topology with Less Switch Requirement. Energies 2020, 13, 1556. [CrossRef]
17. Sathik, M.J.; Vijayakumar, K.; Member, S. Compact Switched Capacitor Multilevel Inverter (CSCMLI) With Self Voltage Balancing
and Boosting Ability. IEEE Trans. Power Electron. 2018, 34, 4009–4013.
18. Tehrani, K.; Weber, M.; Rasoanarivo, I. Hybrid Power System Optimization for Microgrids. In Proceedings of the 2021 23rd
European Conference on Power Electronics and Applications (EPE’21 ECCE Europe), Virtual Conference, Ghent, Belgium, 6–10
September 2021; pp. 1–9.
19. Biswas, M.; Podder, S.; Khan, Z.R. Modified H-bridge multilevel inverter for Photovoltaic micro-grid systems. In Proceedings of
the 2016 9th International Conference on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, 20–22 December
2016; pp. 377–380.
20. Alawieh, H.; Riachy, L.; Tehrani, K.A.; Azzouz, Y.; Dakyo, B. A new dead-time effect elimination method for H-bridge inverters.
In Proceedings of the IECON 2016—42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, 24–27
October 2016; pp. 3153–3159.
21. Abualigah, L.; Yousri, D.; Elaziz, M.A.; Ewees, A.A.; Al-Qaness, M.A.; Gandomi, A.H. Aquila Optimizer: A novel meta-heuristic
optimization algorithm. Comput. Ind. Eng. 2021, 157, 107250. [CrossRef]

View publication stats