Digital Input and Output:

1. What are the valid input voltage ranges for a KL25 MCU with VDD = 3 V? With 2V?

At VDD = 3V:

The minimum input voltage for a logic one (VIH) is 0.7 * 3 V = 2.1 V. There is no maximum specified , so
use the maximum VDIO = 3.6 V. So a one input must be between 2.1 V and 3.6 V.

The maximum input votage for a logic zero (VIL) is 0.35 * 3 V = 1.05 V. There is no minimum specified,

so use the minimum VDIO = -0.3 V. So a zero input must be between -0.3 V and 1.05V.

At VDD = 2V:

The minimum input voltage for a logic one (VIH) is 0.75 * 2 V = 1.5 V. There is no maximum

, so use the maximum VDIO = 3.6 V in section 4.4. So a one input must be between 1.5 V and 3.6 V.

The maximum input votage for a logic zero (VIL) is 0.3 * 2 V = 0.6 V. There is no minimum specified

, so use the minimum VDIO = -0.3 V in section 4.4. So a zero input must be between -0.3 V and 0.6 V.

2. Which digital outputs on the Cortex M0 subfamily support high drive capability? Refer to the MCU’s
data sheet or reference manual.

PTB0, PTB1, PTD6 and PTD7 have a high drive capability.

3. Calculate the resistor values needed to limit current through the blue and red LEDs of MCU, 3 to 18
mA each.

Assume the supply voltage VDD is 3.0 V.

Red: R1 = (VDD-VF)/ILED = (3.0 V – 1.8 V)/18 mA = 66.7 Ω

Blue: R2 = (VDD-VF)/ILED = (3.0 V – 2.7 V)/18 mA = 16.7 Ω

4. Consider a program which uses bits 0 through 5 on Port E as GPIO inputs, and bits 16 through 20 as
GPIO outputs.

a. What control register settings are needed?

Enable clock to Port E. Set PORTE in SIM CGCG5.

Make PORTE bits 0–5 and 16-20 GPIO

Set PORTE PCR to 1 for bits 0–5 and 16-20

Make bits 0–5 inputs by clearing those bits in PTE PDDR

Make bits 16-20 outputs by setting those bits in PTE PDDR

So PORTE->PDDR in binary should be xxxx xxxx xxx1 1111 xxxx xxxx xx00 0000, where x = don’t care

b. Write C code to implement these control register settings.

void gpio(void) {

int i;

// Enable Clock to Port E

SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;

// Make pins GPIO

for (i=0; i<=5; i++) {

PORTE->PCR[i] &= ~PORT_PCR_MUX_MASK;

PORTE->PCR[i] |= PORT_PCR_MUX(1);

for (i=16; i<=20; i++) {

PORTE->PCR[i] &= ~PORT_PCR_MUX_MASK;

PORTE->PCR[i] |= PORT_PCR_MUX(1);

// Configure bits as inputs

for (i=0; i<=5; i++) {

PTE->PDDR &= ~MASK(i);

// Configure bits as outputs

for (i=16; i<=20; i++) {

PTE->PDDR |= MASK(i);

}
ARM cortex M0 and Interrupts:

1. How does the word 0xdec0ded1 appear in memory in a little-endian memory system? And in a
big-endian memory system? Specify the relative address for each byte.

2. Does the stack in ARM processors grow toward larger or smaller addresses?

Smaller addresses

3. Assuming that SP is 0x0000_2220 initially, what is its value after executing the instruction PUSH
{r0,r2}?

Two registers are pushed, so 8 bytes are used. The new SP value is 0x0000_2218.

4. Assuming that SP is 0x0000_2010 initially, what is its value after executing the instruction POP {r0-
r7,PC}?

Nine registers are popped, so 36 bytes are used. 36 in hexadecimal is 0x24. The new SP value is
0x0000_2034.

5. We would like to configure a KL25Z MCU so that if interrupts IRQ0, IRQ10 and IRQ31 are requested

simultaneously, the CPU responds by servicing IRQ10 first, then IRQ0, and finally IRQ31. Write the C
code using CMSIS functions to configure the MCU.
NVIC_SetPriority(DMA0_IRQn, 0);

NVIC_SetPriority(SPI0_IRQn, 1);

NVIC_SetPriority(PORTD_IRQn, 2);

Other settings are possible: 0,1,3; 0,2,3; 1,2,3.

6. We wish to enable IRQ13 but disable IRQ24. What value needs to be loaded into which register bits,
and what is the CMSIS code call to accomplish the same?

Write 1<<13 to NVIC_ISER

Write 1<<24 to NVIC_ICER

NVIC_EnableIRQ(UART1_IRQn)

NVIC_DisableIRQ(USB0_IRQn)
Analog Interfacing:

For all of these questions, assume the KL25Z peripherals are used unless specified otherwise.

1. Consider a 12-bit ADC with a reference voltage of 3.3 V operating in single-ended mode. Given an
input voltage of 0.92 V, what will the output code be?

n = round( (0.92 V/ 3.3 V)*212) = round (1141.92) = 1142

2. Consider an 8-bit ADC with a reference voltage of 2.7 V operating in single-ended mode. What input
voltage range will lead to an output code of 0x34?

Center of voltage range = (0x34/256) * (2.7 V) = (52/256)*2.7V = 0.548438 V

Upper end of voltage range = 0.548438 V + 2.7 V/(256*2) = 0.553711 V

Lower end of voltage range = 0.548438 V - 2.7 V/(256*2) = 0.543164 V

3. Consider a 12-bit ADC with an unknown reference voltage operating in single-ended mode. What is
the reference voltage if sampling the 1.0V band gap reference results in a code of 0x513?

n = 0x513 = 1299 = round((1.0V/VRef) *212))

Vref = 1.0V/1299 * 212 = 3.15319 V

4. Consider a 12-bit ADC with a reference voltage of 3.3 V operating in single-ended mode. If it samples
the internal temperature sensor and reads a voltage of 0.621 V, what is the temperature? Assume
VTemp25=719 mV and m = 1.175 mV/°C.

T = (0.621 V – 0.719 V)/(1.175 mV/⁰C) + 25 ⁰C = -58.40 ⁰C

5. Consider a 12-bit DAC with a reference voltage of 3.3 V. What input code will result in an output of
1.43 V?

No code will result in precisely that voltage. However, the closest input code is 1774, which will produce
an output of (1774 + 1)/4096*3.3V = 1.430054 V, with an error of 54 µV.

6. Consider a 10-bit DAC with a reference voltage of 2.7 V. Given that the input code is 0x104, what is
the output voltage?

The output voltage is (0x104+1/210)*2.7 V = (261/210)*2.7 V = 0.68818 V

7. What is the output voltage resolution of an 8-bit DAC with a reference voltage of 3.0 V?

3.0 V/28 = 11.72 mV

Serial Communication:

1. Assume (Signal Multiplexing and Signal Descriptions) of the KL25 Sub-Family Reference Manual to determine
the answers to the following questions. Assume that an MCU in an 80 QFP package is used.
a. Which port bits can be used for SPI0?

PTA14, PTA15, PTA16, PTA17, PTC4, PTC5, PTC6, PTC7, PTD0, PTD1, PTD2, PTD3

b. Which port bits can be used for SPI1?

PTE1, PTE2, PTE3, PTE4, PTB10, PTB11, PTB16, PTB17, PTD4, PTD5, PTD6, PTD7

2. Show the register settings needed to configure SPI0 to operate as a master at 12 MHz, eight data bits (MSB
first), SPI mode 0 (Clock Phase CPHA = 0, Clock Polarity CPOL = 0). Assume the bus clock is 24 MHz. Enable
interrupts for transmission, reception and errors. Use the /SS pin as a slave select output.

SIM_SCGC4:
SPI0 = 1

SPI0_C1:
SPIE = 1
SPE = 1
SPTIE = 1
MSTR = 1
CPOL = 0
CPHA = 0
SSOE = 1
LSBFE = 0

SPI0_C2:
SPMIE = 0 (not explicitly specified, but assume not used)
SPLPIE = 0 (not explicitly specified, but assume not used)
TXDMAE = 0 (not explicitly specified, but assume not used)
MODFEN = 1
BIDIROE = 0 or 1 (doesn’t matter)
RXDMAE = 0 (not explicitly specified, but assume not used)
SPISWAI = 0 or 1 (doesn’t matter)
SPC0 = 0

SPI0_BR:
24 MHz/12 MHz = division factor of 2
Prescaler divisor of 1: SPPR=000
Divisor of 2: SPR = 0000

3. Draw a timing diagram showing the bytes 0x31 0xF1 being transmitted by SPI at 1,000,000 baud, with SPI
mode 0. Indicate the time of each signal transition.

Use definition of SPI Mode 0 from above: Clock Phase CPHA = 0, Clock Polarity CPOL = 0
 MSB or LSB first is not specified, so we’ll pick MSB first.
0x31 0xF1 = 0011 0001 1111 0001
SPSCK

MOSI
Time (µs) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16

4. Assume (Signal Multiplexing and Signal Descriptions) of the KL25 Sub-Family Reference Manual to determine
the answers to the following questions. Assume that an MCU in an 80 QFP package is used.
a. Which port bits can be used for UART0?

PTE20, PTE21, PTA1, PTA2, PTA14, PTA15, PTB16, PTB17, PTD6, PTD7

b. Which port bits can be used for UART1?

PTE0, PTE1, PTA18, PTA19, PTC3, PTC4

c. Which port bits can be used for UART2?

PTE22, PTE23, PTD2, PTD3, PTD4, PTD5

5. Show the register settings needed to configure UART 1 to transmit and receive at 71433 baud, eight data bits
(LSB first), one stop bit and odd parity. Assume the bus clock is 24 MHz. Enable interrupts to indicate that the
transmit data register is empty, the receive data register is full, or any error has occurred. The UART should
not trigger any DMA activity.

SIM_SCGC5
UART1 = 1

UART1_C1
LOOPS = 0
UARTSWAI = 0 or 1, not specified
RSRC = 0 or 1, doesn’t matter
M=0
WAKE = 0 or 1, not specified
ILT = 0 or 1, not specified
PE = 1
PT = 1

UART1_C2
TIE = 1
TCIE = 0
RIE = 1
ILIE = 0
TE = 1
RE = 1
RWU = 0
SBK = 0
 UART1_C3
T8 = 0 or 1, doesn’t matter
TXDIR = 0 or 1, doesn’t matter
TXINV = 0
ORIE = 1
NEIE = 1
FEIE = 1
PEIE = 1

UART1_C4
TDMAS = 0
TCDMAS = 0
RDMAS = 0
ILDMAS = 0 or 1, doesn’t matter
LBKDDMAS = 0
Baud rate of 71433 baud with 24 MHz bus clock. Baud rate = 24 MHz/(SBR*16). UART1 has fixed oversampling
rate of 16. SBR = 24 MHz/(16*71433 Hz) = round(20.9987) = 21 = 0x015

UART1_BDH
LBKDIE = 0
RXEDGIE = 0
SBNS = 0
SBR = 0x0 (bits 13-8 of 0x015)

UART1_BDL
SBR = 0x15 (bits 7-0 of 0x015)

6. Assume a UART has both TIE and TCIE set to one and a program writes a byte to the UART D register for
transmission. Which interrupts will occur, and when?

A UART Transmit interrupt will occur once the data has been transferred from the transmit data buffer to the
transmit shifter. This is indicated by TDRE being set to one by the UART hardware.
Another UART Transmit interrupt will occur after the UART has finished transmitting the data. This is indicated
by TC being set to one by the UART hardware.

7. Draw a timing diagram showing the bytes 0x31 0xF1 being transmitted by a UART at 115200 baud, with LSB
first, odd parity and one stop bit. Indicate the time of each signal transition.

0x31 = 0011 0001

LSB First: 1000 1100
Parity bit: 0

0xF1 = 1111 0001

LSB First: 1000 1111
Parity bit: 0
Data
Time (µs) 0 8.7 17.4 26 34.7 43.4 52.1 60.8 69.4 78.1 86.8 95.5 104.2 112.8 121.5 130.2 138.9 147.6 156.3 164.9 173.6 182.3

Start b0 b1 b2 b3 b4 b5 b6 b7 Parity Stop Start b0 b1 b2 b3 b4 b5 b6 b7 Parity Stop

8. Assume (Signal Multiplexing and Signal Descriptions) of the KL25 Sub-Family Reference Manual to
determine the answers to the following questions. Assume that an MCU in an 80 QFP package is used.
a. Which port bits can be used for I2C0?

PTE24, PTE25, PTB0, PTB1, PTB2, PTB3, PTC8, PTC9

b. Which port bits can be used for I2C1?

PTE0, PTE1, PTA3, PTA4, PTC1, PTC2, PTC10, PTC11

9. Show the register settings needed to configure I2C1 to communicate at approximately 800 kbaud. Assume the
bus clock is 24 MHz. What is the actual communication frequency?

See Section 38.3.2 and Table 38-41 in KL25 Subfamily Reference Manual.
I2C baud rate = 24 MHz/(mul * SCL divider)
For mul = 1, SCL divider = 24 MHz/800 kHz = 30.

I2C1_F
MULT = 0 (to get mul value of 1)
ICR = 0x05 (to get SCL divider value of 30)

Since the precise divider value of 30 is available, we expect the actual communication frequency to be 800
kbaud for a 24 MHz bus clock.

10. Draw a timing diagram of the following I2C message: a value of 0x31 being written to device 0x36 register
0x55. Assume 200 kbaud communications speed. Indicate the time of each signal transition.

0x31 = 0011 0001

0x36 = 0011 1100
0x55 = 0101 0101

SCL
SDA
Time (µs) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 ### ### ### ### ### ### ### ### 140 145
Note MSB 6 5 4 3 2 1 LSB ACK MSB 6 5 4 3 2 1 LSB ACK MSB 6 5 4 3 2 1 LSB ACK
Sta rt Devi ce 0x36 (0011 0110) + Wri te Regi s ter 0x55 (0101 0101) Da ta 0x31 (0011 0001) Stop
MCQ on ARM architecture and Lowpower features:

1. The following are examples of ARM processor series (choose multiple):

A. SecureCore
B. Cortex-A
C. Cortex-R
D. Cortex-M

2. Which processor series is more suited for low power, low cost applications in energy
efficient embedded devices? (choose one):
A. SecureCore
B. Cortex-A
C. Cortex-R
D. Cortex-M

3. The following are some of the features supported by the Cortex-M7 processor (choose
multiple):
A. Debug
B. Sleep modes (WFI, WFE)
C. Interrupts
D. Bus Interconnect
4. Which component of the Cortex-M7 processor is used to achieve low latency interrupt
processing? (choose one):
A. Bus Interconnect
B. Nested Vectored Interrupt Controller (NVIC)
C. Wakeup Interrupt Controller (WIC)
D. Memory Protection Unit (optional)

5. How many pipeline stages are in the Cortex-M7 processor? (choose one):
A. 6
B. 2
C. 3
D. 4

6. Which register is used to save the current address of the stack (context of a program
while switching between tasks)? (choose one):
A. Link register
B. Stack Pointer
C. Program status registers
D. CONTROL register
7. Which register is used to record the address of the current instruction code? (choose
one):
A. Link register
B. Stack Pointer
C. Program Counter
 D. CONTROL register
8. How much addressable memory is available in the Cortex-M7 processor? (choose
multiple):
A. 1GB
B. 2GB
C. 6GB
D. 4GB

9. Which region of the memory map is primarily used for program code? (choose one):
A. External RAM
B. Code
C. Peripheral
D. SRAM

10. Which memory region is primarily used to store data such as heaps and stacks? (choose
one):
A. External RAM
B. Code
C. Peripheral
D. SRAM

11. Which memory region is primarily used to map external devices? (choose one):
A. External RAM
B. Code
C. Peripheral
D. External Device Region

12. When the lowest byte of a word-size is stored in bit 0 to bit 7, this is known as: (choose
one):
A. Little endian
B. Big endian

13. Which of the following is a source of interrupt (choose one):

A. Hardware
B. Exceptions
C. Software
D. All the above

14. When the processor receives an interrupt which subroutine is executed? (choose one):
A. Maskable interrupts
B. Interrupt Service Routine (ISR)
C. Exceptions
D. All the above
 15. The Cortex-M7 processor supports which of the following modes of operation? (choose
two):
A. Debug
B. Thread
C. Thumb
D. Handler

16. The Cortex-M7 processor enters which mode on reset or when returned from an
exception? (choose one):
A. Debug
B. Thread
C. Thumb
D. Handler

17. Privileged and unprivileged codes and run in the following mode (choose one):
A. Debug
B. Thread
C. Thumb
D. Handler

18. Which stack pointer is always used in handler mode? (choose one):
A. Main Stack Pointer
B. Process Stack Pointer

19. A section of code that creates a possible race condition is called? (choose one):
A. Race
B. Critical

Answer Keys:

1 A, B,C,D 11 D
2 D 12 A
3 A,B,C,D 13 D
4 B 14 B
5 A 15 B,D
6 B 16 B
7 C 17 B
8 D 18 A
9 C 19 B
10 D