electronics
Article
Design and Validation of a V-Gate n-MOSFET-Based RH
CMOS Logic Circuit with Tolerance to the TID Effect
Donghan Ki 1,2 , Minwoong Lee 1 , Namho Lee 1 and Seongik Cho 2, *
Citation: Ki, D.; Lee, M.; Lee, N.; Cho,
S. Design and Validation of a V-Gate
n-MOSFET-Based RH CMOS Logic
Circuit with Tolerance to the TID
Effect. Electronics 2023, 12, 3331.
https://doi.org/10.3390/
electronics12153331
Academic Editor: Laurent Artola
Received: 20 June 2023
Revised: 1 August 2023
Accepted: 2 August 2023
Published: 3 August 2023
Copyright: © 2023 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Electronics 2023, 12, 3331. https://doi.org/10.3390/electronics12153331
1 Korea Atomic Energy Research Institute, Jeongeup 56212, Republic of Korea; dhki07@kaeri.re.kr (D.K.);
minwoong@kaeri.re.kr (M.L.); nhlee@kaeri.re.kr (N.L.)
2 Department of Electronic Engineering, Jeonbuk National University, Jeonju 54896, Republic of Korea
* Correspondence: sicho@jbnu.ac.kr; Tel.: +82-63-270-4137
Abstract: This study designed a radiation-hardened (RH) complementary metal oxide semiconductor
(CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the
total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS
logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing
layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted
the radiation damage using modeling and simulation techniques and validated the tolerance by
conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS
logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total
cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility.
Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the
TID effect was validated through experiments.
Keywords: layout modification; radiation tolerance; total ionizing dose effect; logic gate; modeling
and simulation
1. Introduction
The logic circuit is the fundamental unit in semiconductor-based electronic devices
used in radiation environments, such as the online monitoring systems of nuclear power
plants, field-programmable gate arrays (FPGAs) [1], digital signal processors (DSPs) [2],
and aerospace memory integrated circuits. These devices perform various functions, such
as charge pump circuits, power management circuits, and I/O ports [3]. Logic circuits,
which comprise a complementary metal oxide semiconductor (CMOS), are susceptible to
cumulative radiation effects known as total ionizing dose (TID) effects, which can lead to
data conversion errors, timing issues, and increased power consumption [2–6]. Therefore,
a radiation-hardened design of the fundamental unit of electronic devices, that is, the logic
circuit, is crucial. Furthermore, by ensuring radiation hardness at the basic unit circuit level,
radiation-hardened designs for complex system-level circuits can be achieved.
When constructing CMOS logic circuits in sub-micron processes, p-MOSFETs are un-
affected by TID effects. However, n-MOSFETs experience TID effects and generate trapped
charges in the shallow trench isolation (STI) oxide, leading to leakage currents [7]. Re-
cently, significant research has been conducted on layout modification techniques targeting
n-MOSFETs, which are particularly susceptible to TID effects. The layout modification
technique resists the TID effect by simply changing the layout of a unit MOSFET while
using an existing commercial process. This technique does not require an additional process
because the existing commercial process can be used without modification. The ELT, DGA,
L Style, and I-gate structures are representative examples of MOSFET structures with layout
transformation techniques [8–14]. Among them, the RH variable-gate n-MOSFET, which
is minimized in terms of its speed and area, provides various structural advantages to
the design of RH circuits, considering that it can efficiently connect the electrodes of each
https://www.mdpi.com/journal/electronics
Electronics 2023, 12, 3331 2 of 12

device in the construction of a semiconductor integrated circuit (IC) [15]. Therefore, this
study proposes an RH CMOS logic circuit that is constructed using n-MOSFETs with such
structures, along with conventional p-MOSFETs. The RH CMOS logic circuit is predicted
in advance for radiation damage through modeling and simulation techniques and is
implemented as an actual chip through a 0.18 µm CMOS process. Furthermore, we perform
a radiation exposure test with a cumulative radiation dose of a total of 25 kGy to validate
the radiation tolerance of the implemented chip. The remainder of this paper is structured
as follows: Section 2 introduces the proposed RH CMOS logic circuit and performs the
modeling and simulation of the proposed RH CMOS logic circuit. Section 3 describes the
chip implementation and experimental results of the proposed RH CMOS logic circuit.
Finally, Section 4 presents the conclusion.

2. Proposed RH CMOS Logic Circuits

The main damage to the TID effect of CMOS logic circuits is caused by the leakage
current, owing to the fixed charge generated in the isolation oxide of the n-MOSFET.
Therefore, the fixed charge generated from the isolated oxide of the n-MOSFET should
be reduced in an RH design of a CMOS logic circuit. This study proposes an RH CMOS
logic circuit structure using an RH variable gate (V-gate) n-MOSFET [15] and standard
p-MOSFET to prevent these fixed charges. In this section, we describe the RH V-gate
n-MOSFET resistant to TID effects and the proposed RH CMOS logic circuit structure.
Subsequently, the RH CMOS logic circuit based on the RH V-gate n-MOSFET is modeled
in a 3D structure using a technology computer-aided design (TCAD) tool. The modeled
RH CMOS logic circuit simulates the damage caused by the TID effect and the results are
analyzed and compared with the damage to a standard CMOS logic circuit.

2.1. Introduction to the RH CMOS Logic Circuit

Figure 1 shows the basic configuration of the proposed RH CMOS logic circuit. The
n-MOSFET and p-MOSFET in the CMOS are implemented as an RH V-gate n-MOSFET
and Standard p-MOSFET, respectively. A-A0 show respective cross-sectional views. When
radiation is incident on a CMOS, it undergoes the following four physical processes. First, it
forms electron–hole pairs in the oxide layer. Electrons with a high mobility quickly escape
the oxide layer, leaving holes with a slower mobility trapped inside the bandgap of the oxide
layer. Second, the remaining holes trapped inside the bandgap move toward the silicon–
oxide interface. Third, some of the holes get captured by Strained-Si bonds, owing to lattice
mismatch, thereby generating fixed charges. Finally, charge carriers are induced by these
fixed charges and accumulate. As a result, for n-MOSFETs, the Vth voltage decreases and
the leakage current increases due to the fixed charges created in the gate oxide. Conversely,
for p-MOSFETs, the Vth voltage increases due to the fixed charges in the gate oxide [16,17].
However, in the current sub-micron processes, where the gate oxide thickness is less than
10 nm, holes are not trapped in the gate oxide, but only in the STI oxide [17]. Therefore,
for n-MOSFETs, the Vth voltage remains unchanged, owing to the TID effects; however, a
leakage current occurs as a result of the accumulated holes in the STI oxide. For p-MOSFETs,
the Vth voltage and leakage current do not change due to the TID effect; however, the
drain current decreases due to radiation-induced short-channel effects [18]. This drain
current reduction is almost negligible for the sizes of the p-MOSFETs used in logic circuits,
and the p-MOSFETs used in CMOS logic circuits are relatively insensitive to TID effects.
Therefore, by using a radiation-hardened (RH) n-MOSFET and standard p-MOSFET, an
RH CMOS logic circuit can be constructed. In this study, a V-gate n-MOSFET was used
as the RH n-MOSFET, which incorporates V-gate poly, P+ doping, and P-active layers to
minimize the effects of the radiation-induced fixed charges present in the insulating oxide
layer compared to the standard n-MOSFET, as shown in Figure 1. Through the V-gate poly,
the leakage current path between the drain and source was blocked by replacing the thick
STI oxide with a thin gate oxide on the drain and source sides. The threshold voltage was
increased to prevent channel inversion caused by the fixed charges trapped in the silicon
 replacing the thick STI oxide with a thin gate oxide on the drain and source sides. The
threshold voltage was increased to prevent channel inversion caused by the fixed charges
trapped
Electronics 2023, 12,in the silicon oxide and the generation of a leakage current by adding P+ doping
3331 3 of 12
and a P-active layer. Compared to the existing ELT, DGA, and I-gate layouts, it was mini-
mized in terms of speed and area. By utilizing these principles, various structural ad-
vantages can be provided oxide and
whenthe generation
configuring of a CMOS
leakage current by adding
logic circuits P+ doping
with more and a P-active
efficient layer.
elec-
Compared to the existing ELT, DGA, and I-gate layouts, it was minimized in terms of speed
trode connections ofand n-MOSFETs and p-MOSFETs, by adjusting the gate poly, p+, and p-
area. By utilizing these principles, various structural advantages can be provided when
active layer in various forms such
configuring CMOSas ancircuits
logic I-shape,
withL-shape, C-shape,
more efficient electrodeand Z-shape.
connections Addi-
of n-MOSFETs
tionally, the channel size (W/L) of the device can be changed by adjusting the size of thesuch
and p-MOSFETs, by adjusting the gate poly, p+, and p-active layer in various forms
RH layer. Therefore,asradiationan I-shape, L-shape, C-shape, and Z-shape. Additionally, the channel size (W/L) of the
damage can be prevented regardless of the device size
device can be changed by adjusting the size of the RH layer. Therefore, radiation damage
[11,15,19]. Unlike ELT and
can DGA n-MOSFETs,
be prevented thedevice
regardless of the W/Lsize
ratio of V-gate
[11,15,19]. n-MOSFETs
Unlike ELT and DGAremains
n-MOSFETs,
unchanged; therefore, thethe
W/L W/Lratiosize ration-MOSFETs
of V-gate must not remains
be modified and therefore,
unchanged; process the validation
W/L size is ratio
must not be modified and process validation is possible
possible during circuit design. Moreover, the V-gate poly-layer serves as a silicide-block- during circuit design. Moreover,
the V-gate poly-layer serves as a silicide-blocking layer to prevent band-to-band tunneling
ing layer to prevent band-to-band tunneling between the n+ and p+ layers. Owing to these
between the n+ and p+ layers. Owing to these advantages, the RH V-gate n-MOSFET and
advantages, the RH V-gate standardn-MOSFET
p-MOSFET can and standard
be used p-MOSFET
as the basic components canto be used
design ascircuits
logic the basic
such as
components to design logic
CMOS circuits
INV, NAND,such NORas CMOS
gates, INV, NAND, NOR gates, and others.
and others.

Figure 1. Basic configuration of the proposed RH CMOS logic circuit.

Figure 1. Basic configuration of the proposed RH CMOS logic circuit.
2.2. V-Gate n-MOSFET-Based CMOS Logic Circuit Modeling and Simulation
2.2. V-Gate n-MOSFET-Based CMOScharacteristics
The damage Logic CircuitofModeling andcan
the TID effect Simulation
be determined via irradiation ex-
periments by designing a circuit and fabricating it into a chip. However, the process of
The damage characteristics of the TID
conducting an irradiation effect can
experiment becircuit
after determined
design and via irradiation
chip fabrication isexper-
expensive
iments by designingand a circuit and fabricating
time consuming, it into
and radiation safetyahazards
chip. However, the
are possible. In process
contrast, if theofTID
con-
effects
in semiconductors are modeled and simulated using software,
ducting an irradiation experiment after circuit design and chip fabrication is expensive the damage characteristics
can be efficiently assessed without requiring extensive experimental testing. Consequently,
and time consuming,the and radiation safety hazards are possible. In contrast, if the TID ef-
damage characteristics of the TID effect in the V-gate n-MOSFET-based CMOS logic
fects in semiconductors are
circuit modeled
were evaluatedand
usingsimulated
a TCAD tool. using software,
Furthermore, the
it was damage
modeled charac-
according to the
teristics can be efficiently assessed
procedure shownwithout requiring
in Figure 2, extensive
and the simulation experimental
results were analyzed. testing. Con-
sequently, the damage characteristics of the TID effect in the V-gate n-MOSFET-based
CMOS logic circuit were evaluated using a TCAD tool. Furthermore, it was modeled ac-
cording to the procedure shown in Figure 2, and the simulation results were analyzed.
 Electronics 2023, 12, x FOR PEER REVIEW 4 of 13
Electronics 2023, 12, x FOR PEER REVIEW 4 of 13
Electronics 2023, 12, 3331 4 of 12

Figure 2. Modeling sequence of the TID effect.

Modelingsequence
Figure2.2.Modeling
Figure sequenceof
ofthe
theTID
TIDeffect.
effect.
To model
To model the the TID
TID effect
effect usingusing the
the TCAD
TCAD tool, tool, aa V-gate
V-gate n-MOSFET-based
n-MOSFET-based CMOS CMOS logic logic
To model
circuit was themodeled
first TID effect in using
a 3D the TCAD and
structure tool,itsa V-gate
function n-MOSFET-based
was subsequently CMOS logic
validated
circuit was first modeled in a 3D structure and its function was subsequently validated
circuit
through was first modeled Theincharacteristics
a 3D structureofand its
TIDfunction was evaluated
subsequently validated
through aa simulation.
simulation. The characteristics theTID
of the effectwere
effect were evaluated through through simu-
simula-
through
lations a simulation.
after modeling The
the characteristics
fixed charge of the TID
generated by effect
the were
TID evaluated
effect through through
ion simu-
implanta-
tions after modeling the fixed charge generated by the TID effect through ion implantation.
lations after modeling the fixed charge generated by the TID effect through ion implanta-
tion. First, each RH CMOS logic circuit was modeled as a 3D structure, as shown in Figure 3.
tion. First, each RH CMOS logic circuit was modeled as a 3D structure, as shown in Figure
The NOT, NAND, and NOR gates are shown in Figure 3a,b, respectively. As shown in
3. The
Figure First,
3b,each
NOT, RHbe
it NAND,
can CMOS and NOR
either logic circuit
a NAND wasshown
gates gate
are modeled
or a NOR asgate
in Figurea 3D3a,b,structure, as
onshown
respectively.
depending theAs in Figure
shown
metal in
inter-
3.connections.
The NOT,
Figure 3b, itNAND,can be and
either NORa gates
NAND are
gate shown
or a NOR in Figure
gate
The donor and acceptor concentrations of the RH V-gate n-MOSFET and 3a,b,
depending respectively.
on the As
metal shown
intercon- in
Figure
nections.
standard 3b, p-MOSFET
it can
The be either
donor and
used a inNAND
acceptor or a NOR
gatecircuit
concentrations
the logic are ofgate
thedepending
shown RH V-gate on
in Figure therespectively.
n-MOSFET
3c,d, metaland intercon-
stand-
The
nections.
ard p-MOSFET
TID The donor
effect in theused CMOSand acceptor
in mainly
the logic concentrations
circuitfrom
results are shown of the
the leakage RH
in Figure V-gate
current 3c,d, n-MOSFET
thatrespectively. and
occurs between stand-
The TIDthe
ard
effect
drain p-MOSFET
in the
and the CMOS usedmainly
source in
of the logic
the results circuit
n-MOSFET.from the are leakage
shown suppose
Therefore, in Figurethat
current 3c,d,
that therespectively.
occurs between
leakage The TID
the drain
current path
effect
and the
between in the theCMOS
source of mainly
drain the
andn-MOSFET.
the results
sourcefrom the leakage
Therefore,
of the suppose
n-MOSFET current that
is that
theoccurs
blocked. leakage between
Then, current the
the CMOS drain
path be-
and
tween the source
the drain of the
and n-MOSFET.
the source of Therefore,
the n-MOSFET suppose is
comes resistant to the TID effect. Using the aforementioned principle, RH CMOS logic that
blocked. the leakage
Then, the current
CMOS path
becomesbe-
tween
resistant
circuits the drain
to
(NOT, and effect.
theNAND,
TID theand sourceUsing
NOR of the
theaforementioned
gates) n-MOSFET is blocked.
were constructed principle,
usingThen,
RHRHtheCMOS CMOS
V-gate logicbecomes
circuits
n-MOSFETs.
resistant
(NOT,
The channelto
NAND, the TID
sizeand effect.
NOR
of the Using
RHgates)V-gate the
were aforementioned
constructed
n-MOSFET usedusing principle,
in theRH RHV-gate RH CMOS
CMOSn-MOSFETs. logic
logic circuit was circuits
The chan-
set to
(NOT,
2nel size
µm/0.5 NAND,
of µmthe RH andV-gate
(W/L),NOR thegates)
gate were
n-MOSFET oxideconstructed
used in the was
thickness RHusing 6.7RH
CMOS nm, V-gate
logic n-MOSFETs.
andcircuit
the The
was thickness
body set to chan-
2 µm/0.5
was
nel
3µm size
µm. of the
(W/L),
The theRH
doping V-gate
gate oxide n-MOSFET
concentrationsthicknessof used
thein
was 6.7thenm,RHand
substrate CMOS
and the logic
bodycircuit
channel werewas
thickness 2 ×wasset
1016to3/cm
2µm.
µm/0.5
3 and
The
µm ×(W/L),
2doping /cm the3 ,gate
1016concentrations oxide
respectively,of thickness
the was
substrate
whereas 6.7
theand nm,
doping and
channel the
were
concentration body
2 × thickness
10 was23drain,
/cmsource,
of16the 3 and ×µm. The
1016/cmand3,
doping
body concentrations
was
respectively, 1018 /cmthe
3 ×whereas of3 . the
In substrate
the
doping case ofand
thechannel
concentration standard
of thewere 2 × 10drain,
p-MOSFET,
source, 16/cm3 and 2 × 1016/cm3,
theandchannel
bodysize waswas 3×
respectively,
set
10 to
18 /cm4 .µm/0.5
3 whereas
In the case µm of the
(W/L), doping concentration
and thep-MOSFET,
the standard gate oxide,the of the
body source,
thickness,
channel drain,
size was and
substrate body
set to 4doping was
µm/0.5con- 3µm×
10 18/cm3. In the case of the standard p-MOSFET, the channel size was set to 4 µm/0.5 µm
centration,
(W/L), and channel doping
gate oxide, body concentration,
thickness, substratesource,doping drain, concentration,
and body doping channel concentra-
doping
(W/L),
tion and the
were
concentration, thegatesame oxide,
source, asdrain,bodyand
those thickness,
of thebody substrate
n-MOSFET.
doping doping
The n-well
concentration concentration,
doping
were the channel
concentration
same doping
as those wasof
1018 /cm3 . source,
concentration,
× n-MOSFET.
3the The drain,doping
Thecharacteristics
n-well and body thedoping
ofconcentration
modeled concentration
n-MOSFET
was 3 × 1018and were . the
Thesame
/cm3p-MOSFET as those
refer
characteristics ofof
to the
the
then-MOSFET.
CMOS 180 nm
modeled The n-well
process.
n-MOSFET and doping
p-MOSFETconcentration
refer to the wasCMOS 3 × 1018 /cmnm
180 3. The characteristics of
process.
the modeled n-MOSFET and p-MOSFET refer to the CMOS 180 nm process.

Figure 3. Three-dimensional structural modeling of a V-gate n-MOSFET-based RH CMOS logic

Figure 3. Three-dimensional structural modeling of a V-gate n-MOSFET-based RH CMOS logic cir-
circuit.
Figure 3.(a)
cuit. (a) NOT gate,
(b)(b)
Three-dimensional
NOT gate, NAND(NOR) gate,(c)(c)donor
structuralgate,
NAND(NOR) modeling donor concentration,
of aconcentration,
V-gate and(d)
(d)acceptor
n-MOSFET-based
and acceptor
RH CMOSconcentration.
logic cir-
concentration.
cuit. (a) NOT gate, (b) NAND(NOR) gate, (c) donor concentration, and (d) acceptor concentration.
To validate the functioning of the 3D-modeled RH CMOS logic circuit, the operating
characteristics were checked with respect to time through a circuit simulation, as shown in
Figure 4. For the NOT gate, an inverted output was obtained according to the input pulse.
Electronics 2023, 12, x FOR PEER REVIEW 5 of 13

Electronics 2023, 12, 3331 To validate the functioning of the 3D-modeled RH CMOS logic circuit, the operating 5 of 12
characteristics were checked with respect to time through a circuit simulation, as shown
in Figure 4. For the NOT gate, an inverted output was obtained according to the input
pulse.
In the In theofcase
case theof the NAND
NAND gate, gate,
logiclogic “0” was
“0” was output
output whenwhenthe the
twotwo inputs
inputs werewere high.
high. In
In
thethe case
case of of
thethe NOR
NOR gate,logic
gate, logic“1”
“1”waswasoutput
outputwhen
whenthe
thetwo
two inputs
inputs were were low.
low. The RH RH
CMOS
CMOS logic
logic circuit,
circuit, which
which was
was modeled
modeled and and validated
validated for
for the
the operating
operating characteristics,
characteristics,
was
was compared
compared and and analyzed
analyzed with
with aa standard
standard CMOS
CMOS logic
logic circuit
circuit to to validate
validate its
its effect
effect on
on
TID. Figure 5 shows the modeling of the the fixed
fixed charge
charge generated in the oxide layer layer of of each
each
n-MOSFET by the
n-MOSFET the TID
TID effect
effect using
using the
the cutoff
cutoff depth method [20]. The The modeling
modeling of of the
the TID
TID
effect of
effect of the
the standard
standard CMOS
CMOS logiclogic circuit
circuit and
and RH
RH CMOS
CMOS logic
logic are
are shown
shown in in Figure
Figure 5a,b,
5a,b,
respectively. A-A0 and
respectively. A-A′ B-B0 show
and B-B′ show respective
respective cross-sectional
cross-sectional views.
views. Currently,
Currently, thethe doping
doping
concentration of
concentration of the fixed charge injected into the oxide is 3 ××10 101818/cm
/cm3. 3 .

Electronics 2023, 12, x FOR PEER REVIEW 6 of 13

Figure 4.
Figure Operating characteristics
4. Operating characteristics of
of the
the RH
RH CMOS
CMOS logic
logic gate.
gate.

Figure 5. ModelingFigure
of the5. TID effectofof
Modeling the(a)
TIDa effect
standard
of (a) CMOS logic
a standard circuit,
CMOS logic and (b)and
circuit, an(b)
RH anCMOS
RH CMOS logic
logic circuit. circuit.

The damage characteristics owing to the TID effect of the standard and RH CMOS
logic circuits were validated through circuit simulations, as shown in Figure 6. In the sim-
ulation, the standard CMOS NOT gate output of logic “1” decreased from 3.3 V to 2.51 V,
the NAND gate decreased from 3.3 V to 2.22 V, and the NOR gate decreased from 3.3 V
to 1.96 V, owing to the TID effect. However, unlike the standard CMOS logic circuit, the
Electronics 2023, 12, 3331 Figure 5. Modeling of the TID effect of (a) a standard CMOS logic circuit, and (b) an RH CMOS 6logic
of 12
circuit.

The
The damage
damage characteristics
characteristicsowing
owingto tothe
theTID
TIDeffect
effect of
of the
the standard
standard and
and RH
RH CMOS
CMOS
logic circuits were validated through circuit simulations, as shown
logic circuits were validated through circuit simulations, as shown in Figure 6. in Figure 6. In theInsim-
the
ulation, the standard
simulation, CMOS
the standard CMOSNOT NOT
gate output of logic
gate output of“1” decreased
logic from 3.3
“1” decreased V to3.3
from 2.51V V,
to
the
2.51NAND gate decreased
V, the NAND from 3.3from
gate decreased V to3.32.22 V, 2.22
V to and V,theand
NORthegate
NORdecreased from 3.3
gate decreased fromV
to
3.31.96
V toV,1.96
owing to theto
V, owing TID
theeffect. However,
TID effect. unlike
However, the standard
unlike CMOS
the standard logiclogic
CMOS circuit, the
circuit,
RH CMOS
the RH CMOSlogic circuit
logic was
circuit wasvalidated
validated to to
have
haveradiation
radiationresistance
resistancecharacteristics
characteristics that
that
showed
showedthe thesame
same results
results as
as those
those before
before the
the damage.
damage.

Figure6.
Figure TIDdamage
6.TID damagecharacteristics
characteristicsof
ofthe
thestandard
standard and
and RH
RH CMOS
CMOS logic
logic circuits.
circuits.

3. Chip Implementation and Experimental Results of RH CMOS Logic Circuit

For the RH CMOS logic circuit using the RH V-gate n-MOSFET, the damage to the
TID effect was predicted in advance through modeling and simulation. In this section, the
RH CMOS logic circuit was designed as an IC chip using KEY FOUNDRY’s 0.18 µm (STI)
CMOS process to validate the actual damage characteristics of the TID effect. Additionally,
the simulation results for the damage were obtained by modeling the leakage current flow
owing to the TID effect. The circuit and IC chip were designed using the Cadence’s Specter
and Virtuoso tools, which can be used to design circuits with process devices, create layouts,
and can be validated. Subsequently, the operating characteristics of the fabricated chip were
validated and an actual radiation experiment was conducted at the high-level radiation
irradiation facility of the Korea Institute of Advanced Radiation Technology (ARTI). Finally,
the radiation tolerance characteristics of the V-gate n-MOSFET-based CMOS logic circuit
were validated.

3.1. Chip Implementation of the RH CMOS Logic Circuit

Two circuits were designed using KEY FOUNDRY’s 0.18 µm (STI) CMOS process to
compare and analyze the actual damage characteristics of the RH CMOS logic circuit using
the RH V-gate n-MOSFET with the standard CMOS logic circuit, as shown in Figure 7. The
schematics of the NOT, NAND, and NOR gates, are shown in Figure 7a–c, respectively. The
standard CMOS logic circuit and RH CMOS logic circuit are the same in terms of schematic
representation, with the layout of the n-MOSFET being the only difference between the
standard n-MOSFET and V-gate n-MOSFET. The channel sizes for the n-MOSFET and
p-MOSFET in the NOT, NAND, and NOR gates are the same as the results obtained from
the two models. The channel sizes for the n-MOSFET and p-MOSFET are designed as
2 µm/0.5 µm (W/L) and 4 µm/0.5 µm (W/L), respectively.
 tively. The standard CMOS logic circuit and RH CMOS logic circuit are the same in term
of schematic representation, with the layout of the n-MOSFET being the only differenc
between the standard n-MOSFET and V-gate n-MOSFET. The channel sizes for the n
MOSFET and p-MOSFET in the NOT, NAND, and NOR gates are the same as the resul
Electronics 2023, 12, 3331 obtained from the two models. The channel sizes for the n-MOSFET and p-MOSFET
7 of 12 a
designed as 2 µm/0.5 µm (W/L) and 4 µm/0.5 µm (W/L), respectively.

Figure 7. Schematic of the logic circuit (a) NOT gate, (b) NAND gate, and (c) NOR gate.
Figure 7. Schematic of the logic circuit (a) NOT gate, (b) NAND gate, and (c) NOR gate.
Figure 8 shows the layout of the RH CMOS logic circuit. Compared with the standard
CMOS8logic
Figure showscircuit,
the only theof
layout n-MOSFET
the RH CMOSwas replaced with theCompared
logic circuit. RH V-gate layout-type
with the standar
n-MOSFET. In the CMOS structure, fixed charges in the STI oxide between the drain and
CMOS logic circuit, only the n-MOSFET was replaced with the RH V-gate layout-type n
source (n+) of the n-MOSFET and the n-well of the p-MOSFET can generate leakage current
MOSFET. paths.InThese
the leakage
CMOScurrentstructure, fixed
paths can charges
be easily in thebySTI
eliminated oxide
using guardbetween the drain an
rings. Therefore,
sourceguard
(n+) ofringthe n-MOSFET
(p+, n+) techniquesandwerethe n-well
applied of the n-MOSFET
to the p-MOSFET andcan generateinleakage
p-MOSFET the cu
proposed RH CMOS logic circuit to prevent leakage current
rent paths. These leakage current paths can be easily eliminated by using paths when fixed charges occur
guard ring
Electronics 2023, 12, x FOR PEER REVIEW 8 of 13
in the STI oxide between the drain and source (n+) of the n-MOSFET and n-well of the
Therefore, guard ring (p+, n+) techniques were applied to the n-MOSFET and p-MOSFE
p-MOSFET.
in the proposed RH CMOS logic circuit to prevent leakage current paths when fixe
charges occur in the STI oxide between the drain and source (n+) of the n-MOSFET and n
well of the p-MOSFET.

Figure 8. Layout of the RH CMOS logic circuit.

Figure 8. Layout of the RH CMOS logic circuit.
Figure 9 shows the circuit simulation of the designed CMOS logic circuit with the
Figurecurrent
leakage 9 shows the circuit
flowing simulation
through. of the designed
To simulate CMOS
the leakage logic
current circuit through
flowing with the the n-
leakage current flowing through. To simulate the leakage current flowing through the n-
MOSFET owing to the TID effect, the n-MOSFET was modeled as a current source,
whereas the resistance of the p-MOSFET when the n-MOSFET was OFF and the p-
MOSFET was ON was modeled as a resistor for the circuit simulation. If a leakage current
of 20 uA flows through the n-MOSFET when it is in the OFF state due to the TID effect,
 Figure 8. Layout of the RH CMOS logic circuit.

Electronics 2023, 12, 3331 8 of 12

Figure 9 shows the circuit simulation of the designed CMOS logic circuit wi
leakage current flowing through. To simulate the leakage current flowing through
MOSFET owing to the TID effect, the n-MOSFET was modeled as a current s
MOSFET owingwhereas
to the TID effect,
the the n-MOSFET
resistance was modeled
of the p-MOSFET as a current
when source, whereas
the n-MOSFET was OFF and
the resistance ofMOSFET
the p-MOSFET
was ONwhen the n-MOSFET
was modeled was for
as a resistor OFFtheand the p-MOSFET
circuit simulation. If was
a leakage c
ON was modeled as a resistor for the circuit simulation. If a leakage current of
of 20 uA flows through the n-MOSFET when it is in the OFF state due to the TID 20 uA flows
through the n-MOSFET
there willwhen it is in drop
be a voltage the OFF state
in the due toofthe
product theTID effect, there
p-MOSFET’s on will be a and the
resistance
voltage drop in age
the product
current for logic “1.” However, if no leakage current is flowingforthrough
of the p-MOSFET’s on resistance and the leakage current
logic “1.” However,
MOSFET,if no the
leakage current
voltage valueisofflowing
logic “1”through
will bethe n-MOSFET,
maintained thesupply
at the voltagevoltage of
value of logic “1” willthe
Once be maintained
circuit design,at the supply
layout, andvoltage of 3.3verification
simulation V. Once theare circuit design, the chip
completed,
layout, and simulation
ufacturingverification are completed,
process will be carried out the through
chip manufacturing
semiconductor process will be Subsequ
fabrication.
carried out through semiconductor fabrication. Subsequently, the manufactured
the manufactured chip was implemented as a device under test (DUT) for chip waselectrical t
implemented asand a device under test
radiation testing. (DUT) for electrical testing and radiation testing.

Electronics 2023, 12, x FOR PEER REVIEW 9 of 13

Figure 9. Circuit
Figure 9. Circuit simulation result simulation
of the CMOSresult ofcircuit.
logic the CMOS logic circuit.
3.2. Radiation Exposure Test and Analysis of Results
3.2. Radiation Exposure Test and Analysis of Results
The electrical characteristics were first determined to validate whether the CMOS
The electrical characteristics were first determined to validate whether the CMOS logic
logic circuits of the fabricated chip operated normally. The output was measured by ap-
circuits of the fabricated chip operated normally. The output was measured by applying
plying square
square waves waves
(0–3.3 (0–3.3
V) of V) of
IN1 and IN2IN1
withand IN2 with
different different
cycles cycles
to the input to theFigure
terminal. input10terminal.
Figure
shows the10 electrical
shows the electrical output
characteristic characteristic
graph ofoutput
the CMOSgraph
logicofcircuit.
the CMOS logicpeak
The output circuit. The
output
values ofpeak values of
the standard andthe
RHstandard
CMOS logicandcircuits
RH CMOS logic
operated circuits
normally at operated normally at
approximately
3.2 V and the initial
approximately 3.2 peak
V andvalues were validated.
the initial peak values were validated.

Figure 10. Electrical characteristic test of the fabricated chips.

Figure 10. Electrical characteristic test of the fabricated chips.

Subsequently, an irradiation experiment was conducted to validate the TID effect in

an actual radiation environment. The TID effect test was conducted at a high-level radia-
tion facility at the Advanced Radiation Research Institute of Korea. Figure 11 shows the
 Electronics 2023, 12, 3331 9 of 12

Figure 10. Electrical characteristic test of the fabricated chips.

Subsequently, an irradiation experiment was conducted to validate the TID effect

Subsequently, an irradiation experiment was conducted to validate the TID effect
in an actual radiation environment. The TID effect test was conducted at a high-level
an actual radiation environment. The TID effect test was conducted at a high-level radi
radiation facility at the Advanced Radiation Research Institute of Korea. Figure 11 shows
tion facility at the Advanced Radiation Research Institute of Korea. Figure 11 shows t
the irradiation test setup. The test was divided into a control room that applied voltage
irradiation test setup. The test was divided into a control room that applied voltage to t
to the DUT and DUTmeasured the result
and measured through
the result an oscilloscope,
through andand
an oscilloscope, an anirradiation room
irradiation room that irr
that irradiated diated
the cumulative dose to the test sample through a radiation source.
the cumulative dose to the test sample through a radiation source. For For thethe irradi
irradiation test tion
conditions, the dosethe
test conditions, was set to
dose was5 kGy/h
set to 5 per hour,
kGy/h perthe total
hour, thecumulative dose dose w
total cumulative
was set to 25 kGy, and the electrical data were measured by applying sinusoidal waves
set to 25 kGy, and the electrical data were measured by applying sinusoidal waves (0–3
(0–3.3 V) to the V)
input terminals
to the IN1 andIN1
input terminals IN2andat different frequencies.
IN2 at different frequencies.

Figuretest
Figure 11. Irradiation 11.configuration.
Irradiation test configuration.

The experimental Theresults

experimental results
are shown are shown
in Figure in Figure
12. After 12. After
irradiation, theirradiation,
peak voltagethe of
peak volta
of theNOT
the standard CMOS standard CMOS NOT
gate decreased gate
from decreased
3.221 from
V to 2.97 1 V,3.221 V to 2.97
the NAND 1 V,decreased
gate the NAND gate d
Electronics 2023, 12, x FOR PEER REVIEW 10 V.
of Th
13
from 3.231 V tocreased
2.904 V,from
and 3.231 V to gate
the NOR 2.904decreased
V, and thefrom
NOR3.246
gate decreased
V to 2.51 V. from
This3.246 V to 2.51
confirms
confirms
that the radiation damage thatwas
the caused
radiation
bydamage
voltagewas caused
drops by voltage drops
of approximately of0.33,
0.25, approximately
and 0.2
0.33, and 0.74 V for the NOT, NAND, and NOR gates, respectively.
0.74 V for the NOT, NAND, and NOR gates, respectively. In contrast, the peak voltage of In contrast, the pe
the RH CMOS NOT,voltage of the RH
NAND, andCMOS NOT,using
NOR gates NAND, theand
RHNOR
V-gate gates using theranged
n-MOSFET RH V-gate
fromn-MOSFE
ranged from 3.213 V to 3.211 V, 3.241 V to 3.24 V, and 3.255 V to 3.238 V, respectively, with
a3.213 V to 3.211 V, 3.241 V to 3.24 V, and 3.255 V to 3.238 V, respectively, with a small voltage
small voltage drop. In other words, the radiation resistance characteristics were vali-
drop. In other words, the radiation resistance characteristics were validated. Additionally,
dated. Additionally, as shown in Figure 13, when the leakage current was extracted, the
as shown in Figure 13, when the leakage current was extracted, the general CMOS NOT,
general
NAND, andCMOS NOR NOT,
gatesNAND, and NOR gates
were approximately 11.52 were approximately
µA, 13.05 µA, and 21.6911.52 µA, 13.05 µA, and
µA, respectively.
21.69 µA, respectively.
In contrast, In contrast,
the leakage currents theCMOS
of the RH leakage currents
logic of thenearly
circuits were RH CMOS logic
unaffected by circuits
were
radiation damage, measuring approximately 10 nA, 34 nA, and 42 nA, respectively, in thenA, and
nearly unaffected by radiation damage, measuring approximately 10 nA, 34
42 nA,ofrespectively,
order in the order of tens of nanoamperes.
tens of nanoamperes.

12.Radiation
Figure 12.
Figure Radiationcharacteristics experiment.
characteristics experiment.
Electronics 2023, 12, 3331 10 of 12
Figure 12. Radiation characteristics experiment.

Figure13.
Figure Actual measurement
13.Actual measurement results
resultsofof
thethe
leakage current
leakage of the
current ofCMOS logic circuit
the CMOS based on
logic circuit the on the
based
cumulative dose.
cumulative dose.

Table 1 summarizes the leakage currents flowing in the CMOS logic circuit owing
Table 1 summarizes the leakage currents flowing in the CMOS logic circuit owing to
to the TID effect. Unlike conventional CMOS logic circuits, the RH CMOS logic circuit
the TID effect.
exhibited Unlike
minimal conventional
leakage CMOS
currents owing logic
to the TID circuits, the study,
effect. In this RH CMOS logic circuit
we validated the ex-
hibited
damageminimal leakage
that occurred currents
in standard owing
CMOS to circuits
logic the TID effect.
owing In this
to the study,aswe
TID effect, validated
well as the the
damage
radiationthat occurred
tolerance in standard
characteristics CMOS
of RH CMOS logic circuits
logic circuits,owing to the TID with
using n-MOSFETs effect,
RHasV-well as
the radiation
gate toleranceThe
layout structures. characteristics of RH used
CMOS logic circuits CMOS logic circuits,
in radiation using n-MOSFETs
environments are mainly with
RHused in various
V-gate layoutsystems, such The
structures. as DSPs
CMOSor FPGAs, and tensused
logic circuits of millions of logicenvironments
in radiation circuits are are
used in one system. Supposed cumulative damage occurs in a CMOS
mainly used in various systems, such as DSPs or FPGAs, and tens of millions of logiclogic circuit, which
influences
circuits arethe nextinlevel,
used oneoverlaps
system.with the accumulated
Supposed cumulativedamage,
damageand causes
occursa malfunction
in a CMOS logic
of the system, such as timing errors or data errors. Therefore, the design of radiation-
circuit, which influences the next level, overlaps with the accumulated damage, and
resistant CMOS logic circuits is crucial. As mentioned earlier, the V-gate layout structure
causes a malfunction
is smaller of the
and faster than system,that
structures such as timing
utilize errorstransformation
other layout or data errors. Therefore, the
techniques.
Furthermore, by controlling the gate poly, p+, and p-active layer in various forms, such
as an I-shape, L-shape, C-shape, and Z-shape, there are advantages in configuring CMOS
logic circuits with more efficient electrode connections of the n-MOSFET and p-MOSFET.
Additionally, this can ensure symmetry, making them robust against mismatches. Therefore,
by merely altering the gate shape and adding a few layers, this technique becomes more
radiation resistant and can be applied to existing processes, providing a distinct advantage
compared to MOSFETs that use other layout modification techniques.

Table 1. Actual measurement results of the leakage current of the experiment on the TID effect.

Type Leakage Current (@25 kGy)

Standard CMOS NOT [µA] 11.52
Radiation-Hardened CMOS NOT [µA] 0.01
Standard CMOS NAND [µA] 13.05
Radiation-Hardened CMOS NAND [µA] 0.034
Standard CMOS NOR [µA] 21.69
Radiation-Hardened CMOS NOR [µA] 0.042

4. Conclusions
This study proposed an RH CMOS logic circuit for the radiation-resistant design of
CMOS logic circuits, which are essential elements in most semiconductor ICs. The proposed
RH CMOS logic circuit used the RH V-gate n-MOSFET based on the layout modification
technique, which is resistant to the TID effect for the n-MOSFET constituting the CMOS.
Electronics 2023, 12, 3331 11 of 12

The RH V-gate n-MOSFET was minimized in terms of speed and area among the layout
modification techniques and provided various structural advantages to RH circuit design,
considering that the electrodes of each device can be connected more efficiently when
configuring semiconductor ICs. A 3D structure was modeled and simulated using the
TCAD tool to predict the damage characteristics of the TID effect before chip fabrication.
The damage characteristics were modeled using the cutoff depth method for the fixed
charges generated in the oxide layer of the n-MOSFET. The simulation results showed that,
unlike the standard CMOS logic circuit, the radiation tolerance characteristics of the RH
CMOS logic circuit were consistent with those before the damage. Upon the completion of
the modeling and simulation, standard and RH CMOS logic circuits were designed using
KEY FOUNDRY’s 0.18 µm (STI) CMOS process to validate the actual radiation damage
characteristics of the RH CMOS logic circuit. Each circuit was designed using the Cadence
and Specter tools and was finally implemented as an IC chip after the layout design and
process validation. The normal operation of the fabricated IC chip was validated through
an electrical characteristic test. A radiation irradiation test was conducted using a high-
level gamma-ray irradiation device at the Korea Advanced Radiation Research Institute to
validate the actual damage characteristics. Based on the experimental results, the RH CMOS
logic circuit based on the RH V-gate n-MOSFET was found to be resistant to the TID effect,
unlike the standard CMOS logic circuit. Finally, when the V-gate n-MOSFET with these
advantages was configured as a CMOS logic circuit, the area of the system significantly
decreased, the speed improved, and the leakage current was almost nonexistent, owing
to the radiation resistance. This research was conducted with the aim of enhancing the
radiation tolerance of the semiconductors used in radiation environments, such as space
and nuclear power plants. Additionally, significant contributions are expected to achieve
the anti-radiation of electronic systems in radiation environments by improving the area
and speed of existing devices.

Author Contributions: Conceptualization, D.K. and N.L.; methodology, D.K. and S.C.; software,
D.K. and M.L.; validation, S.C., D.K. and M.L.; investigation, D.K.; data curation, D.K. and M.L.;
writing—original draft preparation, D.K. and M.L.; writing—review and editing, S.C. and D.K.;
visualization, M.L.; supervision, S.C.; project administration, N.L. All authors have read and agreed
to the published version of the manuscript.
Funding: This research was supported by the KAERI Institutional R&D Program (Project No. 523420-
23). This research was supported by the IDEC.
Data Availability Statement: No new data were created or analyzed in this study. Data sharing is
not applicable to this article.
Conflicts of Interest: The authors declare no conflict of interest.

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