A) METODO MAPAS DE KARNAUGH

A) a)
A B C D E

U5 U6 U7 U8 U9
NAND NAND NAND
NAND NAND

U1

U12
NAND U15

NAND

U2 NAND

U13
NAND

Elio Churata U3
U14 U17 F PFC NAND

NAND

NAND NAND_3
NAND

U4
U16
U11
NAND

U10 NAND_3
NAND

NAND

A B C D E

U21
U18 U19 U20 NOR U22
NOR NOR NOR NOR

U25
U23
Elio Churata
NOR_4

NOR U26

U24
NOR_4 U33 F SFC NOR

NOR
U27 NOR_4

NOR_4

U28

U30 NOR_4

U29 U32
NOR

U31
NOR NOR

NOR
A,a) Codigo en VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY metKarnaug IS
PORT(
A,B,C,D,E : IN STD_LOGIC;
F_a, F_a_red : OUT STD_LOGIC
);
END metKarnaug;

ARCHITECTURE arch OF metKarnaug is

BEGIN

F_a <= (
(NOT A AND NOT B AND NOT C AND NOT D AND NOT E) OR -- M0
(NOT A AND NOT B AND NOT C AND NOT D AND E) OR -- M1
(NOT A AND NOT B AND NOT C AND D AND NOT E) OR -- M2
(NOT A AND NOT B AND NOT C AND D AND E) OR -- M3
(NOT A AND NOT B AND C AND NOT D AND NOT E) OR -- M4
(NOT A AND NOT B AND C AND D AND NOT E) OR -- M6
(NOT A AND B AND NOT C AND NOT D AND NOT E) OR -- M8
(NOT A AND B AND NOT C AND NOT D AND E) OR -- M9
(NOT A AND B AND NOT C AND D AND NOT E) OR -- M10
(NOT A AND B AND C AND NOT D AND NOT E) OR -- M12
(NOT A AND B AND C AND NOT D AND E) OR -- M13
(NOT A AND B AND C AND D AND NOT E) OR -- M14
(A AND NOT B AND NOT C AND NOT D AND NOT E) OR -- M16
(A AND NOT B AND NOT C AND D AND E) OR -- M19
(A AND NOT B AND C AND NOT D AND E) OR -- M21
(A AND NOT B AND C AND D AND E) OR -- M23
(A AND B AND NOT C AND NOT D AND E) OR -- M25
(A AND B AND NOT C AND D AND E) OR -- M27
(A AND B AND C AND NOT D AND E) -- M29
);
F_a_red <=((not A and not B and not E) or (B and not D and E)
or (not A and D and not E) or (not C and not D and not E)
or (not A and not B and not C) or (A and not C and D and E)
or (A and not B and C and E))
;
END arch;
 A) b)

A B C D E

U34 U35 U36 U37 U38

NAND NAND NAND NAND NAND

U39

NAND_3

U40

Elio Churata NAND_3

U41
U42

NAND_3 F2 PFC

U43

NAND_8
NAND_4

U44

NAND_4

U45

NAND_4

U46(D1) U47(D1) U48(D1) U49(D1) U50(D1)

U47 U49
U46 U48 U50
NOR NOR NOR NOR NOR

U55
Elio Churata U51

NOR

NOR_3

U52

U57 U58
F2 SFC
NOR

U53
NOR_4 NOR_3

NOR

U54

NOR
U56

NOR_5
A,b) Codigo en vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY metKarnaug IS
PORT(
A,B,C,D,E : IN STD_LOGIC;
F_b, F_b_red : OUT STD_LOGIC
);
END metKarnaug;

ARCHITECTURE arch OF metKarnaug is

BEGIN

F_b <= (
(NOT A OR NOT B OR NOT C OR NOT D OR NOT E) AND (NOT A OR C OR NOT D OR E) AND
(NOT A OR NOT B D OR E) AND (NOT A OR C OR D OR E) AND (A OR C OR NOT D OR NOT
E)AND
(A OR NOT B OR NOT D OR E)AND (A OR NOT B OR D OR NOT E)AND (NOT A OR B OR C
OR D OR E) AND
(A OR B OR C OR E)AND (B OR NOT D OR E)AND (B OR D OR E)AND (B OR NOT C OR
E)AND
(A OR NOT B OR C OR D OR E)AND (A OR NOT B OR D OR E)
);
F_b_red <=(
(C OR E)AND (B OR E)AND(A OR E)AND(A OR C OR NOT D)AND(A OR NOT
B OR D)AND
(NOT A OR NOT B OR NOT C NO NOT D OR NOT E)
);
END arch;
 A) c)

U64:A
1 Z
3
U63:A 2 1
1
U60 4071
b2 U62:A U65 2 9
1 &
3 8
a2
NOT
2 &
4073
U61:A NOT
4081
1
3
2 1 Elio Churata
U62:B 4001
U59 5
4 b1
6 & U63:B
U66 3
4081 a1
NOT
4 6
&
5 U64:B
NOT
5 Y
4073 4
6 1
4071

a1 b1 a2 b2

U67 U68 U69 U70

NAND NAND NAND NAND

U71

NAND

U72 U75
Z PFC

NAND_3 NAND_3

U74

NAND_3

U76

NAND

U73 U78
Y PFC

NAND_3 NAND_3

U77

NAND_3
A,c) Codigo en VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY metKarnaug IS
PORT(
a_1, b_1,a_2,b_2 : IN STD_LOGIC;
Y, Z : OUT STD_LOGIC
);
END metKarnaug;

ARCHITECTURE arch OF metKarnaug is

BEGIN

Y <= (
(not a_1 and b_1 and b_2)or(not a_2 and b_2)or (not a_1 and b_1 and not a_2)
);
Z <=(
(a_2 and not b_2)or (a_1 and not b_1 and not b_2)or (a_1 and not b_1
and a_2)
);
END arch;
 B) OREX / NOREX

B) a) A) b)
A B C D

A B C D
U1

U10 U6 U12
XOR
Elio Churata
U2
NOT
AND XOR
U16
U36
U11
XOR
U7
U9 NAND
U13
NOT XOR
NOT
U8 U35
AND X1 U14
U5 NAND
U3 U18
OR_4 XOR U39
NAND X2

AND U37
AND NOR
NOR
U4 U15
U38 U17
XOR

AND NOR
NAND NOR

B) CODIGO EN VERILOG

module b_orex(
input A,B,C,D
output X_1,X_2
);

assign X_1 = (~A & ~C & ~D & ~E) | (~A & ~B & ~C & D & E) |
(~A & ~B & C & ~D & E) | (~A & C & D & ~E) | (~A & B & ~E) | (~A & B &
C & D);
assign X_2 = (~A|~B|~C|D)&(~A|B|~C|~D)&(~A|B|~C|D)&(~A|B|C|~D)&(A|~B|~C|D)

&(A|~B|C|~D)&(A|~B|C|D)&(A|B|~C|D)&(A|B|~C|D)&(A|B|C|~D);

endmodule
 c)QUINE McCLUSKEY

c) f1 c) f2 c) f2
A B C D A B C D

A B C D

U5 U6 U7 U8 U16 U17 U18

NOT NOT NOT NOT NOT NOT NOT
U2
U3 U10
U19
U4
f1
AND U20
NOT U24
AND_4
U1 OR f3
OR U11
U22
OR
AND
XOR
AND_3
AND

Elio Churata U12 U9

f2 U23

AND_3 OR_5 U21

U13 Elio Churata AND

OR

AND_3

U14

Elio Churata AND_3

c) Codigo en verilog

module quine_McCluskey (
input A,B,C,D,
output F_1, F_2,F_3
);

assign F_1 =
(~A&~B&~C&D)|(~A&~B&C&~D)|(~A&~B&C&D)|(~A&B&~C&~D)|(~A&B&~C&D)|(A&~B&C&~D)
|(A&B&~C&~D)
;
assign F_2 =
(~A&~B&~C&~D)|(~A&B&~C&D)|(~A&B&C&D)|(A&~B&~C&D)|(A&~B&C&D)|(A&B&~C&~D)|(A
&B&~C&D)|(A&B&C&~D)
;
assign F_3 =
(~A|~B|~C|D)&(~A|B|~C|~D)&(~A|B|C|D)&(A|~B|~C|D)&(A|B|~C|~D)&(A|B|C|~D)&(A|B|C|D);

endmodule
 D)VARIABLES BIFORMES

D) a D)b
P Q R S T A B C D E

U10
U5 U6 U7 U8 U1 NOT U16 U17 U18 U11
NOT NOT NOT NOT NOT NOT NOT NOT NOT

U2
U12

AND_3

U3 U9 AND_3
Fa
U14 U15
Fb simplificado

AND_3 OR_3

U4 AND OR_3

U13

Elio Churata AND_3

AND_3
Elio Churata
U19

AND_4

U20

AND_4 U25
U21
Fb sin simplificar

AND_3

U22 OR_6.DM

AND_3

U23

AND_3

U24

AND_3

module d_var_Biformes (
input A,B,C,D,E,
input P,Q,R,S,T,
output F_a, F_b,
);

assign F_a =
(~P&~Q&~R&~S&~T)|(~P&~Q&~R&~S&T)|(~P&~Q&R&~S&~T)|(~P&~Q&R&~S&T)|(P&~Q&~R&
~S&~T)|(P&~Q&~R&~S&T)|(P&~Q&R&~S&T)|(P&Q&~R&~S&T)|(P&Q&R&~S&T)
;
assign F_b = (~A&~B&C&~E)|(~A&~B&~C&~D)|(~B&D&~E)|(~B&C&~D)|(C&D&~E)|(B&D&~E)
;

endmodule
 e) APLICACION MAPAS DE KARNAUGH
Ao A1 A2 A3

U7
U1

AND
U10
NOR U11
Bo
U2
OR
OR
U8
NOR U9
B1
U3 Elio Churata
OR
OR

NOR

U5

U6
AND
U4
AND

NOR

E) Codigo en Verilog

module e_Apli_mapas_de_karnaugh (
input A_0,A_1,A_2,A_3,
output B_0, B_1,
);

assign B_0 = A_0|(A_1&~A_2&~A_3)|(~A_1&A_2&A_3);

assign B_1 = A_0|(~A_1&~A_2)|(~A_1&~A_3)
;

endmodule
 f)APLICACION OREX/ NOREX
L S V F

U1

XOR

U2 U3
U4 B

Elio Churata NOT

AND OR_3

F)CODIGO EN VERILOG
module f_apli_orex_norex (
input L,S,V,F,
output B,
);

assign B = L|(V&~F)|S^V;

endmodule
 g) APLICACION QUINE McCLUSKEY
A B C D E

U2

AND
Elio Churata U5
U3 U1 F

AND
AND OR_3

U4

AND

G)código en verilog
module g_apli_quine_mccluskey (
input A,B,C,D,E,
output F,
);

assign F = C&((A&D)|(A&E)|(B&D));

endmodule
 h) APLICACION VARIABLES BIFORMES
A B C D E
Elio Churata
U6

OR_4

U7

OR_4 F1 F2

U8 U5

OR_4 AND_5

U12

OR_4

U9

OR_4

U1 U2 U3 U11 U4
AND_4 AND_4 AND_4 AND_4 AND_4

U10
OR_5

H) Codigo en Verilog
module g_apli_var_biformes (
input A,B,C,D,E,
output F_1,F_2,
);

assign F_1 =
~((~A&~B&~C&~D&~E)|(~A&~B&~C&~D&E)|(~A&~B&~C&D&~E)|(~A&~B&C&~D&~E)|(~A&B&~
C&~D&~E)|(A&~B&~C&~D&~E));
assign F_2 =
(A&B&C&D&E)|(A&B&C&D&~E)|(A&B&C&~D&E)|(A&B&~C&D&E)|(A&~B&C&D&E)|(~A&B&C&D&E);

endmodule