Basics of UVM - Structure

Robin Garg

Engineering @ NUVIA
26 articles Following
November 29, 2016
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UVM (Universal Verification Methodology) is a SystemVerilog language based

Verification methodology which has rapidly gained lot of popularity, and is being widely
used across the VLSI Verification industry. This methodology is currently in the IEEE
working group 1800.2 and is expected to become an IEEE standard soon.
UVM is a methodology defined to build testbenches for verifying a design under
development. It consists of a defined methodology for architecting modular testbenches
for Design-Verification. UVM has a library of classes that helps in designing and
implementing modular testbench components and stimulus. This enables: Re-use of
testbench components and stimulus within and across projects, Development of
Verification IP, and Easier migration from simulation to emulation environment, etc.
Hence, owing to its advantages, knowledge of UVM has become an important sought-
after skill for Verification jobs.

Getting started with any new verification methodology is always bit tricky because a new
starter doesn't know where to begin from. On top of this, learning curve for UVM is
pretty steep due to its rigid/fixed structure which needs to be followed while
programming. Unavailability of resources that crisply summarize the structure, and flow
of events in the language aggravate the problem. Hence, through this post, I am going
to share few pointers that summarize "Basic UVM Structure". I came up with this
summary when I started exploring UVM. This summary helped me understand the
methodology better. Hopefully, this would help you as well.
Hope you enjoyed reading this summary.

In case you are preparing for Digital VLSI Verification interviews and are looking for one-
stop-shop resource to aid your preparations, please refer the book* (Cracking Digital
VLSI Verification Interview: Interview Success) I wrote with one of my good friends, and a
semiconductor veteran (Ramdas M). This book cover almost all the topics relevant to a
Digital VLSI Verification Interview.