Ain Shams Engineering Journal 14 (2023) 102049

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Ain Shams Engineering Journal

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Energy-Efficient circuits with improved diode free adiabatic logic design

methodology
Reginald H. Vanlalchaka, Reshmi Maity, Niladri Pratap Maity ⇑
Department of Electronics and Communication Engineering, Mizoram University (A Central University), Aizawl-796004, India

a r t i c l e i n f o a b s t r a c t

Article history: This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) cir-
Received 29 April 2022 cuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness,
Revised 7 October 2022 numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) tech-
Accepted 6 November 2022
nology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS
Available online 21 November 2022
design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static
CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-
Keywords:
phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked
Low Power Circuits
IDFAL
CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various oper-
ADCL ating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product
Adiabatic Logic (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS
QSERL inverter at 16 nm high-performance predictive technologies (HP_PTM).
2PADCL Ó 2022 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Ain Shams Uni-
2PASCL versity. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

1. Introduction tant factors [4–11]. When the device’s performance is primarily

In the field of very-large-scale-integration (VLSI) system design,
power design has emerged as a major concern since modern elec-
tronic systems are increasingly requiring low power usage. Elec-
tronic gadgets, both portable and nonportable, are highly popular
nowadays. Several industries and companies have worked to pro-
vide devices with higher performance at lower costs since the evo-
lution of VLSI technology [1–7]. It appears that we are all now
reliant on portable and hand-held devices. While in both high-
performance and portable applications, power consumption has
become a major issue. Consequently, various design strategies
are being developed to reduce power consumption [8–10]. One
of the most promising low-power design approaches has been
shown to be energy recovery circuits established on the adiabatic
switching principle [1–40]. Product efficiency and performance
can be measured in several ways, but the speed of operation and
power consumption (battery life) are usually the two most impor-
⇑ Corresponding author.
E-mail address: maity_niladri@rediffmail.com (N. Pratap Maity).
Peer review under responsibility of Ain Shams University.
Production and hosting by Elsevier
focused on power consumption rather than speed of operation,
adiabatically powered logic operation is desirable. The adiabatic
design approach is advantageous for devices that can be powered
at low frequencies, like smart cards, radio frequency identifications
(RFIDs), and sensors [11,12]. The primary goal of adiabatically
designed circuits is to minimize energy loss in CMOS circuits while
charging and discharging the load capacitor. Furthermore, since an
AC power supply is employed as an alternative of a DC power sup-
ply, the output transition by charging and discharging is consider-
ably slowed down, resulting in no heat emission inside the
adiabatic circuit as described in [13,14]. In addition, the charge
stored in load capacitor is retrieved during a specific adiabatic
phase, resulting in less energy loss [22,23].
Several adiabatic circuits have been presented over the years
[1–37]. Output floating, pipelining challenges, transmission delays,
the requirement for several sophisticated cloaking systems, silicon
area usage, and output voltage deterioration have all been reported
by some of the adiabatic logic families [16–19]. The output voltage
amplitude degradation is mainly because of the voltage drop that
occurs in the diode while charging and discharging the load capac-
itor [13–15,24].
The adiabatic switching process can be implemented with dif-
ferent shapes of power supply waveforms, such as trapezoidal, tri-
angular, and sinusoidal power sources. The sinusoidal power-clock
timing events are depicted in Fig. 1. It is distributed into two seg-

https://doi.org/10.1016/j.asej.2022.102049
2090-4479/Ó 2022 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Ain Shams University.
This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 1. Sinusoidal power supply.

ments: evaluation and hold/recovery. During the evaluation phase,

the energy is provided to the circuit and, consequently, output is
being evaluated, whereas, during the hold phase or recovery phase,
the output is either held or recovered depending on the input con-
ditions. In this phase, energy stored at the output node can be
recovered from the circuit and returned to power supply. The
four-phase trapezoidal power supply is shown in Fig. 2. It com-
prises events such as evaluation, hold, recovery, and wait. During
the evaluation phase, energy is drawn from power supply and uti-
lized by the circuit to do useful work while the new output is being
Fig. 3. Basic inverter of 2PASCL.
evaluated. The energy is kept at the output load capacitor during
the hold phase and is given back to the source power supply in
the recovery period. The circuit is idle and awaits the next input
during the wait state. In this work, we are using a sinusoidal power
clock as a substitute of a trapezoidal power supply since the sinu-
soidal waveform has more advantages than a trapezoidal power
clock [12,20].
Adiabatic switching can be accomplished by keeping the volt-
age drop across the switching devices as low as possible, which
can be achieved by charging the load output capacitor with a
non-DC power supply such as a sinusoidal, trapezoidal, or triangu-
lar power clock, as demonstrated in [22,23]. Figs. 3–9 show
schematics of the basic inverter circuits. Some of the popular refer-
ence adiabatic literature used in this work are 2PASCL [12], 2PADCL
[26], ADCL [15], QSERL [20], DFAL [24,25 39], and CCAL [7]. Fig. 3
depicts the basic inverter circuit using 2PASCL system. Figs. 4-8
describe the basic inverter circuits for ADCL, DFAL, QSERL, 2PADCL
and CCAL respectively. The proposed design IDFAL is compared
with conventional CMOS logic and the above reference logic in
respect of power consumption and propagation delays. In the
energy recovery circuit that employs diodes, the energy benefit
would be degraded unless the quotient of ðV t =V dd Þ is maintained
while scaling V dd [20], where V dd is supply bias and V t is threshold
voltage. The approximate energy dissipated in the diode during
each logic transition with capacitor ðC Þ is presented in [20] and Fig. 4. Basic inverter of ADCL.
shown below as:
Ediode ¼ CV t ðV dd  V t Þ ð1Þ Both technology scaling and power supply scaling are insepara-
ble, and they are mutually exclusive. However, there is an inevita-
ble problem with continual scaling of the threshold voltage as it
may lead to a significant escalation in leakage current which is a
major factor for today’s metal–oxide-semiconductor (MOS) devices
[41,42]. Several alternative gate-oxide materials are in research
[43–47]. Therefore, on scaling down the technology, preservation
of the ratio ðV t =V dd Þ is not feasible, and the energy recovery circuits
that involve diodes in the structure, such as 2PADCL, 2PASCL, ADCL
and QSERL, have encountered this type of drawback. In addition,
QSERL, 2PASCL and 2PADCL circuits also exhibited output voltage
floating at alternate hold phases. A single clock power supply is uti-
lized in an ADCL circuit to reduce power consumption, but this
imposes a substantial amount of gate delay [12]. Another type of
design: CCAL, DFAL and IDFAL use clocked control transistors
Fig. 2. Trapezoidal power supply.

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 5. Basic inverter of DFAL. Fig. 7. Basic inverter of 2PADCL.

Fig. 8. Basic inverter of CCAL.

Fig. 6. Basic inverter of QSERL.

clock system. Due to the split-level power supply, the peak current
flowing through transistors can be suppressed, minimizing power
instead of diodes. These control transistors restrict the output
consumption. In addition, the circuit is provided with control tran-
wave to follow the power supply signal for the whole cycle,
sistors to restrict the leakage power. The remainder of this paper is
thereby reducing node switching activity. These types of circuits
structured as follows: Section II discusses adiabatic circuit opera-
with clock control transistors can be operated at high frequencies
tion. Section III describes improved diode-free adiabatic logic and
[7,29].
mathematical analysis of the IDFAL. Section IV illustrates circuit
In this paper, we propose an improved diode-free adiabatic
design with IDFAL. Section V demonstrates results and discussions,
logic that is realized from conventional static CMOS logic. The logic
and Section VI concludes the paper.
utilized a two-phase, split-level complementary sinusoidal power

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 9. Basic IDFAL circuit.

Fig. 10. Equivalent RC model of IDFAL.

2. Improved diode free adiabatic logic


V /pp  V ctl
Fig. 9 shows a schematic of the IDFAL inverter, and Fig. 10 rep- ð2Þ
2
resents its RC equivalent circuit. The inverter circuit consists of five
transistors in total: two control transistors M 1 and M 4 , two func-
where V /pp is peak-to-peak voltage of the power supply V / , and V ctl
tional transistors M 2 and M 3 , and a transistor M 5 in the pull-
is voltage drop transversely the control transistor M1 , which is close
down network for discharging. The control transistors, as their
to the transistor’s drain-to-source voltage V DS and its threshold
name, implies, control the charging and discharging times of the
voltage V t [6,29].
circuits. That is, the circuit is connected to the power supply and
The circuit operations can be described by referring to Figs. 9–
limits flow of current only when it is deemed necessary, which
11. Depending on the nature of power clocks, the circuit actions
eliminates redundant switching at the output node and, in turn,
minimizes unwanted power dissipation. By replacing the transis-
tors M2 and M 3 , any logic function can be implemented. In addi-
tion, the circuit employs complementary split-level sinusoidal
power clocks, V / and V / , that substitute V dd and V ss , respectively
[12]. Two power clocks are 180 degrees out of phase. An LC reso-
nant oscillator can be used to build and implement these types
of power clocks effectively [12,27,28]. Each power clock’s peak-
to-peak voltage is set to half of V dd , implying that the magnitude
of both V / and V / peak-to-peak voltages is V dd =2. Therefore, by a
factor of V dd =2, voltage level of V / is higher than that of V / .
Through utilizing these two power clocks in the circuit, the voltage
among the current-carrying electrodes could be reduced, resulting
in reduced power consumption, as mentioned in [18]. That being
stated, M 1 and M4 are the control transistors that can be used to
limit the flow of current in the circuit and reduce dynamic and
leakage power, while M 2 and M 3 are the functional transistors that
influence logic operations, From Fig. 9 and Fig. 10, the output volt-
Fig. 11. A timing diagram of IDFAL.
age across the load capacitor C L swings at [29]:

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

are split into two phases: evaluation and hold, as depicted in Fig. 11. Consequently,
During the evaluation interval, V / goes up and V / goes down,

R2 C L  2
whereas in the hold interval opposite happens: V / swipes down ER2 ðchrgÞ ¼ C L V /pp  V ctl ð7Þ
4T
and V / swipes up. From the schematic presented in Fig. 9, IDFAL
is analogous to static CMOS logic. It is a normal static CMOS logic Therefore, from (4) and (6), total energy lost on charging is
with two additional control transistors, pull-up network and given as [15]:
pull-down network, and one more extra transistor in parallel to ET ðchrgÞ ¼ Ectl þ ER2 ðchrgÞ ð8Þ
the nMOS tree for reducing the discharging resistance of the cir-
cuit. The function of the inverter circuit based on the IDFAL design So,



is described below. V /pp  V ctl R2 C L  2
ET ðchrgÞ ¼ C L V ctl þ C L V /pp  V ctl ð9Þ
2 4T
1) Evaluation Phase:
a) In this phase, V / swipes up and V / swipes down, and by the The energy lost owing to threshold voltage of M 2 when it starts
time they reach their corresponding threshold voltages, both to be conductive is estimated as [4,6,15]:
the transistors M1 and M 2 are turned ON. 1  2
b) When output node Y is logic 0, or LOW state and the pMOS
Etp ¼ C L V tp ð10Þ
2
tree is ON, the output load capacitor C L is charged to logic 1,
Whereas, during discharging, the energy consumed by nMOS
through the pMOS transistors M 1 and M 2 , and therefore the
transistor M 3 due to threshold voltage has the same expression as:
output is maintained at a HIGH state.
1
c) No transition happens when nMOS transistors in the pull- Etn ¼ C L jV tn j2 ð11Þ
down network are ON but node Y logic level is in a LOW 2
state. Etp and Etn are the non-adiabatic energy losses, that are inevita-
ble [4]. On discharge, energy accumulated across the output load
When the output node is in HIGH state and the nMOS transis- capacitor C L is dissipated across the discharging path transistors.
tors in the pull-down network are turned ON, load capacitor C L is From equation (2), the output voltage swing is:
discharged to V / , and recycled via the transistors M 3 and M 4 ,

V /pp  V ctl
resulting in zero output logic. V out ¼ ð12Þ
2
2) Hold Phase: By applying Kirchhoff’s voltage law (KVL) to the discharging

a) In this phase, V / swipes down and V / swipes up and by the route when V / is swinging down as shown in [30], the output volt-
time they reach their corresponding threshold voltages, age swing is:
together the transistors M 1 and M 2 are turned off.
b) If the initial condition of output node Y is HIGH and only
V out ¼ V R þ V PDT ð13Þ
pMOS transistors in the pull-up network are switched ON, where V R denotes the voltage drop across transistor M 3 , and V PDT
no transition occurs. denotes the voltage across parallel transistors M4 andM5 . Since
the output voltage is identical to the load capacitor voltage, the total
Since the IDFAL is static in nature, unlike dynamic logic circuits energy consumption on discharging will be formulated as:
in which each gate requires continual charging and discharging
ET ðdischrgÞ ¼ ER3 ðdischrgÞ þ EPDT ðdischrgÞ ð14Þ
every clock cycle, the circuit nodes do not have to charge and dis-
charge every clock cycle, which dramatically minimizes node The energy dissipated in the parallel transistors is the product
switching activity. The hold phase significantly suppresses of the voltage drop across the transistors and the charge drawn
dynamic switching activities, resulting in lower power dissipation. from the output capacitor on discharging.
EPDT ðdischrgÞ ¼ QV PDT ð15Þ
3. Circuit analysis of IDFAL
From equations (3) and (15), we get
A. Dynamic Energy Consumption.

V /pp  V ctl
Assuming all the initial conditions of the circuit are zero. During EPDT ðdischrgÞ ¼ C L V PDT ð16Þ
2
charging, the charge Q ejected from the power supply is given
below by referring to [12,15,29]. The energy lost while discharging on the ON-resistance R3 is the

 same as it is in equation (7) as,
V /pp  V ctl
Q ¼ CL ð3Þ

2 R3 C L  2
ER3 ðdischrgÞ ¼ C L V /pp  V ctl ð17Þ
4T
The energy requires to transport the charge Q through the con-
trol transistor M 1 [13]. From equations (14), (16), and (17), the total energy lost while
discharging is:
Ectl ¼ QV ctl ð4Þ



R3 C L  2 V /pp  V ctl
From equation (2) and (3), we get, ET ðdischrgÞ ¼ C L V /pp  V ctl þ C L V PDT ð18Þ

 4T 2
V /pp  V ctl
Ectl ¼ CL V ctl ð5Þ The total energy loss, on the other hand, is the sum of dynamic
2
and static energy dissipations [36]. Therefore,
Also, the energy dissipated in the ON-resistance R2 of charging
ETotal ¼ Edynamic þ Estatic ð19Þ
path is given as:

2 The total energy consumption in IDFAL inverter is given as,
2 Q
ER2 ðchrgÞ ¼ i R2 T ¼ R2 T ð6Þ EIDFAL ¼ ðEadb þ EnonAL Þdynamic þ ðEleak Þstatic ð20Þ
T

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

From (9) and (18), clock frequencies can be double, trice, or multiples of input fre-
   2 CL   2  3 C L   2 quencies, and that may cause more delay time in logic transitions.
V /pp V ctl
Eadb ¼ C L 2
V ctl þ R4T C L V /pp  V ctl þ R4T C L V /pp  V ctl Fig. 13, depicts the waveform of the IDFAL inverter, and by utilizing
  the graph tool, the circuit delay was directly measured and evalu-
V V
þC L /pp2 ctl V PDT
ated. It’s worth noting that we do not apply a DC offset voltage to
ð21Þ the complementary power clocks in any simulations when analyz-
ing the power consumption and propagation delay of each circuit.
The non-adiabatic loss is the energy lost due to threshold volt-
The noise margins of Fig. 12, are estimated from the curve of the
age or drain-source potential difference when a MOS transistor
corresponding voltage transfer characteristic VTC, as illustrated in
begins to be conductive. Assuming the nMOS and pMOS are sym-
Fig. 14. The output voltage at high state V OH , low state V OL and
metrical. Hence, from (10) and (11):
the corresponding input voltage at low state V IL , and high state
1  2 1 V IH are obtained from the marker points of the graph when the
EnonAL ¼ Etp þ Etn ¼ C L V tp þ C L jV tn j2 ¼ C L V 2th ð22Þ slope of the curve is 1, i.e., Slope ¼ 1. The noise margin for high
2 2
input NMH ¼ ð469:588  266:596ÞmV ¼ 202:992mV and the noise
Assuming R2 and R3 are the same and denoted as R, the total
margin for low input NMH ¼ ð175:068  22:4292ÞmV ¼
energy consumption of an IDFAL circuit is given as:
152:6388mV are being evaluated. Unlike ADCL, 2PADCL, 2PASCL,
RC   2  
V V QSERL, etc., the IDFAL, as the name suggests, contains no diodes.
EIDFAL ¼ 2T
L
C L V /pp  V ctl þ C L /pp2 ctl ðV ctl þ V PDT Þ
ð23Þ It employs two control transistors; each control transistor being
þC L V 2th þ Eleak attached to both the pull-up and pull-down networks. Hence, it
can provide a better noise margin than those designs that involve
B. Leakage Energy Consumption.
diodes in their structure.
The general equation of leakage current is given as [16,43]:
B. NAND Gate Using IDFAL
 !
V GS V th V DS Maintaining all the circuit parameters and power supply under
Ileak ¼ I0 e nV T
1e VT
ð24Þ the same conditions as the previous IDFAL inverter circuit, a NAND
gate circuit is designed based on IDFAL and simulated to ensure the
Here, V T ¼ kT=q; V T is thermal voltage, k is Boltzmann’s con- feasibility of the IDFAL design technique. The circuit and waveform
stant, T is temperature in (Kelvin), and q is the number of charges are shown in Fig. 15 and Fig. 16, respectively.
in coulombs. A general formula for energy consumption is given C. IDFAL Inverter Chain.
below by Y. Takahashi et al. [26] and N. Anuar et al. [12]. Fig. 17 depicts the four inverter chains of an IDFAL circuit, each
with load capacitance of 0.01 pF. Power supply is connected in
ZT S !
X
n such a way that every alternate inverter has a different phase of
Ediss ¼ V pi  Ipi dt ð25Þ power source than the previous inverter and vice-versa [20]. Dur-
i¼1 ing the evaluation phase, the output of the first and third inverters
0
follows the power clock, whereas it is an antiphase with the second
The power clock and power clock bar expression are given in
and fourth inverters. During the hold period, the opposite happens.
equation (26) by N. Anuar et al. [3] and S. Upadhyay et al. [24].
The alternate power supply is useful for successful pipelining and
V / ¼ V4DD sin ðwt þ hÞ þ 34 V DD cascading and to minimize floating of the output nodes. Fig. 18
ð26Þ shows the waveform of the IDFAL four-inverter chain, indicating
V / ¼  V4DD sin ðwt þ hÞ þ 14 V DD
each output stage and the output logic are not degraded. The
According to [36], the leakage energy is given as: phases of cascaded inverters are reversed; when the second inver-
ter is evaluated, the first inverter is in the hold phase.
ZT Z p Z 3p   
2
Eleak ¼ Pleak ðt Þdt  Ileak  V / ðt Þdt þ Ileak  V / ðt Þ dt
0 p
0
2 5. Results and discussion

The integration intervals are obtained by referring to Fig. 11 and
after mathematical analysis the leakage energy may be approxi-
mated as:
2hþ3pw 2hþpw
V DD cos  V DD cos
Eleak ¼ Ileak 2 2
4w
4. Circuits design using IDFAL
A. Basic Inverter Circuit Using IDFAL.
Fig. 12 shows the basic inverter circuit of IDFAL using 45
nm_HP_PTM technology with parameters C L ¼ 10 pf and
V in ¼ 1V. Both the power clock PCK and PCK_bar are represented
by the time-varying voltages V / and V / , and the magnitude of each
peak voltage is fixed to 0.5 V. The operating frequency is set at
100 MHz, and the duration of each simulation is fixed at 50 ns.
Unlike other recovery circuits, both the complementary power
supply frequencies do not need to be double or larger than the
input signal frequency but can be operated at the same frequency.
That is to say, the input frequency and the supply frequency are
kept at the same value. In the case of 2PASCL, IDFAL, etc., power
The power consumption of each circuit is evaluated using the
Cadence Virtuoso analog design environment, as shown in
Fig. 19. Figs. 20 and 21, show the bar graph representation of the
þ pV DD w inverters’ power consumption at 45 nm_HP_PTM technology. The
ð27Þ aspect ratio W=L is calculated by choosing L = 45 nm, Wn = 400 nm,
and Wp = 600 nm. Other simulation parameters are set as Vin = 1 V,
and CL = 10 pf. The magnitude of the complementary sinusoidal
   
split voltage is given as V /  ¼ V /  ¼ 0:5 V. For all the adiabatic
families involved in the paper, both the input and power supply
frequencies are kept similar to obtain the minimal power con-
sumption of each design technique and to allow genuine compar-
isons among them. The frequency is set to 100 MHz and runs for 5
cycles, i.e., V in ¼ V / ¼ V / ¼ 100MHz. As mentioned earlier, the adi-
abatic logic design literature involved in this work includes ADCL,
QSERL, 2PADCL, 2PASCL, CCAL, and DFAL. The power supply voltage
for QSERL and 2PADCL is scaled to half of the peak amplitude of the
input voltage and marked QSERL (scaled) and 2PADCL (scaled).
Fig. 22 depicts the energy consumption of various adiabatically
powered inverter circuits at 100 MHz operating frequency.
Several CMOS technology nodes, their respective power sup-
plies V DD ðV Þ, the channel length LðnmÞ, the channel width for PMOS
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R.H. Vanlalchaka, R. Maity and N. Pratap Maity
Fig. 12. Inverter circuit (IDFAL).
W p ðnmÞ, the channel width for NMOS W n ðnmÞ, and aspect ratios
are illustrated in Table 1 as presented in [32]. In all analyses, the
load capacitor is fixed at C L ¼ 0:01 pF. Evaluation of the inverter
circuit’s average power consumption at various switching frequen-
cies from 20 MHz up to 800 MHz is depicted in Table 2. The CMOS
technology employed 180 nm Taiwan semiconductor manufactur-
ing company (TSMC). From Table 2, it can be seen that the IDFAL
circuit consumed the least average power at several operating fre-
quencies when compared to CMOS and other adiabatic logic
circuits.
Some of the standard and quasi-adiabatic logic circuits are effi-
cient for high frequency applications in the range of  500MHz
[29,30,37,49]. The proposed IDFAL has also exhibited its advan-
tages in high frequency usage. In this scenario, the analyses are
carried out at low frequencies in the range of KHz. Table 3 illus-
trates the inverter power consumption of IDFAL, CMOS, and differ-
ent adiabatic logic circuits at various frequencies. Results show
that, at low frequency analyses, the power dissipation of each logic
circuit significantly drops off. The IDFAL shows optimal power uti-
lization even at low frequency operations as compared to other
design strategies.
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Ain Shams Engineering Journal 14 (2023) 102049
Table 4 represents the leakage current and leakage power asso-
ciated with CMOS and adiabatic circuits at 100 MHz using 180 nm
TSMC technologies. Results show that ADCL has the best leakage
power saving. However, it has the slowest logic transitions, as
mentioned earlier in section 2. The IDFAL comes in second place
in leakage power saving. Each analysis was done within four cycles
of the operating frequency.
Table 5 and Table 6 present the average power consumption
of inverter circuits designed with conventional CMOS and several
adiabatic logic techniques at various frequencies using 45 nm
HP_PTM and 32 nm HP_PTM technology, respectively, and the
load capacitor is kept at C L ¼ 0:01 pF for each analysis. From
these two tables, it can be noted that at every operating fre-
quency, the proposed circuit IDFAL consumes the least power
when compared with CMOS and other design methods. These
tabulation results validate the power saving- capacity of the
IDFAL circuit.
The circuit delays of each gate are assessed from the associated
waveform. In Fig. 23, a CMOS inverter waveform with fixed hori-
zontal lines at 50 % of the input and output waveforms is depicted.
The simulation is performed at 16 nm_HP_PTM with device param-
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 13. Waveform of the IDFAL inverter circuit.

Fig. 14. Voltage Transfer Characteristic (VTC) of the IDFAL inverter circuit.

eters of L ¼ 16nm, W n ¼ 150nm, and W p ¼ 225nm respectively.
The supply voltage, input voltage and the load capacitor are
V DD ¼ 700mV, V in ¼ 700mV, and C L ¼ 10fF. The Fig. 23 demon-
strates how circuit delays are determined in all delay analyses. A
low-to-high propagation delay t pLH ¼ 0:03114 ns and a high-to-
low propagation delay t pHL ¼ 0:0307 ns are estimated, and the final
propagation delay is evaluated as 0:01546 ns. Due to the advantage
of being diode free in the IDFAL structure, it has comparatively
shorter propagation delays than other adiabatically designed
techniques.
Tables 7, 8, 9, and 10 show the average power consumption,
circuit delay, power delay product, energy consumption, and
energy-delay product (EDP) of basic logic gates using different
CMOS technology nodes, namely 16 nm_HP_PTM, 22 nm_HP_PTM,
32 nm_HP_PTM, and 45 nm_HP_PTM. Simulations are performed
within four clock cycles at 100 MHz. It should be noted that all

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 15. IDFAL NAND gate.

Fig. 16. Waveform of IDFAL NAND gate.

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 17. Waveform of IDFAL inverter chain.

Fig. 18. Waveform of IDFAL inverter chain.

power supply voltages except for CMOS and ADCL are scaled to half
of their corresponding input voltages, and the load capacitor is
fixed at C L ¼ 0:01 pF for all simulations. According to observation
tables 7, 8, 9, and 10, the average power consumption, PDP, energy
consumption, and EDP of the proposed IDFAL circuit at 16
nm_HP_PTM, 22 nm_HP_PTM, 32 nm_HP_PTM, and 45
10
nm_HP_PTM outperformed their counterpart traditional CMOS
and adiabatic logic design styles used in the work.
Here we observed also that the average power consumption for
each logic gate decreases gradually when we move from a higher
CMOS technology node of 45 nm to a lower CMOS technology node
of 16 nm. Fig. 24 depicts the average power savings of numerous
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 19. Analog design environment showing simulation parameters and the result of average power consumption in the analysis.

Fig. 20. 45 nm_HP_PTM, inverter power consumption at 50 MHz.

adiabatic logic circuits as compared to standard CMOS. The com- HP_PTM are 80.9 %, 92 %, 91.7 %, and 92.6 %, respectively, whereas
parative evaluations are carried out on inverter circuits at various the power savings in 32 nm HP_PTM are 90.02 %, 95.2 %, 95 %, and
CMOS technology nodes. The bar graph shows that the power sav- 95 %. In the same way, in 22 nm HP_PTM, the power savings are
ings of 2PASCL, CCAL, DFAL, and IDFAL over CMOS at 45 nm 94.4 %, 96.1 %, 96 %, and 96.2 %, respectively. Similarly, the power

11
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 21. 45 nm_HP_PTM, Inverter power consumption at 20 MHz.

Fig. 22. 45 nm_HP_PTM, inverter energy consumption at 100 MHz.

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Table 1
Different CMOS Technology Nodes, Their Respective Power Supplies, Parameters and Aspect Ratio.

CMOS Technology Nodes V DD ðV Þ LðnmÞ W p ðnmÞ W n ðnmÞ W p =L W n =L

180 nm_TSMC 1.8 180 800 400 4.444 2.222

45 nm_HP_PTM 1 45 600 400 13.333 8.888
32 nm_HP_PTM 0.9 32 420 280 13.125 8.75
22 nm_HP_PTM 0.8 22 300 200 13.636 9.090
16 nm_HP_PTM 0.7 16 225 150 14.062 9.375

Table 2
Comparision of 180 nm _TSMC Inverter Power Consumption at Various Operating Frequency Within Four Clock Periods / Cycles Times of Their Respective Inputs.

180 nm_TSMC: Average Power Consumption in (lW)

Logics/ 20 MHz 50 MHz 100 MHz 200 MHz 400 MHz 500 MHz 800 MHz
Freq.
CMOS 0.8279 2.111 4.254 8.556 17.14 21.42 34.34
2PASCL 0.5298 1.222 2.422 4.494 5.640 5.888 6.370
DFAL 0.02421 0.0676 5.505 5.883 6.708 7.195 8.653
CCAL 0.02765 0.07434 0.1697 0.4043 1.054 1.422 2.740
ADCL 0.1277 0.2035 0.3393 0.6406 1.297 1.634 2.608
2PADCL (Scaled) 0.2404 0.3175 0.4407 0.7067 1.314 1.645 2.702
QSERL (Scaled) 0.5663 0.7546 0.9722 1.409 2.368 2.885 4.541
IDFAL 0.02673 0.07054 0.1595 0.3836 0.9765 1.328 2.599

Table 3
Comparision of 180 nm _TSMC Inverter Power Consumption at Various Operating Frequency Within Five Clock Periods /Cycles Times of Their Respective Inputs.

180 nm_TSMC: Average Power Consumption in (nW)

Logics/ CMOS IDFAL DFAL CCAL 2PASCL 2PADCL ADCL QSERL
Freq.
10 K 193.8 0.01372 0.01464 0.0141 2.381 0.25 0.8613 0.3043
20 K 193.8 0.02736 0.02826 0.02811 2.437 0.4982 1.896 0.6183
50 K 193.8 0.06913 0.07295 0.07109 2.587 1.193 5.244 1.511
100 K 194.1 0.1379 0.1564 0.01475 2.910 2.243 11.06 2.901
200 K 195 0.2787 0.342 0.03261 3.586 4.128 22.81 5.395
400 K 198 0.5793 0.7345 0.06517 2.5 7.92 45.93 9.755
500 K 199.5 0.7136 0.9416 0.08815 5.627 9.295 71.36 11.73

savings of the aforementioned adiabatic logic circuits over tradi-

tional CMOS at 16 nm HP_PTM are 94.8 %, 96.6 %, 96.6 %, and
Table 4
Leakage Current and Leakage Power Measurements Within 40 nm Simulation Time, at 96.5 %. IDFAL provides better power savings and optimization in
a Frequency of 100 MHz. all scenarios.
The efficacy of the circuit is further investigated under a sub-
Basic Inverter using 180 nm_TSMC_Model
threshold regime. The PTM 22 nm BSIM4 model, which contains
Circuit Design Total Leakage Current (A) Leakage Power (W)
device parameters in the subthreshold region, is used to investi-
CMOS 23.7838  10-12 4.28  10-11 gate the behavior of adiabatic logic circuits in the weak inversion
2PASCL 24.6459653  10-27 2.22  10-26 or sub-threshold domain [48]. In this instance, the simulation’s
DFAL 12.65461  10-27 1.14  10-26
IDFAL 8.261607  10-27 7.44  10-27
parameters are set at L ¼ 22nm; Wn ¼ 200mV;
CCAL 13.8382  10-27 1.25  10-26 Wp ¼ 300mV; C L ¼ 5fF; V DD ¼ 200mV; V in ¼ 200mV; V / ¼ 100mV
2PADCL 14.16858  10-27 1.28  10-26 and V / ¼ 100mV [48]. Inverter circuit energy consumption of
ADCL 1.63267  10-37 1.47  10-37
IDFAL, CMOS, and several adiabatic logic circuits at various fre-
QSERL 17.5636  10-27 1.58  10-26

Table 5
Comparision of 45 nm _HP_PTM Inverter Circuits’ Power Consumptions at Several Operating Frequencies Within Four Clock Periods / Cycles Times of Their Respective Inputs.

45 nm_HP_PTM: Average Power Consumption in (nW)

Logics/ Freq. 20 MHz 50 MHz 100 MHz 200 MHz 400 MHz 500 MHz 800 MHz
CMOS 239.3 530 1175 2344 4671 5835 9353
2PASCL 117 160 220.9 305 401.5 436 509.7
DFAL 38.41 59.91 95.30 169.7 329.4 420.1 712.9
CCAL 37.41 58.42 91.71 161 313.2 398.2 677.5
2PADCL 44.58 91.6 144.9 205.4 266.4 290.6 350.9
(Scaled)
QSERL 53.64 115.4 196.7 302.5 420.5 455.2 539.2
(Scaled)
IDFAL 35.72 54.51 84.13 145.2 284.8 362.3 619.5

13
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Table 6
Comparision of 32 nm _HP_PTM Inverter Circuits’ Power Consumptions at Various Operating Frequency Within Four Clock Periods / Cycles Times of Their Respective Inputs.

32 nm_HP_PTM: Average Power Consumption in (nW)

Logics/ Freq. 20 MHz 50 MHz 100 MHz 200 MHz 400 MHz 500 MHz 800 MHz
CMOS 191.4 463.6 917.2 1825 3639 4545 7265
2PASCL 51.03 69.04 86.82 106.2 135 148.6 193.6
DFAL 10.78 23.16 43.75 88.29 186.8 245.3 431
CCAL 10.49 22.57 42.31 84.53 180.4 236 417.7
2PADCL 27.62 46.24 60.28 76.08 102.6 116.5 161
(Scaled)
QSERL 33.63 62.98 88.72 114.3 146.4 160.9 209.3
(Scaled)
IDFAL 10.07 21.24 39.89 79.98 172.8 223.5 403.7

Fig. 23. Waveform of the CMOS inverter circuit at 16nm_PTM.

Table 7
16 nm_HP_PTM: Performance Comparision of Basic Gates Designed Using Conventional CMOS and Various Adiabatic Logic Techniques Within 40 ns Simulation Time at 100 MHz
Operating Frequency.

16 nm_HP_PTM
Circuit Design Logic Gates Avg. Power (lW) Delays (ns) PDP Energy (fJ) EDP
(fJ) (10-24J)
CMOS NOT 0.5931 0.01546 0.009169 23.724 0.366773
NAND 0.6314 0.03391 0.021411 25.256 0.856431
2PASCL NOT 0.03084 0.248425 0.007661 1.2336 0.306457
NAND 0.03668 0.4913 0.018021 1.4672 0.720835
DFAL NOT 0.01987 0.184635 0.003669 0.7948 0.146748
NAND 0.0218 0.49841 0.010865 0.872 0.434614
CCAL NOT 0.0198 0.1851 0.003665 0.792 0.146599
ADCL NOT 0.6438 1.596875 1.028068 25.752 41.12273
NAND 0.5888 1.62494 0.956765 23.552 38.27059
IDFAL NOT 0.02032 0.098214 0.001995 0.8128 0.014804
NAND 0.0216 0.497765 0.010752 0.864 0.430069

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R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Table 8
22 nm _HP_PTM: Performance Comparision of Basic Gates Designed Using Conventional CMOS and Various Adiabatic Logic Techniques Within 40 ns Simulation Time at 100 MHz
Operating Frequency.

22 nm_HP_PTM
Circuit Design Logic Gates Avg. Power (lW) Delays (ns) PDP Energy (fJ) EDP
(fJ) (10-24J)
CMOS NOT 0.7203 0.02196 0.015818 28.812 0.632712
NAND 0.7602 0.028345 0.021548 30.408 0.861915
2PASCL NOT 0.04018 0.250305 0.010057 1.6072 0.40229
NAND 0.03648 0.652725 0.023811 1.4592 0.952456
DFAL NOT 0.02812 0.136815 0.003847 1.1248 0.15389
NAND 0.03065 0.210245 0.006444 1.226 0.25776
CCAL NOT 0.0277 0.124238 0.003441 1.108 0.137656
NAND 0.03030 0.480715 0.014566 1.212 0.582627
ADCL NOT 0.8630 1.05551 0.910905 34.52 36.43621
NAND 0.8243 1.489945 1.228162 32.972 49.12647
IDFAL NOT 0.02727 0.121255 0.003307 1.0908 0.132265
NAND 0.02942 0.482085 0.014183 1.1768 0.567318

Table 9
32 nm_HP_PTM: Performance Comparision of Basic Gates Designed Using Conventional CMOS and Various Adiabatic Logic Techniques Within 40 ns Simulation Time at 100 MHz
Operating Frequency.

32 nm_HP_PTM
Circuit Design Logic Gates Avg. Power (lW) Delays PDP Energy (fJ) EDP
(ns) (fJ) (10-24J)
CMOS NOT 0.9173 0.018435 0.01691 36.692 0.676417
NAND 0.9727 0.02249 0.021876 38.908 0.875041
2PASCL NOT 0.08971 0.182035 0.01633 3.5884 0.0586
NAND 0.08974 0.33411 0.029983 3.5896 0.107627
DFAL NOT 0.04548 0.058405 0.002656 1.8192 0.004832
NAND 0.05458 0.4592 0.025063 2.1832 0.054718
CCAL NOT 0.04395 0.05475 0.002406 1.758 0.00423
NAND 0.05307 0.45824 0.024319 2.1228 0.051624
ADCL NOT 1.095 0.77826 0.852195 43.8 34.08779
NAND 1.112 1.151985 1.281007 44.48 51.24029
IDFAL NOT 0.04118 0.026435 0.001089 1.6472 0.043544
NAND 0.04954 0.45983 0.02278 1.9816 0.911199

Table 10
45 nm_HP_PTM: Performance Comparision of Basic Gates Designed Using Conventional CMOS and Various Adiabatic Logic Techniques Within 40 ns Simulation Time at 100 MHz
Operating Frequency.

45 nm_HP_PTM
Circuit Design Logic Gates Avg. Power (lW) Delays (ns) PDP Energy (fJ) EDP
(fJ) (10-24J)
CMOS NOT 1.175 0.01547 0.018177 47 0.72709
NAND 1.585 0.024655 0.039078 63.4 1.563127
2PASCL NOT 0.2243 0.122625 0.027505 8.972 1.100192
NAND 0.2423 0.280 0.067844 9.692 2.71376
DFAL NOT 0.09727 0.016934 0.001647 3.8908 0.065887
NAND 0.1475 0.435245 0.064199 5.9 2.567946
CCAL NOT 0.09347 0.011255 0.001052 3.7388 0.04208
NAND 0.1439 0.43466 0.062548 5.756 2.501903
ADCL NOT 1.289 1.133005 1.460443 51.56 58.41774
NAND 1.327 1.088025 1.443809 53.08 57.75237
IDFAL NOT 0.08636 0.0241 0.002081 3.4544 0.083251
NAND 0.1348 0.435755 0.05874 5.392 2.349591
2PADCL (Scaled) NOT 0.1482 0.21792 0.032296 5.928 1.29183
NAND 0.1842 0.398625 0.073427 7.368 2.937069
QSERL (Scaled) NOT 0.200 0.557685 0.111537 8 4.46148
NAND 0.2369 0.9684 0.229414 9.476 9.176558

quencies is shown in Table 11. The analysis results revealed that at at lower frequencies or when either or both the time period and
a sub-threshold regime, the energy consumption of each logic cir- simulation times are extended. The IDFAL circuit exhibits its supe-
cuit is substantially minimized to the range of pJ. Table 11 vali- riority in energy optimization even when subjected to sub-
dates that adiabatic logic circuits have greater energy efficiency threshold domain analyses.

15
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Fig. 24. Dynamic power saving of adiabatic inverter circuits against conventional CMOS.

Table 11
Comparision of 22 nm _BSIM4 Inverter Average Energy Consumption at Various Operating Frequency Within Five Clock Periods /Cycles Times of Their Respective Inputs.

22 nm_BSIM: Average Energy Consumption in (pJ)

Logics/ CMOS IDFAL DFAL CCAL 2PASCL 2PADCL ADCL QSERL
Freq.
10 K 0.03661 0.00851 0.00907 0.00864 0.00994 0.01855 0.01557 0.0206
20 K 0.0724 0.01652 0.01729 0.01671 0.01881 0.03207 0.02988 0.03401
50 K 0.1801 0.04013 0.042 0.04063 0.04498 0.07095 0.05808 0.06773
100 K 0.3599 0.07915 0.08215 0.07965 0.08585 0.11075 0.1006 0.12505

6. Conclusion Declaration of Competing Interest

In this paper, we present an improved DFAL system. IDFAL uti-
lized two control transistors, resulting in the minimization of out-
put node floating. The control transistors and complementary
split-level power clocks reduce the leakage current and leakage
power. A parallel additional transistor across the pull-down net-
work reduced the discharging resistance and hence lessened the
dynamic power consumption. To validate the feasibility of the cir-
cuit, an extensive analysis is carried out at various technology
nodes, such as 180 nm TSMC, 45 nm, 32 nm, 22 nm, and 16 nm
HP_PTM. Besides circuit delay, average, and leakage power con-
sumption, assessments are performed with other aspects such as
PDP, and EDP on basic gates. It shows that IDFAL saves an average
power of 92.6 %, 95.5 %, 96.2 %, and 96.5 % against CMOS at 45 nm,
32 nm, 22 nm, and 16 nm HP_PTM. Observation and analysis
results and comparative performance evaluation exhibit its superi-
ority over CMOS. IDFAL has better power saving and optimization
than CMOS and the mentioned adiabatic logic families. We believe
that IDFAL is advantageous for forthcoming developments in low-
power VLSI circuit implementations.
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared
to influence the work reported in this paper.
Acknowledgment
The Authors are highly indebted to National Institute of Tech-
nology, Mizoram and Mizoram University (A Central University),
Mizoram, India for supporting this technical work.
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Reginald H. Vanlalchaka received M. Tech. degree in
Electronics Design and Technology from Tezpur
University, Assam, India. Since April, 2020, he is the
Assistant Professor in the department of electronics,
Government Zirtiri Residential Science College, Aizawl.
Currently he is doing research leading to his Ph.D.
degree in the department of electronics and communi-
cation engineering, Mizoram University (A Central
University), Aizawl, India. His research interests include
VLSI Design and Low Power Circuit Design.
Reshmi Maity received the B. Tech. and M. Tech. degree
in radio physics and electronics from University of
Calcutta, India, in 2004 and 2006 respectively. She has
completed her Ph. D. degree in electronics and com-
munication engineering from National Institute of
Technology, Silchar, India, in 2016. Dr. Maity, from
2004-2008, was an Assistant Professor in JIS College of
Engineering at Kolkata and an Assistant Professor in
Mizoram University at Aizawl, India. Since 2018, she is
an Associate Professor in the department of electronics
and communication engineering, Mizoram University,
India. Currently she is the Head of the department of
electronics & communication engineering Mizoram University at Aizawl, India. She
is the author of more than 125 archival refereed publications. Her research interests
include nanoelectronics and MEMS.
R.H. Vanlalchaka, R. Maity and N. Pratap Maity Ain Shams Engineering Journal 14 (2023) 102049

Niladri Pratap Maity received the M. Tech. degree in

electronics design and technology from Tezpur Univer-
sity, India, and the Ph.D. degree in electronics and
communication engineering from National Institute of
Technology, Silchar, India. Since 2020, he is a Professor
in the department of electronics and communication
engineering, Mizoram University, India. He is the author
of more than 150 articles. His research interests include
MOS device modeling, VLSI Design and MEMS. He is the
Fellow of IE (I), Fellow of IETE and Senior Member of
IEEE.

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