2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)
Design of Adiabatic Logic Two Tail Comparator
2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N) | 978-1-6654-7436-8/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICAC3N56670.2022.10074436
for Low Power and Analyze with CMOS
Comparator
Varun Sai Gajawada
Department of Electronics and Communication Engineering,
Saveetha University, Chennai, Tamilnadu. India
varunsai.gajawada1999@gmail.com
Abstract-- The purpose of the research is to develop an
innovative Adiabatic logic two tail comparator, analyze its
power utilization and compare it with Complementary Metal
Oxide Semiconductor (CMOS) logic two tail comparator.
Tanner tool EDA is used to simulate and check the comparator's
configuration. The length of transistors in a circuit was varied to
obtain power values. The innovative adiabatic logic double tail
comparator was found to consume power of 0.43mW. The
significance of the study is around 0.000 which is less than 0.05
(p<0.05). Compared to the adiabatic logic two tail comparator,
the developed CMOS logic two tail comparator shows low
consumption of power.
Keywords-- Innovative Adiabatic logic double tail
comparator, CMOS logic double tail comparator, tanner EDA
I. INTRODUCTION
A comparator is a system that compares the values of
two binary inputs. The two tail comparator proves to be
the most powerful device. Since it reduces piling, adds
complexity, and is low-voltage rail to rail, it's a good
option. Relaxation oscillators are often utilised in systems
that measure digitised analogue signals. For high-speed
applications, a two-tail comparator is employed [1], [2].
The voltage difference between the outputs will be
increased to improve the speed of the latch [3]. Because of
their significance in wireless sensor networks, low voltage
and less power in gadgets, analog to digital converters and
digital signal processing were more popular [4]. Adiabatic
logic and CMOS comparators are used in a variety of
applications, including analogue to digital converters,
wireless sensors, microcontrollers and microprocessors
[5].
Adiabatic logic circuit is a low power circuit which
uses “reversible logic” for conservation of energy. It
functions with the concept of switching activities in order
to increase the speed by returning the saved power again
to the mains. Two tail comparator is a clocked
regenerative comparator mostly used due to the ability of
providing fast solutions due to its favourable response
used in the regenerative storage device. The Adiabatic is a
very good technique at circuit and logic level to make the
circuit work under low power. The complication of the
series system increases. The lengthy downtime makes the
ISBN: 978-1-6654-7436-8/22/$31.00 ©2022 IEEE
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J. Mohana
Department of Electronics and Communication Engineering,
Saveetha University, Chennai, Tamilnadu. India
mohana@saveetha.com
system to ingest high energy and occupy large space
compared to the 4-phase adiabatic structure [6]. The adder
unit which contains diode frees adiabatic logic and option
unit for adiabatic logic family. The study is about
reduction of area dissipation. The power consumption is
not constant, it changes [7], [8]). Construction of sub
threshold adiabatic logic based parallel and series circuits
in the study finds single parallel and series circuit is
constructed based on stationary CMOS. Electrolytic
capacitors have not good performance [9]. The best
overall study is one subthreshold adiabatic logic because
here they have used circuits of different combinations.
This research aims to develop an adiabatic logic two tail
comparator, analyse its operation power with CMOS logic
double tail comparator [10]-[12].
The existing research has high power consumption.
There is a challenge in developing a low power consuming
comparator for applying in different applications.
Adiabatic Logic based comparators play a major role in
reduction of power consumption. Hence the overall
objective of the research is to develop an Innovative
adiabatic logic two tail comparator and analyse it among
the CMOS comparators.
II. MATERIAL AND METHOD
The design will look into the Innovative Adiabatic
comparator power consumption. A total of 20 different
lengths were taken for the experiment [13]. The adiabatic
double tail structure is considered as group 1. Few basic
transistors were used. Twenty different transistor lengths
were used in the experiment. The CMOS structure is
considered as group 2. It was decided that a regenerative
feedback system would be used. Twenty different transistor
lengths were used in the experiment. The system operated
by an Intel i3 7th generation processor and runs Windows 10
was used. Simulation was done using the tanner tool.
Analogue Integrated Circuits are often created with Tanner
EDA tools. Tools were used to join schematics, run SPICE
simulations, do physical design (chip layout) testing, as well
as design rule checks (DRC) and layout versus schematic
(LVS) tests. The construction of the comparator takes place
in the software suite for the design and layout [14].
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The implementation of the designed system and as Tanner. The power utilization of the systems were
available system was done using the software suite known analyzed.

Fig. 1. Proposed grounded lossy (a) inductance (b) series inductance (c) parallel inductance

Fig 2: Simulated waveform of adiabatic logic double tail comparator

.
III. STATISTICAL ANALYSIS
Statistical Package for Social Sciences 21 is the latest
version used in this analysis. Statistical methods were
followed to analyze the power values of the adiabatic logic
comparator and CMOS comparator. Descriptive statistics
were added to each model (mean, standard deviation, and
standard error). As a consequence, the mean, standard
deviation, and standard error of the comparators was
calculated.
values are 0.43190 and 0.38035. The outline of an adiabatic
two tail comparator is shown in Fig 1. PMOS and NMOS
transistors are utilized. In the circuit is given the VIn, CLK,
and out. Fig 2 shows the outputs of a software suite of T-
spice NMOS logic two tail comparator. The input voltage,
clock and output waveform is shown. Graphs depict volt
with second functions. Fig 3 gives the chart adiabatic
functions representing X axis and a CMOS two tail
comparator in Y-axis. Also power consumed by the groups
is given. It indicates that adiabatic comparators consume
much less power than CMOS logic.

IV. RESULTS
In order to assess power consumption, twenty sizes were
used for analysis. The values of mean for the proposed logic
and the existing logic are exhibited in the Table 2. The mean

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 2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)

To The proposed CMOS logic absorbs 0.38 mW of

power, which is better than the Adiabatic logic. In this
method, adiabatic logic is used to design and simulate an
innovative two tail comparator which is suitable for green
energy systems. Fig. 1 shows the adiabatic comparator
interface circuit. The results of the built comparator is
depicted through the Fig. 2. According to the simulated
results shown in Table I, the CMOS function two tail
comparator has a mean consumption of 0.38 mW, which is
slightly lower than the adiabatic two tail comparator 0.43
mW. Table II shows that the significance of the study is
around 0.000 which is less than 0.05 (p<0.05). This shows
that the study is 99 percent confident. The parallel is also
evident in the bar chart.
The two Tail Comparator using Adiabatic Logic for less
power and delay, can be used in high speed applications like
flash ADC’s, memory sense amplifiers and data receivers
[15]. To decrease power dissipation during transistor
Fig. 3. Adiabatic logic vs CMOS two tail comparator is shown. X axis switching, an adiabatic logic-based comparator was
represents the two groups (Adiabatic and CMOS). Y axis gives the mean designed for low power and high speed applications. Instead
with=+/-1SD of being dumped to the earth, energy should be recycled at
the output node [16]. Low-power ADC design and
V. DISCUSSION simulation utilising a double-tail comparator is more
efficient for the estimation and optimization of the power
performance and by placing the
TABLE I. MEAN VALUES OF THE ADIABATIC AND CMOS TWO TAIL COMPARATORS

Group N Mean Std deviation Std Error Mean

Power Adiabatic 20 .43190 .061137 .013671

power CMOS 20 .38035 .142932 .031961

TABLE II. THE MEAN, STANDARD DEVIATION, AND SIGNIFICANCE DIFFERENCE OF THE ADIABATIC AND CMOS TWO TAIL COMPARATOR

Levene’s Test for Equality of Variances t-test for Equality of Means 95% Confidence interval
of the Difference

F Sig t df Sig(2- Mean Std Error Lower Upper

tailed) difference Difference

Power Equal 18.9 .00 1.48 38 .146 .051500 .034762 -.018821 .121921
variances 5
assumed

Equal 1.48 25.7 .150 .051550 .034762 -.0.19940 .123040

variances
not
assumed

design in between SAR-ADC the power performance is supply clocks. Clock synchronization is more complex. A
improved [17]. Comparative analysis of various adiabatic CMOS function two tail comparator had the lowest
logic techniques for low power but technique uses split level consumption of power than adiabatic logic two tail

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 2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)
comparator. The limitation of the study is the investigation
of power consumption of the built comparator by changing
the operating frequency and voltage. Comparator can be
built using latched logic in the future for performance
analysis.
VI. CONCLUSION
The research discusses output of the Adiabatic logic
comparator, and compares them with the CMOS logic two tail
comparator by varying its duration. CMOS logic comparator
power consumption is 0.38 mW, which is less than the
Adiabatic comparator 0.43 mW.
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