The ModelSim™ Value

VLOG
ModelSim symbolizes value in HDL simulation.
To learn what this means, look to the thousands
of satisfied engineers worldwide who demand
ModelSim for VHDL, Verilog and mixed-HDL designs.

They turn to Model Technology Incorporated (MTI)

because we made ModelSim easy to learn and use.
We power it with breakthrough simulation technology.
We back it with technical support from the very
engineers who created the simulator. And we offer
ModelSim at outstanding prices. For debugging
million-gate ASICs or turning FPGAs fast, ModelSim
is the best choice in HDL simulation.

• Complete adherence to standards

IEEE 1364-’95 with PLI and SDF
• Functionally compatible with
other major Verilog tools, making
the switch easy
• Race detection allows hazard
detection for uncovering race
conditions prior to silicon
• Performance gains with Optimized
Direct Compile technology, which
provides fast compilation and simu-
lation portable across platforms
• Easy to use intuitive user interface
makes ModelSim an effective
interactive tool
• Fast iteration loops with Dynamic
loading of PLI shared object and
compiled Verilog object code make
design iterations fast and efficient
during the early design stages
ModelSim/VLOG Overview
ModelSim/VLOG is a full-featured are back-annotated with SDF files.
Verilog simulator that adheres to ModelSim/VLOG’s Dynamic Hazard
industry standard IEEE 1364-'95. Detection can pinpoint specific race
ModelSim/VLOG enables the fastest conditions during run time and identify
compile times, quick simulation the Verilog statement causing the
performance and design and library potential hazard. With Dynamic Hazard
portability by using Optimized Direct Detection, these problems can be de-
Compile architecture. And, with Tcl/Tk, tected very early in the design process
complete customization of the graphi- when they can be easily changed, thereby
cal user interface (GUI) is possible. making the source code truly portable
ModelSim/VLOG provides greater in execution across other Verilog
levels of openness, fast debugging and simulators. This capability not only
a simple migration path from alternative saves precious design time, but
Verilog environments by providing money as well.
sufficient Verilog-XL compatibility.
Additionally, features like Dynamic
Hazard Detection and Dynamic
loading of PLI are also standard in
ModelSim/VLOG.
Race Detection
The Verilog language offers the
simulator the flexibility of executing
concurrent events in any order.
As such, race conditions may not be
detected until late in the design
process when interconnect delays

Model Technology
 Compatibility with Verilog Tools
ModelSim/VLOG adheres to the IEEE
1364-’95 standard for the Verilog lan-
guage and PLI, but MTI development
engineers did not stop there.
Recognizing the strong industry
support for Verilog, MTI took
ModelSim/VLOG beyond the IEEE
standard and into the industry standard
by implementing additional built-in PLI
system tasks, replicating compile and
invoke options that Verilog users are
familiar with, and by simplifying the
mechanism for specifying user-defined
PLI applications. MTI has also part-
nered with leading Verilog front-end
debuggers. All of this makes the
ModelSim/VLOG includes a powerful graphical user interface and dynamic hazard migration to ModelSim/VLOG from
detection for identifying race conditions prior to silicon commitment. other Verilog environments easy.
Gate-Level Performance
ModelSim/VLOG is optimized for
Dynamic Loading of PLI code or exiting the simulator. This gate-level performance and MTI is
ModelSim/VLOG dynamically loads reduces the support needed for the committed to providing powerful
PLI routines. Other Verilog simulators Verilog environment by allowing all Verilog simulation tools with high
use static binding of Verilog PLI engineers to use a standard simulator performance now and in the future.
routines, which require a support for each project, team and design. With each new version of ModelSim,
staff to compile the PLI routines and performance is improved.
Debugging in Verilog
to build them into simulators unique The ModelSim/VLOG user interface Leading Standards Support
for every project. consists of nine windows, each with ModelSim/VLOG adheres to the
MTI’s approach provides maximum flex- unique functionality for debugging Verilog specifications and PLI system
ibility for PLI coding. ModelSim/VLOG Verilog designs. Eight of these nine tasks defined by IEEE 1364-’95.
users can manage their own PLI windows (Structure, Signals, Source, ModelSim/VLOG also provides support
applications and control the debug and Process, Variables, Dataflow, Wave, of Standard Delay Format (SDF) for
compilation of those applications. The and List) can have multiple invocations, back annotation and full PLI for model
compilation of these PLI applications permitting multiple views of the Verilog extension. In addition, ModelSim/VLOG
are separate from the compilation of design and data. This empowers the supports VCD (value change dump) for
the Verilog source code; the compiled designer with the freedom to combine standard Verilog vector output.
PLI routines and the compiled Verilog design data into views that make Complete Product Support
objects are not bound together until logical debugging sense. and Maintenance
the invocation of the ModelSim Many of the debug windows are A standard annual maintenance
simulator. Hence, as problems are dynamically linked together. Structure contract provides technical support,
detected in a PLI routine, the changes View, Signals, and Source code are maintenance releases, ModelUser
can be made, the PLI routine recom- tied together and tracked as selections newsletter and access to on-line
piled, and the simulator restarted, all change. The designer easily traverses support services. Technical support
without touching the Verilog source the design and quickly locates informa- is available by phone, fax, e-mail and
tion, aiding in debug. With the user at MTI’s website.
Ve r i l o g P e r f o r m a n c e G a i n s interface’s Tcl/Tk architecture, the Contact Model Technology at:
designer also has the freedom of
Model Technology Incorporated
“fixing” views of the design data.
8905 SW Nimbus Avenue, Suite 155
8x

This fixing of views and dynamically

linked views, coupled with multiple Beaverton, OR 97008-7100 USA
invocations of the various windows, phone: 503-641-1340
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demonstrates the power of ModelSim’s fax: 503-526-5410

e-mail: sales@model.com
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user interface.
web: www.model.com
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4.6i 5.0b 5.1 5.1b

M o d e l S i m / VLOG Ve r s i o n

1003-198 ModelSim/VHDL, ModelSim/VLOG and ModelSim/PLUS are trademarks of Model Technology Incorporated.
11/96 Verilog is a trademark of Cadence Design Systems. Windows is a registered trademark of Microsoft Corporation.
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