Register Transfer Language

The internal hardware organization of a digital computer is best defined

by specifying:
1. The set of registers it contains and their function.
2. The sequence of microoperation performed on the binary information
stored in the register.
3. The control that initiates the sequence of microoperation.
It is more convenient to adopt a suitable symbolic language to describe
the sequence of transfers between registers and the various arithmetic
and logic microoperation associated with the transfers, rather than using
explaining every operation in words.
Register Transfer Language can be defined as, the symbolic notation
used to describe the microoperation transfers among registers. The
term Register Transfer implies the availability of hardware logic circuits
that can perform a stated microoperation and transfer the result of the
operation to the same or another register. The word language is
borrowed from programmers, who apply this term to programming
languages.
Programming language is a procedure for writing symbols to specify a
given computational process. In the same manner, a natural language
such as Arabic is a system for writing symbols and combining them into
words and sentences for the purpose of communication between
people. A Register Transfer Language is a system for expressing the
microoperation sequences among the registers of a digital module in
symbolic form. It can be used to facilitate the design process of digital
systems.
Register Transfer
Normally computer registers are designated by capital letters,
sometimes followed by numerals to denote the register function. For
example, the Address Memory Register is designated by (MAR), in which
it is function is to hold an address for the memory unit. Other examples
are Program Counter (PC), Instruction Register (IR), and Processor
Register (R1).
The n-bit of the register are numbered in sequence from 0 in the
rightmost position and increasing the numbers toward the left.

Figure 5.1 shows different forms of register representation.

1. Figure 5.1(a) shows the common way to represent a register (a
rectangular box with the name of the register inside).
2. Figure 5.1(b) shows how the individual register bits are distinguished.
3. Normally the numbering of bits in a 16-bit register is marked on top of
the box as shown in figure 5.1(c).
4. For a partitioned 16-bit register into two parts as shown in figure
5.1(d), bits 0 to 7 are assigned the symbol L (low byte), while bits 8 to15
are assigned the symbol R (high byte), and the name of the register is PC
(Program Counter).here the symbol PC(0-7)or PC(L) refer to the low-
order byte and PC(8 -15) or PC(H) to the high-order byte.

Some basic symbols for register transfer are shown below

Symbol: Description: Examples
 Letters & Numerals: Denotes a Register
Examples: MAR, R2
 Parentheses ( ) :Denotes a part of a Register
Examples: R2(8-15), R2(L)
 Arrow :Denotes Transfer of Information
Examples: R2 ← R1
 Comma ,:Separates Two Microoperations
Examples : R2 ← R1, R1 ← R2
 Colon :Denotes Transfer of Information under a Predetermined
Control Condition
Examples : P: R2 ← R1
Normally registers are denoted by capital letters with numerals
Parentheses are used to denote a part of register either by specifying
the range of bits or by giving a symbol name to a portion of a register.
Arrows denote a transfer of information and the transfer direction as
A Comma is used to separate two or more operations that are executed
at the same time.
A Colon is used to terminate the control condition.
The statement R2 ← R1 denotes a transfer of the content of register R1
into R2, in which, the content of the source register R1 remains
unchanged.
The statement R2 ← R1, R1 ← R2 denotes an operation that exchanges
the contents of two registers R1 and R2 during one common clock
pulse.
The statement P: R2 ← R1 denotes a transfer of the content of register
R1 into R2 provided that the control function P = 1 in which, the content
of the source register R1 remains unchanged.
Figure 5.2 shows the block diagram that explains the transfer of
information from register R1 to R2 providing that the control function
P = 1.
The n outputs of register R1 are connected to the n inputs of register R2.
Register R2 has a load input that is activated by the control variable P.
Here; it is assumed that the control variable is synchronized with the
same clock as the one applied to the register. The timing diagram shows
P which activated in the control section by the rising edge of a clock
pulse at time t. The next positive transition of the clock at time t+1 finds
the load input active and the data inputs of R2 are then loaded into the
register in parallel. P may go back to 0 at time t+1; otherwise, the
transfer will occur with every clock pulse transition while P remains
active.
 Memory Transfer
• Memory Transfer The transfer of information from a memory word
to the outside environment is called a read operation.
• The transfer of new information to be stored into the memory is
called a write operation.
• A memory word will be symbolized by the letter M.
• The particular memory word among the many available is selected
by the memory address during the transfer.
• It is necessary to specify the address of M when writing memory
transfer operations.
• This will be done by enclosing the address in square brackets
following the letter M.

Memory read
• The address register, symbolized by AR.
• The data are transferred to another register, called the data
register, symbolized by DR.
• The read operation can be stated as follows:
Read: DR <- M[AR]

Memory write
• memory write this causes a transfer of information into DR from
the memory word M selected by the address in AR.
• The write operation transfers the content of a data register to a
memory word M selected by the address.
• Assume that the input data are in register Ri and the address is in
AR.
• The write operation can be stated symbolically as follows
Write: M[AR] <- R1
Shift micro-operations are those micro-operations that are used for serial
transfer of information. These are also used in conjunction with arithmetic
micro-operation, logic micro-operation, and other data-processing
operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for
logical shift-left and shr for shift-right.
1. Logical Shift Left –
In this shift one position moves each bit to the left one by one. The
Empty least significant bit (LSB) is filled with zero (i.e, the serial
input), and the most significant bit (MSB) is rejected.

2. Right Logical Shift –

In this one position moves each bit to the right one by one and the
least significant bit(LSB) is rejected and the empty MSB is filled with
zero.
2. Arithmetic :
This micro-operation shifts a signed binary number to the left or to the right
position. In an arithmetic shift-left, it multiplies a signed binary number by 2
and In an arithmetic shift-right, it divides the number by 2.
1. Left Arithmetic Shift –
In this one position moves each bit to the left one by one. The
empty least significant bit (LSB) is filled with zero and the most
significant bit (MSB) is rejected. Same as the Left Logical Shift.

2. Right Arithmetic Shift –

In this one position moves each bit to the right one by one and the
least significant bit is rejected and the empty MSB is filled with the
value of the previous MSB.
3. Circular :
The circular shift circulates the bits in the sequence of the register around
the both ends without any loss of information.
1. Left Circular Shift –

2. Right Circular Shift –

 Arithmetic Logic Shift Unit
Arithmetic Logic Shift Unit (ALSU) is a member of the Arithmetic Logic
Unit (ALU) in a computer system. It is a digital circuit that performs
logical, arithmetic, and shift operations. Rather than having individual
registers calculating the micro operations directly, the computer deploys
a number of storage registers which is connected to a common
operational unit known as an arithmetic logic unit or ALU.

Now, to implement the micro operation, the contents of specified

registers are allocated in the inputs of the common Arithmetic Logic
Unit. The Arithmetic Logic Unit performs an operation that leads as a
result and gets transferred to a destination register. Arithmetic Logic
Unit may be a combinatory circuit in order that the complete register
transfer operation from the supply registers through the ALU and into
the destination register is performed throughout one clock pulse amount.
Sometimes, the shift micro operations are performed in a separate unit,
but sometimes it is made as a part of full ALU.
 We can combine and make one ALU with common selection variables by
adding arithmetic, logic, and shift circuits. We can see the, One stage of
an arithmetic logic shift unit in the diagram below. Some particular
micro operations are selected through the inputs S1 and S0.

4 x 1 multiplexer at the output chooses between associate arithmetic

output between Ei and a logic output in Hi. The data in the multiplexer
are selected through inputs S3 and S2 and the other two data inputs to
the multiplexer obtain the inputs Ai – 1 for the shr operation and Ai +
1 for the shl operation.

Note: The output carry Ci + 1 of a specified arithmetic stage must be

attached to the input carry Ci of the next stage in the sequence.

The circuit whose one stage is given in the below diagram provides 8
arithmetic operations, 4 logic operations, and 2 shift operations, and
Each operation is selected by the 5 variables S3, S2, S1, S0, and Cin.

The below table shows the 14 operations perform by the Arithmetic

Logic Unit:

1. The first 8 are arithmetic operations which are selected by S3 S2

= 00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 =
10 & 11
We can combine and make one ALU with common selection variables by
adding arithmetic, logic, and shift circuits. We can see the, One stage of
an arithmetic logic shift unit in the diagram below. Some particular
micro operations are selected through the inputs S1 and S0.

4 x 1 multiplexer at the output chooses between associate arithmetic

output between Ei and a logic output in Hi. The data in the multiplexer
are selected through inputs S3 and S2 and the other two data inputs to
the multiplexer obtain the inputs Ai – 1 for the shr operation and Ai +
1 for the shl operation.

Note: The output carry Ci + 1 of a specified arithmetic stage must be

attached to the input carry Ci of the next stage in the sequence.
 The circuit whose one stage is given in the below diagram provides 8
arithmetic operations, 4 logic operations, and 2 shift operations, and
Each operation is selected by the 5 variables S3, S2, S1, S0, and Cin.

The below table shows the 14 operations perform by the Arithmetic

Logic Unit:

1. The first 8 are arithmetic operations which are selected by S3 S2

= 00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 =
10 & 11
 Instruction Codes :
A set of instructions that specify the operations, operands, and the sequence by which
processing has to occur. An instruction code is a group of bits that tells the computer to perform
a specific operation part.

 Format of Instruction :
The format of an instruction is depicted in a rectangular box symbolizing the bits of an
instruction. Basic fields of an instruction format are given below:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective address is
determined.
 Computers may have instructions of different lengths containing varying number of
addresses. The number of address field in the instruction format depends upon the
internal organization of its registers.
 Addressing Modes:
To understand the various addressing modes to be presented in this section, it is imperative
that we understand the basic operation cycle of the computer. The control unit of a
computer is designed to go through an instruction cycle that is divided into three major
phases:
1. Fetch the instruction from memory
2. Decode the instruction.
3. Execute the instruction.
There is one register in the computer called the program counter of PC that keeps
track of the instructions in the program stored in memory. PC holds the address of the
instruction to be executed next and is incremented each time an instruction is fetched from
memory. The decoding done in step 2 determines the operation to be performed, the
addressing mode of the instruction and the location of the operands. The computer then
executes the instruction and returns to step 1 to fetch the next instruction in sequence.
In some computers the addressing mode of the instruction is specified with a
distinct binary code, just like the operation code is specified. Other computers use a single
binary code that designates both the operation and the mode of the instruction. Instructions
may be defined with a variety of addressing modes, and sometimes, two or more addressing
modes are combined in one instruction.
The operation code specified the operation to be performed. The mode field is sued
to locate the operands needed for the operation. There may or may not be an address field
in the instruction. If there is an address field, it may designate a memory address or a
processor register. Moreover, as discussed in the preceding section, the instruction may
have more than one address field, and each address field may be associated with its own
particular addressing mode.
Although most addressing modes modify the address field of the instruction, there
are two modes that need no address field at all. These are the implied and immediate
modes.
 1 Implied Mode: In this mode the operands are specified implicitly in the definition
of the instruction. For example, the instruction “complement accumulator” is an
impliedmode instruction because the operand in the accumulator register is implied in the
definition of the instruction. In fact, all register reference instructions that sue an
accumulator are implied-mode instructions.

Op code Mode Address

Figure 1: Instruction format with mode field

Zero-address instructions in a stack-organized computer are implied-mode 34

instructions since the operands are implied to be on top of the stack.
2 Immediate Mode: In this mode the operand is specified in the instruction itself.
Inother words, an immediate- mode instruction has an operand field rather than an address
field. The operand field contains the actual operand to be used in conjunction with the
operation specified in the instruction. Immediate-mode instructions are useful for initializing
registers to a constant value.
It was mentioned previously that the address field of an instruction may specify
either a memory word or a processor register. When the address field specifies a processor
register, the instruction is said to be in the register mode.
3 Register Mode: In this mode the operands are in registers that reside within the
CPU.The particular register is selected from a register field in the instruction. A k-bit field can
specify any one of 2k registers.

4 Register Indirect Mode: In this mode the instruction specifies a register in the
CPUwhose contents give the address of the operand in memory. In other words, the
selected register contains the address of the operand rather than the operand itself. Before
using a register indirect mode instruction, the programmer must ensure that the memory
address fo the operand is placed in the processor register with a previous instruction. A
reference to the register is then equivalent to specifying a memory address. The advantage
of a register indirect mode instruction is that the address field of the instruction sues fewer
bits to select a register than would have been required to specify a memory address directly.

5 Auto increment or Auto decrement Mode: This is similar to the register indirect
modeexcept that the register is incremented or decremented after (or before) its value is
used to access memory. When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after every access to the
table. This can be achieved by using the increment or decrement instruction. However,
because it is such a common requirement, some computers incorporate a special mode that
automatically increments or decrements the content of the register after data access.

The address field of an instruction is used by the control unit in the CPU to obtain
the operand from memory. Sometimes the value given in the address field is the address of
the operand, but sometimes it is just an address from which the address of the operand is
calculated. To differentiate among the various addressing modes it is necessary to
distinguish between the address part of the instruction and the effective address used by
the control when executing the instruction. The effective address is defined to be the
memory address obtained from the computation dictated by the given addressing mode.
The effective address is the address of the operand in a computational-type instruction. It is
the address where control branches in response to a branch-type instruction. We have
already defined two addressing modes in previous chapter.

6 Direct Address Mode: In this mode the effective address is equal to the address
part ofthe instruction. The operand resides in memory and its address is given directly by the
address field of the instruction. In a branch-type instruction the address field specifies the
actual branch address.

7 Indirect Address Mode: In this mode the address field of the instruction gives
theaddress where the effective address is stored in memory. Control fetches the instruction
from memory and uses its address part to access memory again to read the effective
address.

8 Relative Address Mode: In this mode the content of the program counter is added
to theaddress part of the instruction in order to obtain the effective address. The address
part of the instruction is usually a signed number (in 2’s complement representation) which
can be either positive or negative. When this number is added to the content of the program
counter, the result produces an effective address whose position in memory is relative to
the address of the next instruction. To clarify with an example, assume that the program
counter contains the number 825 and the address part of the instruction contains the
number 24. The instruction at location 825 is read from memory during the fetch phase and
the program counter is then incremented by one to 826 + 24 = 850. This is 24 memory
locations forward from the address of the next instruction. Relative addressing is often used
with branch-type instructions when the branch address is in the area surrounding the
instruction word itself. It results in a shorter address field in the instruction format since the
relative address can be specified with a smaller number of bits compared to the number of
bits required to designate the entire memory address.

9 Indexed Addressing Mode: In this mode the content of an index register is added
to theaddress part of the instruction to obtain the effective address. The index register is a
special CPU register that contains an index value. The address field of the instruction defines
the beginning address of a data array in memory. Each operand in the array is stored in
memory relative to the beginning address. The distance between the beginning address and
the address of the operand is the index value stores in the index register. Any operand in the
array can be accessed with the same instruction provided that the index register contains
the correct index value. The index register can be incremented to facilitate access to
consecutive operands. Note that if an index-type instruction does not include an address
field in its format, the instructionconverts to the register indirect mode of operation. Some
computers dedicate one CPU register to function solely as an index register. This register is
involved implicitly when the index-mode instruction is used. In computers with many
processor registers, any one of the CPU registers can contain the index number. In such a
case the register must be specified explicitly in a register field within the instruction format.
 10 Base Register Addressing Mode: In this mode the content of a base register is
added to the address part of the instruction to obtain the effective address. This is similar to
the indexed addressing mode except that the register is now called a base register instead of
an index register. The difference between the two modes is in the way they are used rather
than in the way that they are computed. An index register is assumed to hold an index
number that is relative to the address part of the instruction. A base register is assumed to
hold a base address and the address field of the instruction gives a displacement relative to
this base address. The base register addressing mode is used in computers to facilitate the
relocation of programs in memory. When programs and data are moved from one segment
of memory to another, as required in multiprogramming systems, the address values of the
base register requires updating to reflect the beginning of a new memory segment.

Numerical Example:

Figure: Numerical example for addressing modes.

Figure : Tabular List of Numerical Example.
 Computer Instructions:
 What is the need for computer registers?
 The need of the registers in computer for
 Instruction sequencing needs a counter to calculate the
address of the next instruction after execution of the
current instruction is completed (PC).
 Necessary to provide a register in the control unit for
storing the instruction code after it is read from memory
(IR).
 Needs processor registers for manipulating data (AC and
TR) and a register for holding a memory address (AR).
 The above requirements dictate the register configuration shown in below
figure.
 The registers are also listed in Table 5.1 together with a brief description
of their function and the number of bits that they contain.
 The data register (DR) holds the operand read from memory.
 The accumulator (AC) register is a general purpose processing register.
 The instruction read from memory is placed in the instruction register (IR).
 The temporary register (TR) is used for holding temporary data during the
processing.
 The memory address register (AR) has 12 bits since this is the width of a
memory address.
 The program counter (PC) also has 12 bits and it holds the address of the
next instruction to be read from memory after the current instruction is
executed.
 Two registers are used for input and output.
 The input register (INPR) receives an 8-bit character from an
input device.
 The output register (OUTR) holds an 8-bit character for an
output device.
 Common Bus Registers :
 The basic computer has eight registers, a memory unit, and a control
unit
 Paths must be provided to transfer information from one register to
another and between memory and registers.
 A more efficient scheme for transferring information in a system with
many registers is to use a common bus.
 The connection of the registers and memory of the basic computer to
a common bus system is shown in Fig. .
 The outputs of seven registers and memory are connected to the
common bus.
 The specific output that is selected for the bus lines at any given time
is determined from the binary value of the selection variables S2, S1,
and S0.
 The number along each output shows the decimal equivalent of the
required binary selection.

 The lines from the common bus are connected to the inputs of each
register and the data inputs of the memory.
 The particular register whose LD (load) input is enabled receives the
data from the bus during the next clock pulse transition.
 The memory receives the contents of the bus when its write input is
activated.
 The memory places its 16-bit output onto the bus when the read input
is activated and S2S1S0 = 111.
 Two registers, AR and PC, have 12 bits each since they hold a
memory address.
 When the contents of AR or PC are applied to the 16-bit common bus,
the four most significant bits are set to 0's.
 When AR or PC receives information from the bus, only the 12 least
significant bits are transferred into the register.
 The input register INPR and the output register OUTR have 8 bits
each.
 They communicate with the eight least significant bits in the bus.
 INPR is connected to provide information to the bus but OUTR can
only receive information from the bus.
 This is because INPR receives a character from an input device which
is then transferred to AC.
 OUTR receives a character from AC and delivers it to an output
device.
 Five registers have three control inputs: LD (load), INR (increment),
and CLR (clear).
 This type of register is equivalent to a binary counter with parallel load
and synchronous clear.
 Two registers have only a LD input.
 The input data and output data of the memory are connected to the
common bus, but the memory address is connected to AR.
 Therefore, AR must always be used to specify a memory address.
 The 16 inputs of AC come from an adder and logic circuit. This circuit
has three sets of inputs.
 Another set of 16-bit inputs come from the data register
DR. One set of 16-bit inputs come from the outputs of
AC.
 The result of an addition is transferred to AC and the
end carry-out of the addition is transferred to flip-flop E
(extended AC bit).
 A third set of 8-bit inputs come from the input register
INPR.
 The content of any register can be applied onto the bus and an
operation can be performed in the adder and logic circuit during the
same clock cycle.
 For example, the two microoperations DRAC and AC  DR can be
executed at the same time.
 This can be done by placing the content of AC on the bus (with
S2S1S0 = 100), enabling the LD (load) input of DR, transferring the
content of DR through the adder and logic circuit into AC, and
enabling the LD (load) input of AC, all during the same clock cycle.
 Instruction Cycle
A program consisting of the memory unit of the computer includes a series of instructions.
The program is implemented on the computer by going through a cycle for each instruction.
In the basic computer, each instruction cycle includes the following procedures –

• It can fetch instruction from memory.

• It is used to decode the instruction.
• It can read the effective address from memory if the instruction has an indirect
address.
• It can execute the instruction.
After the following four procedures are done, the control switches back to the first step and
repeats the similar process for the next instruction. Therefore, the cycle continues until a
Halt condition is met. The figure shows the phases contained in the instruction cycle.

As display in the figure, the halt condition appears when the device receive turned off, on
the circumstance of unrecoverable errors, etc
Fetch Cycle
The address instruction to be implemented is held at the program counter. The processor
fetches the instruction from the memory that is pointed by the PC.
Next, the PC is incremented to display the address of the next instruction. This instruction is
loaded onto the instruction register. The processor reads the instruction and executes the
important procedures.
Execute Cycle
The data transfer for implementation takes place in two methods are as follows –

• Processor-memory − The data sent from the processor to memory or from memory
to processor.
• Processor-Input/Output − The data can be transferred to or from a peripheral device
by the transfer between a processor and an I/O device.
In the execute cycle, the processor implements the important operations on the
information, and consistently the control calls for the modification in the sequence of data
implementation. These two methods associate and complete the execute cycle
State Diagram for Instruction Cycle
The figure provides a large aspect of the instruction cycle of a basic computer, which is in the design
of a state diagram. For an instruction cycle, various states can be null, while others can be visited
more than once.

• Instruction Address Calculation − The address of the next instruction is computed. A

permanent number is inserted to the address of the earlier instruction.
• Instruction Fetch − The instruction is read from its specific memory location to the
processor.
• Instruction Operation Decoding − The instruction is interpreted and the type of
operation to be implemented and the operand(s) to be used are decided.
• Operand Address Calculation − The address of the operand is evaluated if it has a
reference to an operand in memory or is applicable through the Input/Output.
• Operand Fetch − The operand is read from the memory or the I/O.
• Data Operation − The actual operation that the instruction contains is executed.
• Store Operands − It can store the result acquired in the memory or transfer it to the
I/O

The flowchart of Fig. below presents an initial configuration for the instruction cycle and
shows how the control determines the instruction type after the decoding.
The three possible instruction types available in the basic computer are specified in Fig. on
basic computer formats
Decoder output D7 is equal to 1 if the operation code is equal to binary 111.
From Fig. on basic computer formats we determine that if D7 = 1, the instruction
must be a register-reference type or input-output type.
If D7 = 0, the operation code must be one of the other seven values 000
through 110, specifying a memory-reference instruction.
Control then inspects the value of the first bit of the instruction, which is now
available in flip-flop I. If D7 = 0 and I = 1, we have a memory reference instruction
with an indirect address.
It is then necessary to read the effective address from memory. The
microoperation for the indirect address condition can be symbolized by the
register transfer statement : AR ← M[AR]
Initially, AR holds the address part of the instruction. This address is used
during the memory read operation. The word at the address given by AR is read
from memory and placed on the common bus. The LD input of AR is then enabled
to receive the indirect address that resided in the 12 least significant bits of the
memory word.
The three instruction types are subdivided into four separate paths. The selected
operation is activated with the clock transition associated with timing signal T3. This
can be symbolized as follows:
D'7IT3 : AR ← M[AR]
D'7I'T3 : Nothing
D7I'T3 : Execute a register-reference instruction
D7IT3 : Execute an input-output instruction
 STACK ORGANIZATION
STACK ORGANIZATION

Stack is a storage structure that stores information in such a way that the last item stored is the first item retrieved. It is based on the
principle of LIFO (Last-in-first-out). The stack in digital computers is a group of memory locations with a register that holds the address
of top of element. This register that holds the address of top of element of the stack is called Stack Pointer.

Stack Operations
The two operations of a stack are:

Push: Inserts an item on top of stack.

Pop: Deletes an item from top of stack.

Applications

● Evaluation of mathematical expressions using Reverse Polish Notation

● To reverse a word. A given word is pushed to stack - letter by letter - and then poped
out letters from the stack.

● An "undo" mechanism in text editors; this operation is accomplished by keeping all text
changes in a stack

● Backtracking. This is a process when it is required to access the most recent data element
in a series of elements.

● Language processing

● space for parameters and local variables is created internally using a stack.

● The compiler's syntax check for matching braces is implemented by using stack.

● support for recursion

Implementation of Stack

There are two types of stack organisation which are used in the computer hardware.

1. Register Stack

2. Memory Stack

Register Stack

It is built using register

There are 64 registers used to make a register stack. The numbers 0, 1, 2, 3,.............. Upto 63 denote the address of
different registers.

SP is a pointer which points to the top of the stack i.e. it currently points to the item at the top.
The two more registers called FLAG and EMPTY are used. The Full and EMPTY registers are made up of
flip-flops.

It indicates whether the stack is full or not.

If FULlL = 1, then EMPTY = 0 it means that stack is full.

If FULlL = 0, then EMPTY= 1 it means that stack is empty.

Similarly the EMPTY flag states whether the stack is empty or not because while retrieving the data from the
stack it may happen that stack is empty.

DR is the data register through which data is transferred to and fro from the stack.
Operations

● Push Operation

SP ← SP + 1
//stack pointer is incremented by one M[SP] ← DR
// the content of the data register is stored at the current memory pointed by the stack pointer.
IF (SP = 0) then (FULL ←1)
(EMPTY ←0)
// The values of flag registers are set.

● Pop operation

DR ←M[SP]
// the content of current memory pointed by the stack pointer is stored to data register
SP = SP - 1
//stack pointer is decremented by one If (SP = 0) then ( EMPTY ←1) FULL ←0
Since the address of 64 registers are numbered from 0, 1, 2, 3,.............. Upto 63. The binary value of 63 is 111111
which is of 6- bits. When stack pointer is incremented after 63, it becomes 64 corresponding to the binary value
1000000 which is of 7 - bits. But in this case the address of each register is of 6- bits, hence 1 is discarded from the
binary value of 64. The stack pointer points to the 000000 address register. It implies that the stack is full.
Zero address instructions are used in registers stack organisation.
The address that does not contain the address of the operands.

Example: ( a + b) * ( c + d )

Following are the instructions to execute it

Push a
Push b
Add. Push c Push d Add. Mul.
// Zero address instruction
// Zero address instruction // Zero address instruction

Memory stack
It is a logical part of memory allocated as stack. The logically
partitioned part of RAM is used to implement stack.

The RAM is divided into three logical parts.

● Program- The logical part of RAM where programs are stored. The program section address starts from 1000.

● Data - It is the logical part of RAM where data ( operands) are stored.The data section address starts from 2000.

● Stack - It is the part of RAM used to implement stack. It's address starts from 3000 and continues upto 4001.

It is not necessary that the sequence and address of each part is fixed. It is logically decided by the manufacturer.
Program counter (PC) is used to point the program counter.
Data register is used to store data
Data is pointed by the address pointer or register. There is also a stack pointer.l

Push operation.

SP ← SP - 1.
M[SP]. ← DR.

POP operation

DR ← M[SP]
SP ← SP + 1
Consider its application - Evaluation of mathematical expressions using Reverse Polish Notation.
The common mathematical method of writing arithmetic expressions imposes difficulties when evaluated by a
computer. The Plolish mathematician Lukasiewicz showed that arithmetic expressions can be represented in prefix
notation as well as postfix notation.

Infix Prefix or Polish. Infix Prefix or Polish.

A+B +AB. A + B +AB.

Example : (3 * 4) * ( 5 * 6 ). 3 4* 5 6* *

Actually, this is how a computer evaluates the mathematical expressions. It is one of the applications of stack.
 INSTRUCTION FORMATS
A computer performs a task based on the instruction provided. Instruction in
computers comprises groups called fields. These fields contain different
information as for computers everything is in 0 and 1 so each field has different
significance based on which a CPU decides what to perform. The most common
fields are:
• Operation field specifies the operation to be performed like addition
• Address field which contains the location of the operand, i.e., register or
memory location
• Mode field which specifies how operand is to be founded.
Instruction is of variable length depending upon the number of addresses it
contains. Generally, CPU organization is of three types based on the number of
address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In the first organization, the operation is done involving a special register called
the accumulator. In second on multiple registers are used for the computation
purpose. In the third organization the work on stack basis operation due to which
it does not contain any address field. Only a single organization doesn’t need to
be applied, a blend of various organizations is mostly what we see generally.
Based on the number of address, instructions are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.
1.THREE-ADDRESS INSTRUCTIONS
Computers with three-address instruction formats can use each address field
to specify either a processor register or a memory operand. The program in
assembly language that evaluates X = (A + B) ∗ (C + D) is shown below, together
with comments that explain the register transfer operation of each instruction.
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M [A]
denotes the operand at memory address symbolized by A.
2.TWO-ADDRESS INSTRUCTIONS
Two address instructions are the most common in commercial computers.
Here again each address field can specify either a processor register or a
memory word. The program to evaluate X = (A + B) ∗ (C + D) is as follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
The MOV instruction moves or transfers the operands to and from memory
and processor registers. The first symbol listed in an instruction is assumed to
be both a source and the destination where the result of the operation is
transferred.
3.ONE-ADDRESS INSTRUCTIONS
One-address instructions use an implied accumulator (AC) register for all data
manipulation. For multiplication and division there is a need for a second
register. However, here we will neglect the second and assume that the AC
contains the result of tall operations. The program to evaluate X = (A + B) ∗ (C +
D) is
LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
All operations are done between the AC register and a memory operand. T is
the address of a temporary memory location required for storing the
intermediate result.
4.ZERO-ADDRESS INSTRUCTIONS
A stack-organized computer does not use an address field for the instructions
ADD and MUL. The PUSH and POP instructions, however, need an address field
to specify the operand that communicates with the stack. The following
program shows how X = (A + B) ∗ (C + D) will be written for a stack organized
computer. (TOS stands for top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M [X] ← TOS
To evaluate arithmetic expressions in a stack computer, it is necessary to
convert the expression into reverse Polish notation. The name “zero-address”
is given to this type of computer because of the absence of an address field in
the computational instructions.