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Electronic 17
Electronic 17
Electronic 17
Since it has a very high input resistance high input resistance , therefore I G could be
neglected. Hence , I D could be represented as function of V GS and V DS .
V GS
V DS ¿
I D= f ¿ ,
1
I D = g m V GS + V
r d DS
Where gm=
∆ID
∆V DS
| V DS =const . mutual-conductance or transconductance
1
=
∆ID
r d ∆ V DS
| V DS =const .
1 V
DS
where r d drain-resistance r d = y of = I D
μ=
∆ V DS
∆V GS
| I D =const .= g m r d =¿ amplification factor
V GS
Also g m = g mo (1− )
VP
DSS 2I
Where g mo = V p =¿ the value of g m of V GS =0
| |
Note:
[ ]
2
V
I D = I DSS 1− GS
VP
gm=
∂ID
∂ V DS
| V DS = const .
gm=
2 I DSS
VP [ ] [ ]
1−
V GS
VP
= g mo 1−
V GS
VP
1
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
2 I DSS
g mo =
| |
Vp
Common-Source Configuration:
The common-source configuration circuit of Fig. 17-1 includes a source resistor (RS)
that may or may not be bypassed by a source capacitor (CS) in the ac domain.
Fig. 17-1
Bypassed (absence of RS):
2
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-2
Input impedance:
Z i = RG
Output impedance:
Approximate (neglecting rd); Exact (including rd);
Z o = R D ( for rd ≥ 10 RD ) Z o = R D ∥ rd
´ ´
Zo= RL ∥ RD Z o = R L ∥ Z o= RL ∥ R D ∥ rd
Voltage gain:
Approximate (neglecting rd); Exact (including rd);
(
V O =−g m V gs RL ∥ R D ,) AV =−g m ( RL ∥ R D ∥ rd )
V gs=V i ,
Vo
AV =
Vi (
=−g m R L ∥ RD )
Vo Vo Vi Zi
AVs = = × = AV .
V s Vi Vs Z i + Rsig
Current gain:
Io Z
Ai = =−AV . i
Ii RL
Phase relationship:
The negative sign in the resulting equation for Av reveals that a 180o phase shift
occurs between the input and output signals.
3
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-3
Output impedance:
For V i =0 V , I o + I R = g m V gs , with V gs=−V R
D s | , at V =0 V =−( I + I ) R ,
i o RD s
I o=−I R
and D
Since D ( )
V o =−I R RD , thenV o =− −I o R D = I o R D , and
Vo
Zo= = RD
Io
4
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Voltage gain:
V o =−g m V gs ( Rl ∥ RD )
V o −−g m ( Rl ∥ R D)
Av = =
Vi 1+ g m Rs
Fixed-Bias Configuration:
≅ RD (rd ≥ 10 R D)
Vo
AV =
Vi (
=−g m rd ∥ RD )
= −g m rd (rd ≥ 10 R D)
5
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-4
For the ac equivalent circuit of Fig. 17-5,
Fig. 17-5
Input impedance:
Z i = RG [high]
Output impedance:
For V i =0 V , I o + g m V gs = I r + I R =V o / r d +V o / R s ⟹
d s
I o=V o (1 / r d +1 / Rs )− g m V gs , with
V gs ¿−V o | , at V =0 V ⟹ I =V
i o o (1 / r d +1 / Rs + g m ) ,
6
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
(1/ g m)
¿1 / r d +1 / Rs + 1/¿ ⟹
¿
Z o =V o / I o=1 /¿
Z o = r d ∥ Rs ∥1 / g m [low]
Rs
Z o= Rs∥ 1 / gm= ( for r d ≥ 10 R s)
1+ g m Rs
Voltage gain:
( )
V o =−g m V gs Rl ∥ R s ∥ r d ,
( ) (
V gs=V g−V s =V i−V o =V i−g m V gs Rl ∥ Rs ∥ r d ⟹V i =[1+ g m Rl ∥ R s ∥ r d ]V gs)
Vo g m ( Rl ∥ Rs ∥ r d )
Av = = [less than 1]
V i 1+ g m ( Rl ∥ R s ∥ r d )
Vo g m ( Rl ∥ R s )
Av = = ( for r d ≥ 10 Rs)
V i 1+ g m ( Rl ∥ R s)
Phase relationship:
Vo and Vi are in-phase.
Common-Gate Configuration:
Fig. 17-6
For the approximate ac equivalent circuit ( rd ≈ ∞Ω ) of Fig. 17-7,
7
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-7
Input impedance:
Rs
Z o= Rs∥ 1 / gm= [low] (Derive)
1+ g m Rs
Output impedance:
Zo= RD
Voltage gain:
( )
V o =−g m V gs Rl ∥ R D ,∧¿ V gs =−V i ⟹
Vo
Av =
Vi (
= g m R l ∥ RD )
Phase relationship:
Vo and Vi are in-phase.
For the JFET amplifier circuit of Fig. 17-8 with parameter gm = 2.2 mS, determine:
Zi, Zo, , Zo ′ Av = Vo/Vi, Ai = Io/Ii, Av =V o / V s and V o =0 . Assume r d ≥ 10 RD .
8
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-8
Solution:
Z i = R1 ∥ R2 =2.1 M ∥ 0.27 M =239 k Ω
´
Z i = R1 = 2.4 k Ω , Z o = R L ∥ RD = 4.7 k ∥ 2.4 k =1.59 k Ω .
Z i −(12.11)(239 k )
Ai =−AV . = =107.
RL 4.7 k
Zi (−2.11)(239 k)
AVs = AV . = =−2.10 ≈ AV .
Z i + Rsig 4.7 k
9
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Fig. 17-9
Solution:
V GsQ =V P / 4=¿ −4 / 4=−1 V ,
gm=
2 I DSS
| |
VP ( )
1−
V GS
VP
=
2(10 m)
4 ( )1−
−1
−4
= 3.75 mS ,
| A |= g ( R ∥ R ) ⟹7.5= 3.75 m ( 6 k ∥ R ) ⟹R = 3 k Ω .
v m L D D D
( ) ( )
2 2
V GSQ −1
I DQ = I DSS 1− =10 m 1− =5.625 mA ,
VP −4
Example:
10
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Solution:
V GSQ =−0.94 V
2 I DSS 2∗(8 m)
g mo = = = 4 mS
| |
VP |−4 |
g m = g mo
( ) (
1−
V GS
VP
= 4 mS 1−
−0.94 V
−4V ) =3.06 mS
3.06 mS
AV =−g m RD =−¿ )(1.2k)=-3.67
R i = RG = 1 M Ω
Ro = R D =1.2 k Ω
1 −R
r m= ⟹AV =−g m R D = D
gm rm
11
University of Thi-Qar
Electrical and Electronic Engineering Department lecture Seventeen
.Second year, Electronic ɪ, 2016-2017 by:Abdulqaffar S. M
Exercises:
2. Choose the values of RD, RS, and RL for the JFET amplifier circuit of Fig. 17-11
that will result in a gain of 18.062 dB. Assume that IDSS = 8 mA, VP = −4 V,
rd ≈ ∞ Ω, VDQ/VDD = 0.375, and IDQ/IDSS = 0.25. Calculate Avs =V o /V s , and
sketch Vo.
Fig. 17-11
12