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  • Maha Cover Page Labs VGHH

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    wajeehaadeel57
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    The document contains 3 lab reports for a Digital Logic Design course. The first report details familiarization with basic logic gates and their functions. The second report was on working with universal gates. The third report was about implementing XOR and XNOR gates using universal gates. Each report includes the student and faculty details.

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    maha cover page labs VGHH

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    The document contains 3 lab reports for a Digital Logic Design course. The first report details familiarization with basic logic gates and their functions. The second report was on working with universal gates. The third report was about implementing XOR and XNOR gates using universal gates. Each report includes the student and faculty details.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Download as pdf or txt
    6 views3 pages

    Maha Cover Page Labs VGHH

    Uploaded by

    wajeehaadeel57
    The document contains 3 lab reports for a Digital Logic Design course. The first report details familiarization with basic logic gates and their functions. The second report was on working with universal gates. The third report was about implementing XOR and XNOR gates using universal gates. Each report includes the student and faculty details.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 3

    DIGITAL LOGIC DESIGN LAB

    BS.ELETRONIC ENGINEERING 3RD SEMESTER


    (MORNING)
    TITTLE: Familiarization with Basic Logic Gates and their
    Function

    Student Name: Maha Rubab

    Registration No.2022-BEE-003

    Teaching Faculty
    MAM.KHUSHBAKHT (Course Coordinator)

    MAM.MEHWISH (Lab instructor)


    DIGITAL LOGIC DESIGN LAB
    BS.ELETRONIC ENGINEERING 3RD SEMESTER
    (MORNING)
    TITTLE: Working with Universal Gates

    Student Name: Maha Rubab

    Registration No.2022-BEE-003

    Teaching Faculty
    MAM.KHUSHBAKHT (Course Coordinator)

    MAM.MEHWISH (Lab instructor


    DIGITAL LOGIC DESIGN LAB
    BS.ELETRONIC ENGINEERING 3RD SEMESTER
    (MORNING)
    TITTLE: Implementation of XOR and XNOR using
    Universal Gates

    Student Name: Maha Rubab

    Registration No.2022-BEE-003

    Teaching Faculty
    MAM.KHUSHBAKHT (Course Coordinator)

    MAM.MEHWISH (Lab instructor

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