LAB 4A

GETTING STARTED WITH MODELSIM AND VERILOG HDL

OBJECTIVE:
● To get familiar with ModelSim working environment.
● Create Project, compile and run the simulation
● Basics of Verilog

PART (A)

1. INTRODUCTION TO MODELSIM
● Install ModelSim PE student edition 10.4a on your system.
https://www.mentor.com/company/higher_ed/modelsim-student-edition
● The startup screen looks like this:

● Create a new project by File>New>Project. The Create Project window pops up as

shown below:

Type the project name, lab5 for example in this case and click ok.

A new window pops up Add items to Project. Select Create New File
 Create Project File window appears

Type in a file name lab5 for example (The file name can be different from the project
name) and select Verilog as Add file as type option and select ok.

You will see lab5.v file added to your workspace as shown below:

1. To start typing in your code, Double Click the file name to edit it. The Editor window
appears and you can start your coding in this window.

Type in the code for OR gate given below and save it.

module OR_Gate(out,in1,in2); //OR_Gate is the name of the module

input in1,in2;

output out;

or OR_output(out,in1,in2);

endmodule
The next step is to compile the code. In the toolbar, select the compile icon to compile
it.

In transcript you will get the following message of successful compilation if there are no
mistakes in the code:

The next step is to simulate this code.

We have successfully implemented OR gate in Verilog. The next step is to check its
functionality by giving it some inputs as you have done in actual hardware by giving logic 1
(+5V) and logic 0 (0V). In Verilog, we write another module for this purpose which is called a
testbench or stimulus. Testbench or stimulus is also a module.

For, this purpose, add a new file to the existing project as shown below:

Now, follow the same steps as done before but select a new name for the testbench (like
testbench_OR in this case). Add the following code in this file. Save this file and compile it.

module testbench_OR;

reg IN1,IN2;

wire OUT;

OR_Gate t1(OUT,IN1,IN2);

initial

begin

#100 IN1=1'b0;IN2=1'b0;

#100 IN1=1'b0;IN2=1'b1;

#100 IN1=1'b1;IN2=1'b0;

#100 IN1=1'b1;IN2=1'b1;

end
Overview of Testbench:

module is a keyword.

testbench_OR is the name of our module. Notice it has No ports.

You Notice two new key words reg and wire. These are two of the data types in Verilog.
regGo
data type is used whenever
to Simulate>Start youAwant
Simulation. to store
Simulate a value
window and wire can be thought of the
appears
simple wire as in hardware. The details of them will come in further labs.

OR_Gate t1(OUT,IN1,IN2); Here we are calling our above module OR_Gate and giving it
a instant name t1 like we called or gate and gave it name OR_output.

initial and begin are two other keywords and their details will we explained later.
Anything after initial will be executed sequentially once.

#100 denotes a 100ns or whatever you timescale is defined. By default, in most of the
simulators it is in ns.

Expand the work option and select the name of your testbench (testbench_OR in this case).

WeFollowing
are giving the values
window to inputs
appears. SelectIN1 andtab
Wave IN2and
in awave
logical manner
window as we did in hardware
appears.
or while making truth table. You may give them in any order.

In objects window, select all the inputs and outputs and right click. Select Add Wave.
All the inputs and outputs get added to path name pane.

Set the simulation time 600 ns.

Now click run icon on top and we will see following output on wave window

PART (B)

BASICS OF VERILOG

1. INTRODUCTION
With the ever increasing complexity of modern circuits and digital systems, it is very difficult
(almost impossible) to design the system directly on hardware (by picking up the physical up
components and placing them right away). If somehow we are able to do that, then the
verification or testing of the system takes a lot of time and we have No before-hand method
to verify the functionality of our system unless we have physical systems in our hands.

In order to overcome this problem and several other issues, the computer languages for
designing and simulating circuits have been introduced so that we can verify the functionality
of our system and modify if needed before actually producing a physical hardware system.
These languages are termed as Hardware Description Languages (HDL) and fall in category of
low-level programming languages.

The two major versions of HDL are VHDL and Verilog HDL. We will be using the Verilog HDL
or Verilog in this course. The software we will be using for compiling and simulating Verilog is
ModelSim that we have already covered in part (a).
2. VERILOG MODELING LEVELS
In Verilog, there are different abstraction levels:

● Gate Level Modeling

(using the basic logic gates AND, OR, NOT, etc and their interconnections)
● Dataflow Modeling
(Defining the flow of data among different components of design using operators, no
interconnection between gates needed)
● Behavioral Modeling
(High level algorithm is implemented with little concern for the actual hardware much
like c code with if, case and loop statements)

The abstraction level increases as we move from Gate to Behavioral Modeling. There is yet
another abstraction level Switch Level Modeling in which the transistor level of hardware is
dealt with. It is a very complex level and is only used in critical applications or part of a system.
In this course, we will be dealing with the first 3 only.

The language also defines constructs that can be used to control the input and output of
simulation.

3. LEXICAL CONVENTIONS

a) Comments
Comments can be specified in two ways (exactly the same way as in C/C++):

● Begin the comment with double slashes (//).

● Enclose comments between the characters /* and */. This method allows to continue
comments on more than one line.

Example:

// Verilog code to display Hello World

b) Numbers
Number storage is defined as a number of bits, but values can be specified in binary,
octal, decimal or hexadecimal

Example

3’b001 // a 3-bit number

 c) Identifiers
Identifiers are user-defined words for variables, function names, module names, block
names and instance names. Identifiers begin with a letter or underscore (Not with a
number or $) and can include any number of letters, digits and underscores. Identifiers in
Verilog are case-sensitive.

Syntax:

Allowed symbols: ABCDE…..abcdef….1234567890_$

Not Allowed: anything else especially - @ & #

d) Operators
Operators are one, two and sometimes three characters used to perform operations on
variables.

Examples include >, +, ~, &, !=.

e) Verilog Keywords
These are words that have special meaning in Verilog. Some examples are assign,
case, while, wire, reg, and, or, nand, and module. They should not be used as
identifiers.

f) Delays
In Verilog delays can be introduced with #'num'

– # is a special character to introduce delay,

– 'num' is the number of ticks simulator should delay current statement
execution
Example:

#1 a = b : Delay by 1, i.e. execute after 1 tick

Module

Verilog is a modular language which means the basic component of a Verilog code is a module
or in other words our Verilog code consists of one or more modules and these modules call
each other to perform the desired functionality. The name of the module is just an arbitrary
label invented by the user. It does not correspond to a name pre-defined in a Verilog
component library. module is a Verilog keyword. This line defines the start of a new Verilog
module definition.

Endmodule:

The module definition is terminated by the Verilog keyword endmodule.

PRE-LAB TASK
1- Simulate the code given to you for OR gate and show the simulation results to your
instructor. Compare the simulation waveform results with the truth table in space
provided below.

2- Read the manual Getting Started with Verilog and answer the following questions.

a) HDL stands for

ANSWER:
HDL stands for hardware descriptive language

b) Two standard versions of HDL are?

ANSWER:
1. Modelsim
2. Vivado
c) Give the different levels of abstraction in Verilog HDL
ANSWER:
1. Behavioural level
2. Dataflow level.
3. Gate level.
4. Switch level

3- What do we understand by Simulation of Gates?

ANSWER:

Simulating gates typically refers to the process of using a computer program or software to
model the behavior and operations of digital logic gates in a virtual environment. Digital
logic gates are fundamental building blocks in digital circuit design and are used to perform
logical operations such as AND, OR, NOT, and others

Simulation of gates is a crucial aspect of digital circuit design and analysis for several
reasons:

 Functional Verification
 Timing Analysis
 Debugging
 Power Consumption Analysis
 Behavioral Exploration

Lab Tasks

1. Model and simulate the following gates in Verilog. Compare the simulation waveform
results with truth table. .
a) NAND
b) XNOR
WAVEFORM:

2. Model and simulate the following gates in Verilog using Gate Level Modeling.
a) OR using NAND gate
WAVEFORM: