EE2016-B- Fall 2021

數位系統導論
The Final Project- VHDL Codes:
25x8 ROM
Prof. E Ray Hsieh 謝易叡 助理教授

Prof. E Ray Hsieh Fall, 2021

(5 pts) Project 1: Please develop VHDL design of the 5-to-25
decoder
 Testbench: setup a set of input signals to test all the
outputs from m0 to m24
 The delay of inverter is 2ns. That of Other gates is 5ns.
m0
m1
In0 m2
m3
In1 m4
Decoder m5
5-to-25
In2 m6
In3 m7
In4 m8
………
In5
m22
m23
m24
(5 pts) Project 2: Please develop VHDL design of the 8-to-3
priority encoder
 Testbench: setup a set of m0 to m7 input signals to test all
the outputs from O0 to O2
 The delay of inverter is 2ns. That of Other gates is 5ns.

m 0 m 2 m 4 m 6 m8
25-to-5
Priority Encoder
O0 O1 O2
 m0 (10 pts) Project 3: Please
m1
In0 m2 develop VHDL design of the
m3
In1 m4 25-to-8 ROM array with 5-to-
m5 25x8
Decoder
5-to-25

In2 m6 25 DEC and 8-to-3 P-EDC.

In3 m
In4 m87 ROM  Testbench: The ROM
………

In5 can store 8 bit-streams,

m22
m23 each bitstream with 25
m24 m1 m3 m 5 m 7
bits. TA will provide you
m0 m 2 m 4 m 6 m 8 a 25x8 random truth
8-to-3 table and select 3 of
Priority Encoder them. You need to
The delay of inverter
O0 O1 O2 output with the correct
is 2ns. That of Other
gates is 5ns. output sets (O0O1O2).
• Demo deadline: Starting from pm 7:00, 14th, Jan., 2021
• Location: 原本上課教室地點。
• Demo Platform: EDA playground. Others are rejected.
• Codes: Your demo codes, including the VHDL design and
testbench codes, need to be printed on 3 pdf files (each project
for each separated pdf file) and uploaded to the new-ee-class.
( You can upload the code files before demo.)
• Copy is not allowed. The scores of all projects will be zero.