DC-to-DC

CORPORATION
Voltage Converter

CLM7660

FEATURES DESCRIPTION
• Converts +5V Logic Supply to ±5 System Calogic CLM7660 DC-to-DC converter will generate a negative
• Wide Input Voltage Range . . . . . . . . . . . . . . 1.5V to 10V voltage from a positive source. The CLM7660 generates -5V
• Low Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . 500µA in +5V digital systems and with two external capacitors, the device
• Efficient Voltage Conversion . . . . . . . . . . . . . . . . . 99.9% will convert a 1.5V to 10V input signal to a -1.5V to -10V level.
• RS232 Negative Power Supply
• Low Cost, Simple to Use
Applications include analog-to-digital converters, digital-to-analog
converters, operational amplifiers and multiplexers. Many of these
systems require negative supply voltages. The CLM7660 allows
APPLICATIONS
+5V digital logic systems to incorporate these analog components
• A-to-D Converters without an additional main power source. Lower part count, less real
• D-to-A Converters estate, ease of use are just a few of the benefits of the CLM7660.
• Multiplexers
• Operational Amplifiers ORDERING INFORMATION
Part Package Temperature
CLM7660CP 8 Pin DIP -40oC to +85oC
CLM7660DY 8 Pin SOIC -40oC to +85oC

PIN CONFIGURATION AND BLOCK DIAGRAM

NC 1 8 V+

CAP + 2 7 OSC
CLM7660
LOW
GND 3 6 VOLTAGE (LV)
CAP – 4 5 VOUT

NC = NO INTERNAL CONNECTION

1K-17

V + CAP +

8 2

7 VOLTAGE-
RC
OSC ÷2 LEVEL 4
OSCILLATOR
TRANSLATOR CAP –

6
LV
5
VOUT

INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK

GND 1B-35

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
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ABSOLUTE MAXIMUM RATINGS

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V Operating Temperature Range
LV and OSC Inputs D Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Voltage (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to (V++0.3V) Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC
for V+ <5.5V Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300oC
(V -5.5V) to (V++0.3V)
+
Static-sensitive device. Unused devices must be stored in conductive material.
for V+ <5.5V Protect devices from static discharge and static fields. Stresses above those
Current into LV (Note 1). . . . . . . . . . . . . . . 20µA for V+ >3.5V listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at
Output Short Duration (VSUPPLY ≤ 5.5V) . . . . . . . . Continuous these or any other conditions above those indicated in the operation sections of
Power Dissipation (Note 2) the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375mW

ELECTRICAL CHARACTERISTICS V+ = 5V, TA = +25oC, COSC = 0, Test Circuit (Figure 1), unless otherwise indicated.
SYMBOL PARAMETER MIN TYP MAX UNIT TEST CONDITIONS
+
I Supply Current - 80 180 µA RL = ∞

V+H1 Supply Voltage Range, High 3 - 6.5 V 0oC ≤ TA ≤ +70oC, RL = 10kΩ, LV Open
3 - 5 V -55oC ≤ TA ≤ +125oC, 10kΩ, LV Open

V+L1 Supply Voltage Range, Low 1.5 - 3.5 V Min ≤ TA ≤ Max, RL = 10kΩ, LV to GND
(DX Out of Circuit)

V+H2 Supply Voltage Range, High 3 - 10 V Min ≤ TA ≤ Max, RL = 10kΩ, LV Open

(DX In Circuit)
V+L2 Supply Voltage Range, Low 1.5 - 3.5 V Min ≤ TA ≤ Max, RL = 10kΩ, LV to GND
(DX In Circuit)
ROUT Output Source Resistance - 55 100 Ω IOUT = 20mA, TA = 25oC

- - 120 Ω IOUT = 20mA, 0oC ≤ TA ≤ +70 oC (C Device)

- - 300 Ω V+ = 2V, IOUT = 3mA, LV to GND

0 oC ≤ TA ≤ +70oC

fOSC Oscillator Frequency - 10 - kHz

PEF Power Efficiency 95 98 - % RL = 5kΩ

VOUT EF Voltage Conversion Efficiency 97 99.9 - % RL = ∞

ZOSC Oscillator Impedance - 1 - MΩ V+ = 2V

- 100 - kΩ V+ = 5V

NOTES:
1. Connecting any input terminal to voltages greater than C+ or less than GND may cause destructive latch-up. It is recommended that no inputs
from sources operating from external supplies be applied prior to "power up" of the CLM7660.
2. Derate linearly above 50oC by 5.5mW/ oC.

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
 CLM7660
CORPORATION

CIRCUIT DESCRIPTION

The CLM7660 is an excellent voltage doubler, the device has
all the characteristic with the exception of two inexpensive
10µF polarized electrolytic external capacitors. Figure 3
demonstrates the most effective means of using the device as
a voltage doubler. Capacitor C1 is charged to a voltage, V+,
for the half cycle when switches S1 and S3 are closed. (Note
Switches S2 and S4 are open during this half cycle.) During
the second half of the operation, switches S2 and S4 are
closed, with S1 and S3 open, thereby shifting capacitor C1
negatively by V+ volts. Charge is then transferred from C1 to
C2, such that voltage on C2 is exactly V+, asumming ideal
switches and no load on C2.
The four switches in Figure 3 are MOS power switches, S1 is
a P-Channel device, S2, S3 and S4 are N-Channel devices.
The major challenge with this approach while integrating the
switches, the substrates of S3 and S4 must always remain
reversed-biased with respect to their sources, but not so
much as to degrade their ON-resistances. In addition, at
circuit start-up, and under short circuit conditions (VOUT=V+),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this will result in
high power losses and probable device latch-up.
The above problem is eliminated in the CLM7660 by a logic
network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of S3 and S4
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the CLM7660 is an integral
part of the anti-latch-up circuitry. Its inherent voltage drop can
degrade operation at low voltages. To improve low-voltage
operation, the LV pin should be connected to GND, disabling
the regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latch-up proof operation
and prevent device damage.
When larger values of C1 and C2 are used, the CLM7660
approaches the above conditions for negative voltage
multiplication. Energy is lost only if the transfer of the charge
between capacitors if a change in voltage occurs. The energy
lost is defined by:
E=1/2C1 (V12-V22)
During the pump and transfer cycles V1 and V2 are the
voltages on C1. If the impedances of C1 and C2 are high at
the pump frequency (see Figure 3), compared to the value of
RL, there will be a substantial difference in voltages V1 and
V2. The most optimum selection would be to make C2 as
large as possible to eliminate output voltage ripple, and to
utilize a large value for C1 to achieve maximum efficiency of
operation.
OPERATIONAL RULES:
Never exceed maximum supply voltages.
Never connect LV terminal to GND for supply voltages over
3.5V.
Never short circuit the output to V+ supply voltages above
5.5V for extended periods; however, transient conditions
including start-up are acceptable.
For polarized capacitors, the + terminal of C1 must be
connected to pin 2 of the CLM7660 and the + terminal to of C2
must be connected to GND.
For high-voltage, elevated temperature applications add a
diode DX (reference Figure 1). The 1N914 diode is an
appropriate choice.

THEORETICAL POWER EFFICIENCY CONSIDERATIONS

In theory, a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON-resistance and
virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION

FIGURE 1. CLM7660 TEST CIRCUIT FIGURE 2. CHIP TOPOGRAPHY

IS
1 8
V+ GND C+
2 7 (+5)
IL C-
+ CLM7660
C1 C OSC *
3 6 VOUT
10µF
RL
4 5
D X** LV
VO
1K-11

C2
10µF
+
NOTES:
* For large values of COSC (>1000pf), the OSC V8
values of C1 and C2 should be increased to 100µF.
** DX is required for supply voltages greater than 6.5V at
-55o ≤ TA ≤ +70oC. Refer to performance curves for DIE SIZE = 81.5 x 57.5 (mm) 1L-05
additional information.

FIGURE 3. IDEALIZED SWITCHED CAPACITOR FIGURE 4. SIMPLE NEGATIVE CONVERTER

S1 S2
V+ V+

DX
C1 1 8

2 7 VOUT *
C1 + CLM7660
C2
3 6
10µF 10µF
+
GND C2 4 5
S3 S4
1K-05
V OUT = –VIN

*NOTES:
1. VOUT = -n V+ for 1.5V ≤ V+ ≤ 6.5V.
2. VOUT = -n (V+ –VFDX) for 6.5V ≤ V + ≤ 10V.

1K-12

FIGURE 5. PARALLELING DEVICES LOWERS OUTPUT IMPEDANCE

V+

1 8

2 7 1 8
CLM7660
C1 3 6 2 7 RL
CLM7660
4 "1" 5 DX
C1 3 6

DX 4 "n" 5

1K-06

C2
+

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
 CLM7660
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FIGURE 6. INCREASED OUTPUT VOLTAGE BY CASCADING DEVICES

V+

1 8

2 7 1 8
+ CLM7660
10µF 3 6 2 7
+ CLM7660
4 "1" 5 DX
10µF 3 6
DX
4 "n" 5 VOUT *

10µF
+

*NOTES:
1. VOUT = -n V+ for 1.5V ≤ V+ ≤ 6.5V. 1K-07
2. VOUT = -n (V+ –VFDX) for 6.5V ≤ V + ≤ 10V.

FIGURE 7. EXTERNAL CLOCKING FIGURE 8. LOWERING OSCILLATOR FREQUENCY

V+ V+ V+

1 8 1 8
1kΩ C OSC
CMOS
2 7 2 7
GATE
+ CLM7660 + CLM7660
DX DX
10µF 3 6 C1 3 6

4 5 VOUT 4 5 VOUT

10µF
C2
+
1K-08 +
1K-09

FIGURE 9. POSITIVE VOLTAGE MULTIPLIER FIGURE 10. COMBINED NEGATIVE CONVERTER

AND POSITIVE MULTIPLIER

V+
V+ VOUT
1 8 = –(V+– VF )
1 8
D1
2 7 VOUT = 2 7 C3
CLM7660 D2 (2V+ ) - (2VF ) CLM7660 D1 +
3 6 DX
3 6
+ +
4 5 C1 C2 4 5 VOUT =
+
C1 (2V + ) – (2VF )
1K-10
D2
+

C2 +
C4

1J-49

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
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FIGURE 11. POSITIVE VOLTAGE CONVERSION FIGURE 13A. FIXED POWER SUPPLY OPERATION
OF CLM7106 A-D
VOUT = –V –

1 8 +5V
+
2 7 10µF

C1 + CLM7660 1MΩ
3 6
10µF
4 5

1J-50 V – INPUT CA1004

1
+ 36
LCD V
REF IN
DRIVE
35
REF LO
FIGURE 12. SPLITTING A SUPPLY IN HALF 32
CLM7106 COM
3-1/2 DIGIT 31
V+
A-D IN HI
+ VIN
R L1 50µF 30
IN LO
1 8
8
2 V+
2 7
VOUT = + + 26
CLM7660 1MΩ 5 (–5V)
50µF 10m F CLM7660
+ – 3 6
V –V
4
2
100k Ω 100k Ω 4 5
3
R L2
+ 10m F 1K-02
+
50µF
V–
1K-01

FIGURE 13B. NEGATIVE POWER SUPPLY GENERATION FOR 3 1/2 DIGIT A-D

2 4 +5V

8
CLM7660

3 5
1
V+ 36
REF IN
+ 26 35
V– REF LO
32
COM
CLM7107A
31
3-1/2 DIGIT IN HI
LED
A-D VIN
DRIVE
30
IN LO
GND
COMMON ANODE
LED DISPLAY 21

1K-03

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
 CLM7660
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FIGURE 14. CLM7660 SUPPLIES -5V FOR CONVERTERS IN MICROPROCESSOR-CONTROLLED

DATA ACQUISITION SYSTEMS

10µF
+

+5V 2 4
8 3
CLM7660

5
–5V + 6502 µP BUS
20kΩ +5V
10µF
11 1 20 DATA BUS
CA1004
V +
V – 13 2
100kΩ B1 PA0
2 14 3 D0
REF IN B2
15 4
PA1 .. ADDRESS
3 ANALOG B4 PA2 .. BUS
+
100kΩ
10
COMMON B8
16 5
PA3 ..
+ INPUT 27 6
ANALOG OR PA4 D7
0.1µF 9 28 7
INPUT – INPUT UR PA5
– 7 23 8 CONTROL
REF CAP – POL PA6 BUS
12 9
1µF 8
REF CAP+
D5
26 40
PA7 ..
RS0

4 STROBE CA1 RS3

INT OUT 25 39
1µF RUN/HOLD CA2 CS1
0.47µF ADDRESS
5 DECODER
AZ IN CS2
20
D1 NC
6 19
BUFF OUT D2 NC PB0-PB7
100kΩ 18
D3 NC RESET
17 R/W
4-1/2 DIGIT D4 NC SY6522
A-D=7135 21 O2
BUSY NC
IRQ
DIGITAL 22 CLOCK
CLOCK IN INPUT VSS
GND
f = 120kHz
24 1
1K-04

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
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PERFORMANCE CURVES

OUTPUT VOLTAGE
vs OUTPUT CURRENT

0V
2V @ 5V EFFICIENCY vs
–1V OSCILLATOR FREQUENCY (5mA)
OUTPUT VOLTAGE

100% 92
–2V 90% 95
–3V 5V
–4V s
N v D)
300µA TIO A
–5V S U MP NO LO
ON NCY (
C
–6V ER UE
OW FREQ
200µA VP
–7V @ 5 ATOR
LL
OSCI
–8V 10V 100µA
–9V 7.4 12.6
–10V
10 20 30 40 50 60 70 1 5 10
OUTPUT CURRENT (mA) 1K-13 OSCILLATOR FREQUENCY (kHz) 1K-14

OUTPUT RESISTANCE
vs SUPPLY VOLTAGE
OUTPUT RESISTANCE

200Ω

100Ω

0 5V 10V
INPUT VOLTAGE 1K-15

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025