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  • ) Ljxuh 6Wr67Lplqj'Ldjudp: Electrical Characteristics

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    ady putra
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    This document contains a timing diagram that outlines the sequence and timing of electrical signals between the PCH, CPU, and board during the S5 to S0 transition. Key signals include SLP_S5#, SLP_S4#, SLP_S3#, SLP_A#, VccASW, PROCPWRGD, PWROK, APWROK, DRAMPWROK, SUS_STAT#, and PLTRST#. The diagram shows the order and relative timing of when each signal is asserted during the power on and boot up process.

    Original Description:

    dataheet

    Original Title

    www.teknisi-indonesia.com.hm65 S5-S0

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    This document contains a timing diagram that outlines the sequence and timing of electrical signals between the PCH, CPU, and board during the S5 to S0 transition. Key signals include SLP_S5#, SLP_S4#, SLP_S3#, SLP_A#, VccASW, PROCPWRGD, PWROK, APWROK, DRAMPWROK, SUS_STAT#, and PLTRST#. The diagram shows the order and relative timing of when each signal is asserted during the power on and boot up process.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    6 views1 page

    ) Ljxuh 6Wr67Lplqj'Ldjudp: Electrical Characteristics

    Uploaded by

    ady putra
    This document contains a timing diagram that outlines the sequence and timing of electrical signals between the PCH, CPU, and board during the S5 to S0 transition. Key signals include SLP_S5#, SLP_S4#, SLP_S3#, SLP_A#, VccASW, PROCPWRGD, PWROK, APWROK, DRAMPWROK, SUS_STAT#, and PLTRST#. The diagram shows the order and relative timing of when each signal is asserted during the power on and boot up process.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 1

    Electrical Characteristics

    )LJXUH 6WR67LPLQJ'LDJUDP

    Source Dest Signal Name

    PCH Board SLP_S5#

    PCH Board SLP_S4# t203

    PCH Board SLP_S3# t204

    Could already be high before this sequence begins (to support M3),
    PCH Board SLP_A# but will never go high later than SLP_S3#

    PCH Board SLP_LAN# Could already be high before this sequence begins (to support WOL),
    but will never go high later than SLP_S3# or SLP_A#

    Board PCH VccASW


    t229

    Board PCH Vcc


    PROCPWRGD

    Serial VID
    CPU CPU VRM CPU SVID Load

    V_vid
    Board CPU VccCore_CPU

    CPU VRM PCH SYS_PWROK

    t205
    Board PCH PWROK t206
    t207
    Board PCH APWROK APWROK may come up earlier
    than PWROK, but no later

    PCH CPU DRAMPWROK t230

    25 MHz
    Board PCH stable
    Crystal Osc
    PCH
    PCH Board stable
    Output Clocks
    PCH CPU PROCPWRGD t208
    t209

    PCH Board SUS_STAT# t210

    Assumes soft strap programmed to start at


    PROCPWRGD - expected setting for SNB
    CPU PCH THRMTRIP# ignored honored

    PCH CPU/Board PLTRST# t211

    _A s
    E
    NE ite
    CK
    SE DM N
    DO wr
    RE V DO
    _
    CP SK ET
    T
    SE

    T_
    ex ES
    U_ U
    P_
    ST ing

    Fl R
    U_
    RA
    ain

    CP
    Tr

    PCH CPU DMI

    Datasheet 351

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