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NE567
NE567
NE567
TOP VIEW
FEATURES F Package
• Wide frequency range (.01Hz to 500kHz)
• High stability of center frequency OUTPUT 1 14 GND
BLOCK DIAGRAM
R2
3.9k
INPUT 3 PHASE 2
V1 DETECTOR
R1 LOOP
5
CURRENT LOW
CONTROLLED AMP PASS
6 OSCILLATOR FILTER
C1 C2
R3
+
8
QUADRATURE – AMP
PHASE RL
DETECTOR VREF
+V
7 1
C3 OUTPUT
FILTER
R41
R5 R6 R11 R2 R39 R3
R9 R10 R21 5k R42
10k 4.7k
1
Q8
R7
R26 Q61 Q62 Vref Q55 Q58
Q12
EQUIVALENT SCHEMATIC
R48 R49
Q13 2
Q19 B –V
R1 Q59 Q60
–V Q50 C
C2
R19
–V R36 R40 R43
R20 R22 RL
Tone decoder/phase-locked loop
Q6 –V
6
R12 R13 B
C1
EF R45
Q34 Q35 Q36 Q37 F Q47 Q46 Q45 Q44
Q22 Q23
404
R32
Q7
R33
Q30 A E
B R29 R30 Q61
R48 Q40
R14 21k
3 Q33
–V R48
Cc Q32 21k
A
Q43
R15 R16 R23 Vi Q42 Q62
Q3 Q9 R17
R26 R27
Q2 Q25 Q24
R4
Q5
C
Q26
Q30 R34
Q27 Q28
Q41
Q40 B
Q29 B Q31 B Q38
7
NE/SE567
Product specification
Philips Semiconductors Linear Products Product specification
ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
8-Pin Plastic SO 0 to +70°C NE567D 0174C
14-Pin Cerdip 0 to +70°C NE567F 0581B
8-Pin Plastic DIP 0 to +70°C NE567N 0404B
8-Pin Plastic SO -55°C to +125°C SE567D 0174C
8-Pin Cerdip -55°C to +125°C SE567FE 0581B
8-Pin Plastic DIP -55°C to +125°C SE567N 0404B
DC ELECTRICAL CHARACTERISTICS
V +=5.0V; TA=25°C, unless otherwise specified.
SYM-
PARAMETER TEST CONDITIONS SE567 NE567 UNIT
BOL
Min Typ Max Min Typ Max
Center frequency1
fO Highest center frequency 500 500 kHz
fO Center frequency stability2 -55 to +125°C 35 ±140 35 ±140 ppm/°C
0 to +70°C 35 ±60 35 ±60 ppm/°C
fO Center frequency distribution 1 -10 0 +10 -10 0 +10 %
fO 100kHz
1.1R 1C 1
(Hz * µ F)
300 15 106
LARGEST BANDWIDTH — % OF O
250
f
INPUT VOLTAGE — mVrms
200 10 105
150
100 5 104
50
C3
C2
0 0 103
0 2 4 6 8 10 12 14 16 0.1 1 10 100 1000 0 2 4 6 8 10 12 14 16
BANDWIDTH — % OF fO CENTER FREQUENCY — kHz BANDWIDTH — % OF fO
1000 1.0
25
0.9
15
100 0.5
10 0.4
QUIESCENT 50
CURRENT 0.3 IL = 30mA
5 BANDWIDTH 0.2
30
LIMITED BY (C2)
0.1
0 10 0
4 5 6 7 8 9 10
1 5 10 50 100 –75 –25 0 25 75 125
BANDWIDTH — % OF fO
SUPPLY VOLTAGE — V TEMPERATURE — °C
0.5 0.5 0
(1)
0 0 –2.5
1.0 15.0 14
0.9 12
0 12.5
0.8
BANDWIDTH — % OF f O
10
0.7 10.0
8
–100 t 0.6
O
ń V * %ń V 7.5
t 0.5
O 6
0.4
–200 5.0 4
∆t = 0°C to 70°C 0.3
0.2 2
2.5
–300 0.1 BANDWIDTH AT 25°C
4.5 5.0 5.5 6.0 6.5 7.0 0
0
1 2 3 4 5 10 20 40 100 –75 –25 0 25 75 125
SUPPLY VOLTAGE — V
CENTER FREQUENCY — kHz TEMPERATURE – °C
BW [ 1070 Ǹ VI
fO C2
in % of f O
1. Select R1 and C1 for the desired center frequency. For best
temperature stability, R1 should be between 2K and 20K ohm,
and the combined temperature coefficient of the R1C1 product
should have sufficient stability over the projected temperature
VI v 200mV RMS
range to meet the necessary requirements.
Where
2. Select the low-pass capacitor, C2, by referring to the Bandwidth
VI=Input voltage (VRMS)
versus Input Signal Amplitude graph. If the input amplitude
C2=Low-pass filter capacitor (µF)
Variation is known, the appropriate value of fO ⋅ C2 necessary to
give the desired bandwidth may be found. Conversely, an area of
operation may be selected on this graph and the input level and
PHASE-LOCKED LOOP TERMINOLOGY CENTER C2 may be adjusted accordingly. For example, constant
FREQUENCY (fO) bandwidth operation requires that input amplitude be above
The free-running frequency of the current controlled oscillator (CCO) 200mVRMS. The bandwidth, as noted on the graph, is then
in the absence of an input signal. controlled solely by the fO ⋅ C2 product (fO (Hz), C2(µF)).
Lock Range
The largest frequency range within which an input signal above the
threshold voltage will hold a logical zero state on the output.
TYPICAL RESPONSE saturates; its collector voltage being less than 1.0 volt (typically
0.6V) at full output current (100mA). The voltage at Pin 2 is the
phase detector output which is a linear function of frequency over
INPUT
the range of 0.95 to 1.05 fO with a slope of about 20mV per percent
of frequency deviation. The average voltage at Pin 1 is, during lock,
a function of the in-band input amplitude in accordance with the
OUTPUT transfer characteristic given. Pin 5 is the controlled oscillator square
wave output of magnitude (+V -2VBE)≅(+V-1.4V) having a DC
NOTE: average of +V/2. A 1kΩ load may be driven from pin 5. Pin 6 is an
RL = 100Ω exponential triangle of 1VP-P with an average DC level of +V/2. Only
Response to 100mVRMS Tone Burst high impedance loads may be
OUTPUT OUTPUT
(PIN 8) V+
7% 14% BW
0
VCE (SAT) < 1.0V
INPUT
NOTES: 3.9V
S/N = –6dB
RL = 100Ω LOW PASS
Noise Bandwidth = 140Hz FILTER 3.8V
(PIN 2)
567 8
1 R1
f
O R 1C 1
R2
6
2 7 1
C1 C2
C3
LOW OUTPUT
PASS FILTER
FILTER
Figure 1.
cause supply voltage fluctuations which could, for example, shift the
V+ detection band of narrow-band systems sufficiently to cause
momentary loss of lock. The result is a low-frequency oscillation into
and out of lock. Such effects can be prevented by supplying heavy
R
load currents from a separate supply or increasing the supply filter
567 1 567 1 capacitor.
C3 R
C3
SPEED OF OPERATION
DECREASE INCREASE Minimum lock-up time is related to the natural frequency of the loop.
SENSITIVITY SENSITIVITY The lower it is, the longer becomes the turn-on transient. Thus,
maximum operating speed is obtained when C2 is at a minimum.
V+
When the signal is first applied, the phase may be such as to initially
DECREASE
RA SENSITIVITY drive the controlled oscillator away from the incoming frequency
RB
567 1 rather than toward it. Under this condition, which is of course
2.5k
50k unpredictable, the lock-up transient is at its worst and the theoretical
INCREASE
C3 SENSITIVITY
RC minimum lock-up time is not achievable. We must simply wait for the
1.0k transient to die out.
SILICON
DIODES FOR The following expressions give the values of C2 and C3 which allow
TEMPERATURE highest operating speeds for various band center frequencies. The
COMPENSATION
(OPTIONAL) minimum rate at which digital information may be detected without
information loss due to the turn-on transient or output chatter is
Figure 3. Sensitivity Adjust about 10 cycles per bit, corresponding to an information transfer rate
connected to pin 6 without affecting the CCO duty cycle or of fO/10 baud.
temperature stability. V+ V+
V+ V+
RA
RL 200 TO 1k
OPERATING PRECAUTIONS RL
A brief review of the following precautions will help the user achieve 567 8 567 8
the high level of performance of which the 567 is capable. 1 1 Rf RL
Cf Rf 10k
1. Operation in the high input level mode (above 200mV) will free 10k
1
C3
the user from bandwidth variations due to changes in the in-band Rf* 567 8
signal amplitude. The input C3 10k
stage is now limiting, however, so that out-band signals or high RA
*OPTIONAL - PERMITS 200 TO
noise levels can cause an apparent bandwidth reduction as the 1k
LOWER VALUE OF Cf
inband signal is suppressed. Also, the limiting action will create
in-band components from sub-harmonic signals, so the 567
Figure 4. Chatter Prevention
becomes sensitive to signals at fO/3, fO/5, etc.
V+
2. The 567 will lock onto signals near (2n+1) fO, and will give an
output for signals near (4n+1) fO where n=0, 1, 2, etc. Thus,
signals at 5fO and 9fO can cause an unwanted output. If such R
signals are anticipated, they should be attenuated before
567 2 567 2
reaching the 567 input.
C2 R
3. Maximum immunity from noise and out-band signals is afforded C2
LOWERS fO RAISES fO
in the low input level (below 200mVRMS) and reduced bandwidth
operating mode. However, decreased loop damping causes the
worst-case lock-up time to increase, as shown by the Greatest V+
Number of Cycles Before Output vs Bandwidth graph. LOWERS fO
RA
4. Due to the high switching speeds (20ns) associated with 567 567 1 RB
2.5k
operation, care should be taken in lead routing. Lead lengths 50k
C2
should be kept to a minimum. The power supply should be RC RAISES fO
RAISES fO
adequately bypassed close to the 567 with a 0.01µF or greater 1.0k
capacitor; grounding paths should be carefully chosen to avoid SILICON
ground loops and unwanted voltage variations. Another factor DIODES FOR
TEMPERATURE
which must be considered is the effect of load energization on COMPENSATION
(OPTIONAL)
the power supply. For example, an incandescent lamp typically
draws 10 times rated current at turn-on. This can be somewhat
Figure 5. Skew Adjust
greater when the output stage is made less sensitive, rejection of
third harmonics or in-band harmonics (of lower frequency
signals) is also improved.
250 Rf
20k
CA C3
0.5k 0.9k 1.4k 1.9k 2.5k 3.2k 4.0k
200 UNLATCH
INPUT VOLTAGE MV — RMS
10k V+
150
20k V+
RL
100
100k 567 8
UNLATCH
1
50
R
Rf
20k
0 C3
0 2 4 6 8 10 12 14 16
DETECTION BAND — % OF fO
NOTE:
V+ CA prevents latch-up when power supply is turned on.
RA
50k Figure 7. Output Latching
PIN 2 RB
567 R BR
C
R + R )
A RB ) R
C
C2 RC
OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
NOTE:
130
f
ǒ 10k R) RǓ t C2 t
f
ǒ
1300 10k )
R
R
Ǔ
O O
Adjust control for symmetry of detection band edges
about fO.
Figure 6. BW Reduction
TYPICAL APPLICATIONS
+
R3
567 DIGIT
897Hz 1
R2
R1 C3 + 2
C1 C2
3
567
770Hz 4
+ 5
6
567
852Hz 7
8
+
9
567
941Hz 0
+
*
567
1209Hz
NOTES: +
Component values (Typical)
R1 = 26.8 to 15kΩ
567
R2 = 24.7kΩ 1336Hz
R3 = 20kΩ
C1 = 0.10mF
C2 = 1.0mF 5V +
C3 = 2.2mF 6V
C4 = 250µF 6V
567
1477Hz
Touch-Tone Decoder
R1 C1 5741
1:1
2.5kΩ
fO ≈ 100kHz
C2
.006
Precision VLF
C1 AUDIO OUT
C3
(IF INPUT IS
0.004mfd .02 FREQUENCY +V
MODULATED)
5 6 2 1
+V
R1
INPUT SIGNAL
(>100mVrms)
20k C2
f1 C1 C3
3 567 8
5 6 2 1
RL
R1
3 567 8
INPUT NOR VO
CHANNEL +V 5 6 2 1
C1 C2 C3
OR RECEIVER
R’1 130
20k CȀ 2 + C 2 + (mfd)
f
O
f2 CȀ 1 + C 1
3 567 8
RȀ 1 + 1.12R 1
5 6 2 1 C’1 C’2
R’1
24% Bandwidth Tone Decoder
OUTPUT
(INTO 1k
OHM MIN.
C’1 C’2 C’3 100mv (pp) LOAD)
SQUARE OR 3 567 5
50mVRMS
SINE INPUT
2 6 f2
Dual-Tone Decoder +90°
R1 PHASE
SHIFT
C2 C1
NOTES:
R2 = R1/5
Adjust R1 so that φ = 90° with control midway.
+
+
RL
RL 567
3 567 8 567 8 2 6 5
80°
2 6 5 2 6 5 3 VCO
TERMINAL
CONNECT PIN 3 fO (±6%)
TO 2.8V TO R1
INVERT OUTPUT RL > 1000Ω
R1 RL > 1000Ω R1
10k
C2 C1
C2 C1
CL
+
567
RL
6 5
567 8 RL OUTPUT
567 8
3 6 5 1
1kΩ (MIN)
2 6 5 1
10kΩ
VCO
TERMINAL
(±6%) R1
100kΩ
R1
C2 C1
DUTY
C1 C1 CYCLE
ADJUST