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Exercise 1
Exercise 1
g) What is the range of unsigned numbers stored in 16 bits in standard binary and in BCD?
0 – 9999 (0000 0000 0000 0000 – 1001 1001 1001 1001)
h) Binary addition can be fixed by adding 0110 (6) to any 4 bit BCD result, whenever it is
10 or larger, and then bringing the carry to the next digit. Show this for some
examples.
5 + 5 (decimal) = 0101 + 0101 (binary) = 0101 + 0101 (BCD) = 0001 0000 (1010 + 0110) (BCD)
A Y0 Y1 Y2 Y3
0 0 1 0 1
1 0 0 1 1
a) Identify the NOT and Buffer from Y0 – Y3.
Not = Y1
Buffer = Y2
b) Why are the other two outputs not of interest to make as a separate gate IC?
One is always on, the other always off.
The 2-input gate will have a truth table with 4 rows. In each row the output can be 0 or 1.
This leads to 2^4 = 16 different truth tables. Inputs are A and B, and the output can be called
Y0 – Y15.
c) Identify the NAND, NOR, AND, OR, XOR, and XNOR gate from Y0 – Y15.
NAND = Y7.
NOR = Y1.
AND = Y8.
OR = Y14
XOR = Y6.
XNOR = Y9.
d) Why are the other outputs not of interest to make as a separate gate IC?
Because they can be made with the other gates.
The 3-input gate will have a truth table with 8 rows. In each row the output can be 0 or 1.
e) How many different truth tables can be made?
256 (Y0 – Y255)
f) Which output columns would you suggest are useful to make as a separate gate? Can
you identify some of them with YN?
Y1 = NOR
Y126 =XOR
Y127 = NAND
Y128 = AND
Y129 = XNOR
Y254 = OR
The 4-input gate will have a truth table with 16 rows. In each row the output can be 0 or 1.
g) How many different truth tables can be made?
65536 (Y0 – Y65535)
h) Which output columns would you suggest are useful to make as a separate gate? Can
you identify some of them with YN?
Y1 = NOR
Y32766 =XOR
Y32767 = NAND
Y32768 = AND
Y32769 = XNOR
Y65534 = OR
b) Using 2 input NOR gates: build a NOT gate and 2 input OR, AND, and NAND gates
c) Using 2 input AND gates: build 3 input and 4 input AND gates
d) How would you build 3 input and 4 input NAND gates (using only 2-input AND and
NAND gates)?
e) Using 2 input OR gates: build 3 input and 4 input OR gates
f) How would you build 3 input and 4 input NOR gates (using only 2-input OR and NOR
gates)?
g) Build a 2 input XOR and XNOR gate using any other 2 input gates
NOT:
NAND:
NOR: