A Multilevel Inverter Topology With Reduced

Number of Switches
Muhammad Fayyaz Kashif and Amir Khurrum Rashid
Department of Electrical Engineering
Namal College
Mianwali, Pakistan
fayyaz.kashif@namal.edu.pk

Abstract — A novel multilevel inverter topology with reduced photovoltaic systems [6], [14]. Multilevel inverters exhibit
number of power switches is proposed. This new topology is superior characteristics as compared to traditional two level
based on a combination of conventional diode clamped and H- inverters. Due to higher number of voltage levels, output
bridge topologies. The proposed idea has been validated through waveforms of multilevel inverters contains fewer harmonics
simulation results. essentially reducing the filter size or for some applications
filter can be eliminated completely. Also, multilevel inverters
Keywords— Multilevel Inverter, H-bridge, Motor Drives operate at lower switching frequencies which decrease the
switching losses and hence increase their efficiency. Moreover,
I. INTRODUCTION multilevel inverters provide multiple DC links which may help
Sunlight is a widely available cheap source of energy, which in modular designs. Separate DC link voltage control makes
them suitable for solar applications and separate tracking of
can be converted to electricity through photovoltaic cells [1].
maximum power points of solar panels is possible [6].
Solar panels produce direct current (DC) electricity whereas
Multilevel inverters require a large number of power
existing electricity infrastructure and electric appliances
semiconductor switches to generate the output voltage with
operate on alternating current (AC) electricity. DC/AC power
higher number of levels. Power switches require gate drivers
converters, termed as inverters, are used for this conversion
and protection circuits, which makes overall circuit expensive.
making electricity coming from solar panels useable [2].
To overcome this issue, a number of hybrid multilevel
Conventionally, two level inverters have been used for grid-
inverters have been reported with the focus on getting
integration of solar system. However, these inverters give
maximum number of voltage levels with minimum number of
pulsating waveforms of current and voltage at their outputs and
power semiconductor switches and supporting circuit elements
filters are needed to get fundamental frequency sinusoidal
[15]–[20].
waveforms. Efficiency of this process is low since energy
A very comprehensive summary of the characteristics of
contained in the higher order harmonics is wasted. Keeping in
commonly used multilevel inverter topologies has been
view higher costs and lower efficiencies of solar systems, it is
presented in [14]. It also proposes a new multiple transformer
important to devise new inversion methodologies to make
based topology for standalone photovoltaic applications.
compact, cheap and efficient solar systems.
However, transformer based implementation can be costly.
Many multilevel inverters topologies have been proposed
Gupta et. al., [15] compared classical and reduced device count
in technical literature [3]–[8]. Neutral point clamped or diode
topologies of multilevel converters and concluded that in
clamped [9], the flying capacitor or capacitor clamped [10] and
process of reducing device count many compromises have to
the cascaded H-bridge [11] topologies are considered as the
be made, which include higher voltage rating of power
three basic multilevel topologies. The neutral point clamped
switches and loss of modularity etc. Authors in [17] and [18]
inverters were initially proposed for motor drive applications.
proposed new multilevel inverter topologies with reduced
They greatly reduce odd harmonic amplitudes compared with
number of device count. The proposed topologies are hybrid
fundamental. DC link capacitor voltage unbalancing and
combination of modular submultilevel converter and a full-
requirement of large number of clamping diodes for higher
bridge converter. The main drawback of these topologies is
number of voltage levels are the major disadvantages of this
that they use bidirectional power switches. Bidirectional power
topology. The capacitor clamped topologies find applications
switches require complex drive circuitry and their
in transformer-less systems [12], but these topologies require a
implementation is not cost effective.
large number of electrolytic capacitors which decreases their
Most of the existing multilevel topologies claim to reduce
reliability. Cascaded H-bridge topologies are more suitable for
total number of device count. This objective can be misleading
getting higher number of voltage levels. They also have
since the devices used in a multi-level inverter vary
modular designs and simple control techniques. But they
significantly in terms of their costs and complexities. Diodes
require separate DC sources.
and capacitors are cheap, and offer an easy placement in
Multilevel inverters were first introduced for high power
printed circuit boards. On the other hand, power switches are
and high voltage applications [13], but in recent years, they
expensive, and a careful implementation of transistor gate
have found applications in low power systems especially
drivers is required for their operation. Additional elements,

978-1-4673-8753-8/16/$31.00 ©2016IEEE
e.g., snubbing network, and resonant circuits [2] may also be
required in some applications of these power switches. Based
on that, an optimization for the reduced number of total device
count as carried out may be misleading and less useful when
one goes for a practical implementation. Instead, it appears
more prudent to target a reduced number of switches only,
when we seek an optimum implementation of multi-level
inverters.
We propose a multilevel inverter topology, which results in
a minimum number of switches, especially when the required
number of voltage levels is large. Our topology is a
combination of diode-clamped and H-bridge circuits. Detailed
description, circuit, and results of our proposed scheme are
presented in the following paragraphs.
signals of the switches. Similarly Q1 - Q4 represent gating
signals of H-bridge. The four switches of H-bridge are
operated at the fundamental frequency of the output voltage.
In the proposed topology, k power switches are required
to generate k levels staircase waveform Vbus. Four additional
switches of H-bridge inverter are used to get staircase ac
waveform Vac of 2 k + 1 levels. Effectively, to generate
2 k + 1 level staircase voltage ac waveform, only k + 4
power switches, k capacitors and k diodes are needed which
results in overall lesser device count than an existing multilevel
topology, to the best of our knowledge.

Fig. 1: Our proposed topology of multilevel inverter.

II. DESCRIPTION OF THE PROPOSED STRUCTURE

Fig. 1 shows the proposed multilevel inverter topology.
Here, a simple variation of diode clamped multilevel inverter is
used to generate a staircase waveform. An H-bridge is used to
get an alternating signal with both positive and negative
polarities. Capacitors are used to divide the DC link voltage
into k distinct levels. These capacitor voltages are then added
and subtracted by operating the power switches to generate
2 k + 1 level staircase voltage waveform. Diodes are used with
each power switch in reverse blocking mode. Fig. 2 explains
Fig. 2: Output waveform and states of various switches.
the working principle of the proposed topology, where Vbus is
the DC bus voltage, Vac is the ac output voltage, Vac_1 is the
fundamental component of Vac. S1 - Sk represent the gating
 III. RESULTS AND DISCUSSIONS Table 1: Comparison of switches required for a 33-level inverter

The staircase output waveform for k separate DC sources No. Circuit Topology Number of Power Switches
each having amplitude of Vdc can be expressed by the 1 Diode-Clamped 32
following equation as [21]
2 Cascaded H-Bridges 64
∞
sin( nω0t ) 3 Our Circuit 20
∑ ⎡⎣cos(nα ) + cos(nα ) + ... + cos(nα )⎤⎦
4Vdc
Vo (t ) = 1 2 k
π n=1,3,5,..
n
(1) Table I compares the power switches required by our
Magnitudes of the Fourier coefficients can be calculated as topology with those of the conventional diode-clamped and
4V cascaded H-bridge structures for a 33-level inverter. This
Vn = dc [cos( nα1 ) + cos(nα 2 ) + ... + cos(nα k )] (2) comparison clearly demonstrates the superiority of our
nπ
proposed structure.
It should be pointed that the four switches used in the H-
Based on (1)-(2), we have studied a 33 level inverter of the bridge of our topology, require a large voltage rating. This is
proposed multilevel topology. To generate 220 V RMS AC unlike the switches used in conventional diode-clamped and
waveform, we have considered a DC bus of 320 V. An cascaded H-bridge topologies, where all the switches are of
inductive resistor load is powered through this inverter to the same low voltage ratings. Although cost of a switch
analyze the current and voltage waveforms. Fig. 3 and 4 shows increases with its voltage rating, the required driver circuits
the simulated dc bus voltage, current, ac output voltage and
usually remain the same. Based on that, a significant
current waveforms at 50 Hz operating frequency which
advantage in terms of cost and easy implementation is still
confirms the operating principle of the proposed topology
explained in section II. Harmonic spectrum of output AC offered by our proposed structure.
voltage and current waveforms is shown in Fig. 5. AC output CONCLUSION
waveforms contain only odd harmonics at multiples of the
fundamental frequency. Output current has small harmonic A new multilevel inverter topology has been proposed. The
contents even with very small load inductance. proposed topology is a hybrid combination of conventional
Ibus Vbus
diode clamped and H-bridge converters. It can be a good
choice for photovoltaic applications where multiple separate
300 DC sources are available. This paper has demonstrated the
200 concept and working principles of the proposed topology. A
detailed analysis of efficiency and practical implementation is
100
still required to fully verify the advantages of this new circuit.
0
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