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S.E. (Computer Engineering)
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DIGITAL ELECTRONICS AND LOGIC DESIGN
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(2019 Pattern) (Semester - I) (210245)
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Time : 1 Hour]
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Instructions to the candidates :
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3) Assume suitable data if necessary.
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Q1) a) Simplify the expression F(A,B,C,D) = m (3,4,5,7,9,13,14,15) using
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the K-map method. [5]
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b) Simplify the expression F(A,B,C,D) = π M (0,1,4,5,6,8,9,12,13,14) using
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Y(A,B,C,D) = m (0,1,3,7,8,9,11,15).
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F(A,B,C,D) = m (2,4,5,7,10,14).
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b) Design 4 bit binary to gray code converter circuit using logic gates. [5]
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Q4) a) Explain the rules for BCD addition with suitable example and Design one
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b) How will you implement full adder using half adder? Explain with circuit
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diagram. [5]
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Q5) a) Explain look Ahead carry generator in detail. [5]
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b) Simplify the expression F(A,B,C,D) = m (1,3,7,11,15)+d(0,2,5) using
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the K-map method. [5]
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Q6) a) What do you mean by parity? Design 3 bit parity generator circuit using
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even parity bit.
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b) Minimize the following expression using the K-map with minimum
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hardware.
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Y = m (1,5,6,7,11,12,13,15)
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