Alphacore is a provider of high-performance microelectronics for the needs of demanding segments

including scientific research, aerospace, defence, medical imaging, and homeland security.

We are headquartered in Tempe, Arizona, USA. Alphacore is a young, rapidly growing technology
company: we were identified as one of the fastest growing companies in the US on last year’s Inc 500
Magazine list! We were also ranked #6 in the country for Top Computer Hardware Companies
category! https://www.alphacoreinc.com

This position involves extensive hands-on physical implementation of high-performance CPU cores
and multi-core clusters using industry standard EDA tools and standard libraries. In addition to
driving performance, power, and area optimization and closure in collaboration with designers, the
position will provide opportunities to develop and improve physical implementation flows towards
supporting key customers to meet final SoC level integration.

Minimum Qualifications:

● Bachelors/Masters in Electronics/Electrical/Computer Engineering with 5+ years of industry

experience with a focus on physical design

● Excellent understanding of synthesis, floor planning, place and route, clock-tree synthesis, timing
closure, DFT, IR/EM, and physical verification

● Scripting experience in Python/Perl/TCL/Shell and EDA tool specific scripting

● Strong analytical and problem-solving skills

● Self-motivated with excellent communication and presentation skills, and ability to collaborate well
locally and with global team

Preferred Qualifications:

● Experience with physical implementation of High Speed Serdes (PMA digital, PCS), SoC's and Test
chip's in latest process nodes (Both in FinFet and Bulk CMOS).

Roles and Responsibilities:

● Take RTL designs through synthesis, Place Route, and timing/power/DFT

closure loop

● Work closely with block level and top-level designers to achieve target

performance, power, and area specifications

● Work with multiple EDA tool flows (such as Cadence and Synopsys etc.) and vendors to create
stable implementation flows

for customers to integrate the IP into their SoC

● Support physical implementation of IP during customers SoC

integration/implementation phase