1

SEQUENTIAL CIRCUITS
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Introduction:
• Recollecting the concepts of combinational circuits:

Fig. 1 Combinational circuit

• Fig.1 shows combinational circuit, outputs at any time depends only on the
present combination of inputs at that point of time (here, disregarded the past
state of the inputs)

• The logical function performed by a combinational circuit is fully defined by a

set of Boolean expressions
 3

• Sequential logic circuits, comprises both logic gates and

memory elements such as flip-flops.

• Owing to the presence of memory elements, outputs in a

sequential circuit depends upon not only the present
inputs but also the past state of inputs.

• Sequential circuits are essentially combinational circuits

with feedback.

• The block diagram of a generalised sequential circuit is

shown in Fig. 2.
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Fig. 2 Sequential circuit

• It consists of combinational logic which has two sets of inputs

and two sets of outputs. The inputs and outputs of the
sequential circuit are:

A: the present (external) inputs to the circuit,

y: the inputs fed back from the outputs (past history of inputs)
Z: the present (external) outputs from the combinational circuit
Y: the outputs that are fed back into the combinational circuit.
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• As shown in the Fig.2, the outputs: 'Y' are fed back through the
memory block to become the inputs: 'y' and these are called
the 'present state variables' because they determine the
current state of the circuit. The outputs: 'Y' are called 'next state
variables' as they will determine the next state of the circuit,
Thus

• The information stored in the memory elements at any given time

defines the present state of the sequential circuit.

• Present state and external inputs determines the outputs and next
state of sequential circuit.

• Sequential circuit is specified by a time sequence of external

inputs, internal states (present state and next state) and the
outputs.
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Combinational circuit versus Sequential circuit:

Combinational Circuits Sequential Circuits

Output at all times depends Output dependent not only the

on the combination of inputs present inputs but also past
history of inputs

No Memory element is Memory elements are required

required to store the past history of
inputs

Combinational Circuits are Sequential circuits are slower

faster than combinational circuits

The design of these circuits The design is comparatively

are easier to design difficult
 7

Classification of Sequential Circuits:

Depending on the timings of the signals sequential circuits are

classified as

Synchronous sequential circuits:

Clock signal affect the memory elements only at discrete
instant of time

Asynchronous sequential circuits:

Change in input signals can affect the memory elements
at any instant of time

Note: In both of these circuits memory element is flip-flop/Latch

which stores 1-bit information
 8

Flip-flop versus Latch:

• The interconnection of NAND or NOR forms the basic latch
circuits which is commonly used in a shift registers, a counters,
or in a variety of MSI and LSI circuits. Flip-flops or latches are
bi-stable elements.

• Flip-flop:
A flip-flop is a device, changes its state at times when a
change is taking place in the clock signal.
The flip-flop is said to be either leading edge or trailing
edge triggered clock.

• Latch: (Asynchronous or Synchronous)

An Asynchronous latch is continuously monitoring the

input signals and changes its state at times when an
input signal is changing.
 9

A synchronous latch is also continuously monitoring the

input signals but in this case a change of state at the
output can only occur when the control signal is active.

• In both cases the latch is driven by events, but synchronous

latch the control signal has to be high before the input can be
translated into a change at the output.

S - R Latch: (using NAND gates / also called NAND S-R Latch)

• The NAND latch is just a pair of cross-coupled NAND gates,
as in the following Fig. 3.

Fig. 3 (NAND S-R Latch)

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Notations:
• Latch is said to be "HIGH State" or "Logic 1 State" or "SET State"
When Q = 1

• Latch is said to be "LOW State" or "Logic 0 State" or "RESET State“

When Q = 0.

• In the diagram SET input is "S", RESET input is "R“

• Importantly Outputs: Q and Q_bar are Complementary,

i.e. when Q = 0 must satisfy Q_bar = 1 and vice versa.

Note:

For a NAND gate, if any one input is Logic 0, then its output is Logic 1,
when both inputs are Logic 1 then only its output is Logic 0
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Circuit operation

Case 1: when S = 1, R = 0

• When input S(1) (where (1) indicates input-1 of the NAND gate)
is at logic 1 its output (3) could be either logic 0 or 1, depending
on the state of the other input at (2).

• This is not very helpful, so we will take a look at other gate i.e,
R, input at (5). At this reset input (5) with logic 0, its output at
(6) is definitely at logic 1 based on the NAND gate function.
Since (6) is connected to (2), gate A will now have both its
inputs at logic 1 and this will result in its output (3) being at
logic 0.

• This would make gate B input (4) to be at logic 0. The final

state is the Q output from gate A at logic 0 and the Q_bar
output at logic 1.
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• The first line of the truth table:

It is showing that, its bi-stable output 'resets' because Q = 0.

Case 2: when S = 0, R = 1

• The result of these inputs is obtained by applying reasoning in

the same way as last case.

• Briefly, if S = 0, the output at (3) must be logic 1. Gate B has

two inputs, both at logic 1. NAND input (5) is R and (4) is
connected to (3), and so its output (6) must be at logic 0.

• The final result is S = 0 and R = 1 gives Q = 1 (and Q_bar = 0).

The bi-stable is said to be 'SET'.
 13

• The second line of the truth table:

Note:
For 'SET’ case of the latch i.e. Q =1, we need to apply S =
1, R = 0 as per the definition/notation of SET. Similarly to
RESET (Q=0), we need to apply S =0, R = 1. By observing
the truth tables of above two cases the inputs are opposite
to the (NOT of) actual inputs. These inputs are therefore
referred to as 'active low'.

• Therefore, on logic diagrams, the active low characteristic

is indicated by putting a 'not' line over the inputs S and R.
 14

Case 3: when S = 0, R = 0

• What would happen if we tried to set and reset are logic 0 at the
latch at the same time? (i.e. one input of the both NAND gates
are simultaneously logic 0 at the same time)

• By taking S to logic 0, gate A will make its positive output go to

logic 1 owing to the nature of the NAND gate.

• Similarly, by making R = 0, gate B will have an output of 1, i.e.

violating the condition of Q = 0 must satisfy Q_bar = 1.

• It is a stable condition and does no harm to the gates, but we

avoid this situation and refer to this state as 'forbidden',
'prohibited', 'invalid' or 'indeterminate'. This condition in the truth
table is shown as
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Case 4: when S = 1, R = 1

Now, what would happen if S changed to logic 1 and R

changed to logic 1?

• Depending on the state of output at (6) and (3), inputs of NAND

gates are determined, let output at (6) and (3) are 0 and 1
respectively, then input to gate A at (2) is 0 which makes output
at (6) is 0 and also output (3) is 1 i.e. outputs are same as
assumed outputs.

• Also if output at (6) and (2) are 1 and 0, when S = 1, R = 1

would not change the output state. Thus when S = 1, R = 1
outputs are same as previous outputs
 16

• then final truth table of S-R larch is

• Summary: Observing the above truth table

S = 0 and R = 1 Output Q = 1 (Set)
S = 1 and R = 0 Output Q = 0 (Reset)
(contradicting basic notation of the latch)

• Therefore latch circuit is modified which is called as

S-R Latch (NAND) with active HIGH Inputs

It is the circuit of connecting NOT gates at the inputs as shown below:

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• S-R Latch (NAND) with active HIGH Inputs

Fig. 4 NAND S-R Latch with active high inputs

Circuit Operation:
• When S = 0 and R = 1
(Case – 1 operation of previous circuit ) i.e. 𝑆 = 1, 𝑅 = 0 and Q =0
• When S = 1 and R = 0
(Case – 2 operation of previous circuit ) i.e. 𝑆 = 0, 𝑅 = 1 and Q =1
• When S = 1 and R = 1
(Case – 3 operation of previous circuit ) i.e. 𝑆 = 0, 𝑅 = 0 and Q =X
• When S = 0 and R = 0
(Case – 4 operation of previous circuit ) i.e. 𝑆 = 1, 𝑅 = 1 and Q = N.C
 18

• Truth table of NAND S-R Latch with active HIGH Inputs

 19

• Constructing a Karnaugh Map, as shown in Fig. 5,

(min-terms corresponding to inputs and output are shown in
red shaded box in the truth table. Note that Q is LSB, read the
K-map as SR-Q vertically as shown in the Fig.5)

• We obtain the characteristic equation of S-R Latch given by:

• This equation is used for applications where neither of the

inputs S and R can take the state 1.

Fig.5 K-Map of S-R Latch

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• Fig.6 shows the timing diagram of the SR latch where the

different operating modes that appear in the truth table can be
observed.

Fig.6 Timing diagram of S-R Latch

• Exercise (1) :
The NOR latch circuit is shown in the following Fig. 7
Obtain the truth table ?
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Fig. 7 NOR Latch

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Gated Latches:

• A gated or level-sensitive SR latch uses a control signal C that

can be a clock signal.

• The signal C is used to enable (or inhibit) the latch at specific

time intervals.

• The gated SR latch in Fig. 8(a) is made up of two NAND gates and an
SR latch. It is represented by the symbol shown in Fig. 8(b).

1
3

4
2

Fig. 8 Gated S-R NAND Latch

(a) circuit diagram (b) block diagram
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• If C=0, the outputs of gates (1) and (2) will always be 1,

irrespective of the present values of S and R

• When C changes from 0 → 1, gates (1) and (2) are enabled

and the latch becomes active.

• The state of signals S and R at this time, from 0 → 1 during

active period have an immediate effect on the output of the
latch.

• Timing diagram illustrating controlled transparency is shown in

the Fig.9

Fig. 9 Timing diagram of S-R Latch

 24

• The truth table of the gated SR latch can be constructed

as

• Exercise (2):
Extend the above table as like truth table in slide
no.18 and simplify using K-Map
 25

• By characteristic equation of S-R latch, the following equations

can be derived:

Where

and finally we have

 26

• Exercise (3) :
Draw the gated NOR latch circuit, describe their
operation? Obtain its truth table and timing diagram ?

Gated (Controlled ) D-Latch:

• A gated D latch (D stands for data) is constructed from a gated
SR latch, as shown in Fig. 10.
• Connecting an inverter between the S and R inputs prevents
the forbidden state of S-R latch

Fig. 10 Gated D-Latch

(a) NOR circuit (b) NAND Circuit (c) block diagram
 27

• Making this connection results a modification in the S-R state

table

• Since S and R can never simultaneously 1 or 0, the second

row and last row of S-R truth table can be deleted.

• As there is no independent R signal, the R column can also be

deleted and S column becomes D column. The truth table of
D-latch is given by
 28

• The characteristic equations is obtained as

• Characteristic equation of the gated two SR latches are

 29

• Considering NAND characteristic equation:

• If C = 1 the characteristic equation

• If C = 0 it becomes

• With a gated D latch, the state of the input D is transferred to the

output when the control (or enable) input C is set to 1, while the state
of the output does not change when the control input is reset to 0

• This is translated into a characteristic equation of the form:

 30

• The gated D latch is thus said to be transparent when C = 1. It

is, therefore, sensitive to the high level of the signal applied at
the input C.
•
Fig. shows block diagram of gated D latch. In the truth table the
outputs 𝑄+ and 𝑄 + are complementary. The timing diagram for
the D latch is given in Fig. where the output Q is initially set to 0.

(a) (b)
Fig. 11 (a) Block diagram of D-Latch (b) Timing diagram of D-latch
 31

This slide is
Intentionally Left Blank
 32

• The latches without controlled or enabled input described

earlier, the output can change their state any time when the
input conditions are changed. So, they are called asynchronous
latches.

• By providing control/enable input determines, the state of the

circuit is to be changed and the operation of the basic latch is
modified. If the additional control/enable input is made as clock
signal and thus such latches are called flip-flops.

• Since, flip-flop responds to the changes in inputs only as long as

the clock is high time, these types of flip-flops are also called
level triggered flip-flop

• The flip-flop can be triggered at either rising edge or falling edge

of clock signals. Such flip-flops are called edge triggered flip-
flops. They will be discussed later.
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• Therefore controlled/enabled latches are same as flip-flops.

• Different flip-flops discussed so far

S-R flip-flop (NAND circuit) discussion on slide 22

S-R flip-flop (NOR circuit) exercise (3)

D flip-flop (NAND circuit) discussion on slide 26

D flip-flop (NOR circuit) discussion on slide 26

• Only change is the CLK is the input instead of C input, also

CLK nomenclature is Clk in the most of text books

• Also remember that, ‘E’ symbol is used for enable in the

circuits.
 34

J-K Flip-Flop
• The JK flip-flop (J as a set input, and K as a reset input) is the
most versatile of the basic flip-flops.

• When it is activated, it permits the storage of a binary data based

on the combination of states taken by the inputs J and K.

• A JK flip-flop can be constructed with standard latches and

additional gates, the connections between them are as shown in
the Fig.13(a), its symbol is shown in the Fig.13(b). Its Operation:

(a) (b)
(a)
Fig. 13 (a) J-K Flip-Flop (b) Block diagram
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Case 1:
• Let 𝐽 = 0 𝑎𝑛𝑑 𝐾 = 0, the outputs of both the AND gate will be
0, whatever be the value of 𝑄𝑛 or 𝑄𝑛

Therefore, the inputs to the basic S-R flip-flop will be

S = 0 and R = 0. Hence, output from SR FF is same as
previous state i.e,

𝑄𝑛+1 = 𝑄𝑛

Case 2:
If J = 0 and 𝐾 = 1, and let the previous state of flip-flop is SET
i.e., 𝑄𝑛 = 1, 𝑄𝑛 = 0
then S = J . 𝑄𝑛 = 0 . 0 = 0 and
R = 𝐾. 𝑄𝑛 = 1 . 1 = 1
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• So, 𝑆 = 0 and 𝑅 = 1, therefore on the application of a clock

pulse, the output will be RESET to 0

• If J = 0 and 𝐾 = 1, Let consider previous state of flip-flop is

RESET i.e.,

𝑄𝑛 = 0 and 𝑄𝑛 = 1

then S = J . 𝑄𝑛 = 0 . 1 = 0 and

R = 𝐾. 𝑄𝑛 = 1 . 0 = 0

• Thus, 𝑆 = 0 and 𝑅 = 0, therefore on the application of a clock

pulse, the output will be same state i.e RESET state
 37

Case 3:
• If J = 1 and 𝐾 = 0, Let consider previous state of flip-flop is SET
state i.e.,

𝑄𝑛 = 1 and 𝑄𝑛 = 0
then S = J . 𝑄𝑛 = 1 . 0 = 0 and
R = 𝐾. 𝑄𝑛 = 0 . 1 = 0
• Then, 𝑆 = 0 and 𝑅 = 0, therefore on the application of a clock
pulse, the output will be same sate i.e. SET state.
• If J = 1 and 𝐾 = 0, Let consider previous state of flip-flop is
RESET state i.e.,

𝑄𝑛 = 0 and 𝑄𝑛 = 1
then S = J . 𝑄𝑛 = 1 . 1 = 1 and
R = 𝐾. 𝑄𝑛 = 0 . 0 = 0
 38

• Latch inputs becomes, 𝑆 = 1 and 𝑅 = 0, therefore on the application

of a clock pulse, the output will be SET state.

Case 4:
• Now, we consider one of the important condition of FF, If J = 1 and
𝐾 = 1, Let consider previous state of flip-flop is SET state i.e.,

𝑄𝑛 = 1 and 𝑄𝑛 = 0

then S = J . 𝑄𝑛 = 1 . 0 = 0 and

R = 𝐾. 𝑄𝑛 = 1 . 1 = 1

• Then 𝑆 = 0 and 𝑅 = 1, makes output to RESET state on the

application of a clock pulse. FF output changes from SET to RESET,
i.e. output changes 1 to 0
• Let us consider another condition, when 𝐽 = 1 and 𝐾 = 1, and the
previous state of flip-flop is RESET state i.e.,

𝑄𝑛 = 0 and 𝑄𝑛 = 1
 39

then S = J . 𝑄𝑛 = 1 . 1 = 1 and

R = 𝐾. 𝑄𝑛 = 1 . 0 = 0

• Then 𝑆 = 1 and 𝑅 = 0, makes output to SET state on the

application of a clock pulse. FF output changes from RESET to
SET, i.e. output is changes from 0 to 1.

• In short, when 𝐽 = 1, 𝐾 = 1 and CLK = 1, the flip-flop output toggles.

Toggles means the present output is the complement of previous
output. The state table of J-K FF will be

Comments

No change, memory

RESET
SET

Toggles
 40

Timing diagram:
• The timing diagram of J -K FF is illustrated in the Fig. 13

Fig. 13 Timing diagram of J-K FF

 41

We consider the following cases:

1) Initially all the inputs are zero and the output Q is 1.

2) At the time when first clock pulse goes HIGH (at point a),
inputs are J = 0, K = 1. Thus, the output of flip-flop will be
reset to Q = 0 state.
3) Again, when the clock pulse goes HIGH at point c, inputs are
J=1, K = 1. Therefore, the flip-flop output toggle to its opposite
state i.e., Q = 1, since clock is maintained high again Q = 0, like
this output oscillates.
4) At point e clock pulse goes HIGH and inputs are J =0, K = 0,
hence the flip-flop does not change state on this transition and
output will be Q = 1.
5) At point g, clock pulse goes HIGH and input are J = 1, K = 0
this cause flip-flop to go into SET state i.e., Q = 1. Since it is
already 1, and it will remain in the same state, after few
seconds it toggles again since J =1, K=1.
 42

6) At point i, clock pulse goes high and inputs are J =1, K = = 1 ,

Therefore, the flip-flop toggles.

7) We can determine output for remaining clock transitions in the

same way.

Note: The forbidden state, inherent to the SR latch is eliminated

by adding two feedback pathways in order to ensure that the
output will be set to 1 only if Qn = 0 and reset to 0 only if Qn = 1.

Characteristic Equation:

• Let CLK = C, From the logic circuit of the JK flip-flop, we can

obtain
 43

and

• If C = 1, the characteristic equation takes the form

• If C = 0, we have

• It must be noted that this JK flip-flop is affected by undesirable

oscillations if J=1, K=1 and clock is high i.e output, Qn toggles
between 0 and 1 and it is called race around condition, as
shown in the following Figure 14.
 44

Fig. 14 Race around condition in J-K FF occurs at instant 𝑖

• As long as pulse of the clock is HIGH output, Q toggles therefore

pulse width of the clock signal must be smaller than the
propagation delay of the flip-flop.
 45

Triggering of Flip-Flops:
• The momentary change in clock input of flip-flop to switch it
from one state to the other state is called trigger and the
transition it causes is said to trigger the flip-flop.

• The process of applying the clock signal to change the state of

a flip-flop is called triggering.

• There are two types of triggering the flip-flops:

level triggering and edge triggering

• In level triggering, the input signals affect the flip-flop only when
the clock is at logic 1 level.

• The flip-flops discussed in previous are level-triggered flip-

flops.
 46

• In a level-triggered flip-flop, the output responds to the data

present at the inputs during the time the clock pulse level is
HIGH.
i.e. any changes at the input during the time the clock is
active (HIGH) are reflected at the output as per its truth
table.

• Since the flip-flop changes its state only when clock pulse is
HIGH, this is also referred to as positive level triggered flip-flop.

• In some cases flip-flop changes its state when clock pulse is

LOW and it is called negative level triggered flip-flop. The clock
pulses of these triggering are shown in following the Figure.

+ve Level triggering clock –ve level triggering clock

 47

Edge Triggering:

• In edge triggering, the input signals affect the flip-flop only if

they are present at the positive going or negative going edge of
the clock pulse.

• The clock changes state from 0 to 1 or 1 to 0, as shown in

following Figure.

+ve edge triggering clock –ve edge triggering clock

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• The change of state from 0 to 1 is known as positive edge and

the change of state from 1 to 0 is known as negative edge.

• The flip-flop that responds for the positive edge is known as

positive edge-triggered flip-flop.

• The flip-flop that responds to the negative edge is known as

negative edge-triggered flip-flop.

• The edge triggering is most suitable for J-K flip-flop because

edge triggering avoid race around condition i.e. continuous
toggling is avoided from 0 to 1 when J=1, K=1, Since clock
edge is available only once when its state is changed.

• J-K FF can be two types: +ve edge triggered or –ve triggered.

 49

Methods of Generating Edge Triggering :

• The circuit that convert the clock pulse into positive edge
and negative edge are shown in Fig. 15 (a) and (b)
respectively. This is a RC differentiator circuit.

Fig. 15 Converting pulse triggering to edge triggering

 50

• Another method of generating narrow spikes or achieving

edge triggering uses an inverter and AND gate as shown
in Fig. 16(a) and (b)

Fig. 16 Generating edge triggering using AND and INVERTER gates

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Edge triggered Flip-Flops

The different flip-flops can be

+ve edge triggered S-R flip-flop
-ve edge triggered S-R flip-flop
+ve edge triggered D flip-flop
-ve edge triggered D flip-flop
+ve edge triggered J-K flip-flop
-ve edge triggered J-K flip-flop
+ve edge triggered T flip-flop
-ve edge triggered T flip-flop
 52

• The operation of the edge triggered flip-flops are same as

pulse triggered flip-flops, only difference is the change of their
states are affected at the edge of the clock

• The following timing diagram shows +ve edge triggered S-R

flip-flop

N.C R S S R S

Initial
states
 53

• If this flip-flop is –ve edge the transitions of change of

states are be shown at negative edge of the clock.

• The block diagram of +ve edge and –ve edge flip-flops

+ve edge S-R FF –ve edge S-R FF

+ve edge D FF –ve edge D FF

 54

+ve edge J-K FF –ve edge J-K FF

Timing diagram of J-K flip-flop: No race around

N.C T R S S T R
 55

T flip-flop :
• Recollect, the effect of holding J and K at logic 1 is to make the
outputs toggle.

• In this T flip-flop J and K inputs permanently connected as

shown in the Fig. 17

• Connecting J and K together means S and R tied up together

therefore S-R flip-flop can also modified into T flip-flop.

• D flip-flop can be ready made but T flip-flop can not, it is simply

constructed from J-K or S-R

• When JK flip-flop is made as T flip-flop, there are two input states

only, i.e. T=0 (J=0, K=0) and T=1 (J=1, K=1). In the first case output ,
𝑄𝑛+1 = 𝑄𝑛 and in the second case 𝑄(𝑛+1)= 𝑄𝑛 (toggles)
 56

• Let T =1, when clock is transits, output Q toggles, that’s why T

flip-flop is frequently called toggle circuit (or toggle FF).

Fig. 17 +ve edge triggered T flip-flop

• The truth table of +ve edge triggered T flip-flop is shown below.

 57

• Assuming that J = K = T , we obtain the characteristic equation

of the T flip-flop assuming CLK = C,

• if C = 1, the characteristic equation is reduced to

• if C = 0, we have

• Exercise(4): draw the timing diagram of –ve triggered T flip-flop

with appropriate inputs.
 58

• Exercise(5): The clocked J-K flip-flop is shown in the following

figure obtain its truth table?

• Exercise(6): Draw clocked J-K flip-flop circuit using NAND

gates as like NOR circuit shown in exercise(5) briefly describe
the operation and obtain its truth table

• Exercise(7): Use suitable truth table of J-K and T flip-flop obtain

characteristic equation with K-map
 59

Master – Slave J-K flip-flop

• The race-around condition is a major problem in J-K flip-flop.

• To overcome this problem, edge-triggered circuits can be used

whose output is determined by the edge, instead of the level
triggering of the clock signal.

• Another way to resolve the problem is to use the J-K flip-flop in

Master-and-Slave mode as shown in Fig. 18

Fig. 18 master-slave J-K flip-flop

 60

• This is the cascade connection of two J-K flip-flops. The first

flip-flop is called master and other one is called as slave.

• The master is clocked in the normal way but the inverted clock is
applied to slave
i.e, the master is positive-level-triggered and the slave is
negative-level-triggered.

• It is assumed that the changes in J and K inputs does not

effect on output when clock is low since master flip-flop is
disabled. Operation as follows:

(1) When the clock is high, the master flip-flop is enabled

while the slave flip-flop is disabled.

As a result, the output of master flip-flop (𝑄𝑚 and 𝑄𝑚 )

changes and these changes are fed to the input of the
slave flip-flop.
 61

But there is no change at the output of slave flip-flop

(𝑄 and 𝑄 ) since inverted clock pulse is applied to slave
flip-flop

(2) When the clock goes LOW, the master flip-flop gets
disabled while the slave flip-flop is enabled. Therefore, the
slave J-K flip-flop changes state as per the logic states at its
J and K inputs.
•

The contents of the master flip-flop are therefore

transferred to the slave flip-flop. At this time master flip-
flop as of now disabled can acquire new inputs without
affecting the output.

• The timing diagram of this flip-flop as follows:

 62

Timing diagram of J-K Master-Slave Flip-Flop:

SETS Qm NC Qm
TOGGLE Qm

SLAVE→ J=1,K=0
SETS Q=1 SLAVE→ J=0,K=1
RESETS Q=0
 63

Asynchronous inputs in flip-flops:

• So far discussed flip-flops have output is synchronous with the clock
input.

i.e. data on these inputs are transferred to the flip-flop’s output

only on the triggering of the clock pulse
• Asynchronous inputs affect the flip-flop output independently of the
synchronous inputs and the clock input.

• These asynchronous inputs force the flip-flop output to go to SET (1)

state or RESET(0) state at any time regardless of the conditions at
the other inputs
• PRESET and CLEAR inputs are asynchronous inputs.

• An active level on the PRESET input will SET the flip-flop and an active
level on the CLEAR input will RESET it.

• Asynchronous inputs may be active HIGH or active LOW, usually, these

are active LOW inputs.
 64

J-K flip-flop with asynchronous inputs :

• Fig. 19 shows the logic diagram for a J -K flip-flop with active-LOW
PRESET and CLEAR inputs.

• These inputs are connected directly into the latch portion of the flip-flop
so that they override the effect of the synchronous inputs, J, K and the
CLK.

Fig. 19 J-K flip-flop with PRESET and CLEAR inputs

• In the block diagram PRESET and CLEAR inputs are indicated by small
bubble at the input terminals and labeled as 𝑃𝑅𝐸 and 𝐶𝐿𝑅 respectively.
 65

• PRESET and CLEAR inputs and their state of operation is

shown in the following table

• The asynchronous inputs are inactive and the flip-flop responds

according to J, K and CLK inputs in the normal way. In other
words, these logic states of PRESET and CLEAR for clocked
operation
 66

• Since PRESET is activated, output Q will immediately SETS to

a 1, whatever conditions are present at the J, K and CLK
inputs. The CLK input cannot affect the flip-flop in this case.

• Since CLEAR input is activated, so output Q will be reset to a 0

independent of the conditions on the J, K or CLK inputs. The
CLK input has no effect in this case.

• Both asynchronous inputs can not be active simultaneously.

This condition should not be used, since it can result in an
invalid state.
Timing diagram of J-K FF with asynchronous inputs :

H
A B C D E F G I J

SETS ‘Q’ By PRESET Q=N.C. because no clock, no asn. i/ps

(A, D) (B, E, G, J)
RESETS ‘Q’ By CLEAR (F, I) Q Toggled no asyn. i/ps (C, H)
 68

Flip-flop timing parameters:

• A flip-flop only acquires a signal whose level can remain stable
for a certain time.

• There are three important timing parameters to be considered

when designing circuits with flip-flops.

• Set-up time, ts: Set up time is the minimum time that input signal
must be present on input terminal prior to the triggering edge of the
clock pulse as shown in the following Figure.

• The typical value of set-up time is from 5 to 40 ns. If the set-up time of
the signal is less than the desired set-up time, then the response of
flip-flop is not reliable.
 69

• Hold Time, tH: The hold time is the minimum time interval that
signal must remain at the terminal after the triggering edge of
the clock pulse as illustrated following in Figure.

• In positive edge-triggered flip-flops, the output changes with the

rising edge of the clock.

• It does not mean that after the rising edge of clock, the input
signal can be changed immediately. The input signal should be
held at least for the hold time.
•

• The typical hold-up time is from 0 to 10 ns.

 70

• Propagation Delay, tp : The propagation delay of flip-flop is the

amount of time required to change the state after the clock hits
the input, as shown in the following Figure. The typical value of
is 10 to 20 ns.

• Maximum Clock Frequency : This is the highest clock frequency

at which the flip-flop can be triggered. If the clock frequency is above
maximum, the flip-flop will work reliably and properly.
 71

Excitation Tables of Flip-Flops:

• The excitation table lists the present state (PS), the desired
next state (NS) and the flip-flop inputs (J , K , D, etc.). To
achieve NS from PS it shows what are the required inputs.

• Thus, excitation table of a flip-flop is obtained by looking at its

truth table in a reverse way.

Excitation Table of S-R flip-flop :

Truth Table of S-R FF Excitation Table of S-R FF
 72

How it is obtained?

(Row1): 0 → 0 transition: It means that present state of the flip-

flop is 0 and it remains 0 when a clock pulse is applied.
It is possible when the inputs are S = 0, R = 0 (hold
condition) or S = 0, R = 1 (reset condition). Thus, S has
to be 0 but R can be either 0 or 1. So SR = 0X for this
transition.

(Row2): 0→1 transition: It means that the present state of the

flip-flop is 0 and if it goes to 1 when a clock pulse is
applied. It is possible only when the inputs are S = 1
and R = 0 (set condition). So S R = 10 for this transition.

(Row3): 1 → 0 transition: It mean the present state of the Flip-flop is

1 and if it goes to 0 state when a clock pulse is applied. It is
possible only when the inputs are S = 0, R = 1 (reset
condition). So SR = 01 for this transition.
 73

(Row4): 1 → 1 transition: It means that the present state of the flip-

flop is 1 and it remains 1 when a clock pulse is applied. It is
possible when the inputs are S = 0, R = 0 (no change
condition) or S = 1, R = 0 (set condition). Thus R has to be 0
but S can be either 0 or 1. So SR = 0X for this transition.

Excitation Table of J-K flip-flop:

Truth Table of J-K FF Excitation Table of J-K FF

Exercise (8) How it is obtained give explanation and also obtain

excitation tables for D, T flip-flops?
 74

Conversion of flip-flops:

• To convert one type of flip-flop into another type, we have to

obtain the expressions for the inputs of the given flip-flop in
terms of the inputs of the required flip-flop and the present
state variables of given flip-flop.

• Then, this expression can be implemented using a

combinational circuit. The combinational circuit connected with
given flip-flop will perform as required flip-flop as shown in the
following circuit.

For example to convert a S -R flip-flop to J -K flip flop first

find the expression of inputs of S and R in terms of J, K
and present state Qn. Now, this expression can be
implemented using combinational circuit.
 75

Conversion of S-R Flip-Flop to J-K Flip-Flop:

• We have, S-R flip-flop and we want J-K flip-flop operation

from it.

• J-K is the external input and S and R are the actual inputs to
the existing flip-flop. Now, we have to find expressions of S and
R in terms of J , K and Qn.

Step 1: Construct the present-state and next-state table of a

J-K flip-flop as shown in the Table-A.

Step 2: Write the values of S and R that are required to

change the state of the flip-flop from Qn to Qn+1.
We obtain the complete conversion table as shown
in Table-B.
 76

Table – A Table – B

Step 3: Obtain the K-maps for S and R inputs and obtain

simplified expressions taking J, K and Qn as inputs

Step 4: Using the simplified expressions of S and R and given

flip-flop draw the logic diagram
Step 3: K- Maps

Step 4 : Logic diagram

 78

• Possible conversions
SR to D, JK, T
D to SR, JK, T
JK to SR, D, T
T to SR, JK, D

Conversion of S-R Flip-Flop to D Flip-Flop:

Step 1: Obtaining State table of D flip-flop (Table – A ) as shown

in below
 79

Step 2: Obtaining conversion table (Table – B) by using

excitation table of SR

Step -3: Draw the K-map for S and R

 80

Step 4: From the K-maps, we get the simplified expressions for

S and R. The logic diagram showing the conversion S-R flip-flop
to D flip-flop is shown in the following Figure.

Conversion of S-R Flip-Flop to T Flip-Flop:

Step 1: Obtaining State table of D flip-flop (Table – A ) as shown

in below
 81

Step 2: Obtaining conversion table (Table – B) by using

excitation table of SR

Step -3: Draw the K-map for S and R

 82

Step 4: From the K-maps, we get the simplified expressions for

S and R. The logic diagram showing the conversion S-R flip-flop
to T flip-flop is shown in the following Figure.

Exercise(9): Convert T flip-flop into D flip-flop

Exercise (10): Convert D flip-flop into J-K flip-flop