Bài tập phần 4

1. In Cortex-M processors, first step of pipeline is :

A. Fetch B. Decode C. Memorize D. Execute
2. Processor inside a microcontroller product, excluding the memory system, peripherals, and
other system support components is termed as :
A. Flip flop B. Processor Core C. CPLD D. FPGA
3. Most of the processors designed by ARM are :
A. 4 bit B. 8 bit C. 16 bit D. 32 bit
4. DMA controller stands for :
A. Direct Memory Alternation Controller
B. Direct Memory Access Controller
C. Direct Multi Access Controller
D. Double Memory Access Controller
5. A small processor design optimized for Field Programable Gate Array applications is:
A. Cortex-M0 processor
B. Cortex-M1 processor
C. Cortex-M3 processor
D. Cortex-M0+ processor
6. Which of the following ARM processors have longest pipeline :
A. Cortex-R processor
B. Cortex-A processor
C. Cortex-M processor
D. ARM9E series
7. Simple microcontroller-based systems do not have:
A. Inputs
B. Outputs
C. Peripherals
D. File systems
8. For applications that demand very high data-processing requirements, or if double precision
floating point calculation is needed, then best choice will be:
A. Cortex-M0 processor
B. Cortex-M3 processor
C. Cortex-M0+ processor
D. Cortex-M7 processor
9. In Cortex-M0 and Cortex-M0+ processor, R14 register is a :
A. Stack pointer
B. Link register
C. Program Status Register
D. Program counter
10. In pipelining, after fetching, data is
A. Initialized
B. Decoded
C. Deleted
D. Executed
11. RAM used for data storage in microcontroller is:
A. SRAM
B. DRAM
C. Flash memory
D. Cache memory
12. What is the link register in Cortex M ?
A. It contains the address of current executed instruction
B. It contains the return address of function call
C. It is used to link 2 registers
13. In Cortex-M processors, NVIC stands for :
A. Nested Vectored Interrupt Controller
B. Nested Voltage Interrupt Controller
C. Nested Variable Interrupt Controller
D. Nested Velocity Interrupt Controller
14. In Cortex-M processors, NVIC module is used to:
A. Handle all the interrupts and exceptions that Cortex-M support
B. Handle all DMA requests that Cortex-M support
C. Handle all data communications
D. Handle all system errors
15. Most of the microcontrollers are designed with :
A. BJTs
B. JFETs
C. CMOS
D. Diodes
16. Cortex-M3 processor consist of pipeline :
A. Two stages
B. Three stages
C. Four stages
D. Five stages
17. Microcontroller chip typically contains a :
A. Telecommunication system
B. Memory system
C. Power system
D. Mechanical system
18. Part inside a processor of the microcontroller that handles the software execution, excluding the
interrupt controller and debug support hardware is termed as:
A. Processor core
B. Code
C. Bit
D. Baud
19. After data is decoded by processor, it is :
A. Initialized
B. Decoded
C. Deleted
D. Executed
20. In microcontrollers, GPIO stands for :
A. General Purpose Input/Output
B. Global Purpose Input/Output
C. General Public Input/Output
D. Global Public Input/Output
21. ARM7 is the group of:
A. 32 bit ARM processors
B. 64 bit ARM processors
C. 8 bit ARM processors
D. 128 bit ARM processors
22. RAM type present in microcontroller is:
A. SRAM
B. DDR
C. RDRAM
D. CAS latency
23. Hardware component that handles all memory and caching operations associated with the
processor is termed as:
A. Memory Management Unit (MMU)
B. Flash memory
C. SRAM
D. EEPROM
24. Except special registers, register bank of Cortex-M3 consist of :
A. 8 registers
B. 16 registers
C. 32 registers
D. 64 registers
25. In microcontrollers, non-volatile memory storage for program code is :
A. ROM
B. SRAM
C. DRAM
D. SDRAM
26. In Cortex-M3 processor core, R15 register is :
A. Link register
B. Stack pointer
C. Program counter
D. Program loader
27. Sizes of data bus and address bus in Arm Cortex M3 processor core are:
A. 16 bit and 16 bit, respectively
B. 16 bit and 32 bit, respectively
C. 32 bit and 32 bit, respectively
D. 32 bit and 16 bit, respectively
28. Sizes of Flag register in Arm Cortex M3 processor core:
A. 8 bit
B. 16 bit
C. 32 bit
D. 64 bit
29. Arm Cortex M3 uses:
A. Thumb 16bit and 32bit instruction set
B. Thumb 16bit instruction set
C. Thumb 32bit instruction set
D. Thumb 64bit instruction set
30. This 4-byte data (F8510032) is encoded for:
A. LDR R0, [R1,R2, LSL #3]
B. LDR R0, [R2, R5, LSL #3]
C. LDR R1, [R2,R6, LSL #8]
D. LDR R1, [R3,R5, LSL #9]
31. The instruction: ADD R1, R2, #0x00AE is encoded by the following bytes:
A. F1 02 01 AE
B. F2 01 02 AF
C. F1 01 01 AF
D. F2 02 01 AE
32. How does the LDR R0, [R1, #4]! instruction work:
A. Load 4 byte from memory with the addressing value = R1 + 4 into R0
B. Load 2 byte from memory with the addressing value = R1 into R0, then update R1 = R1 + 4
C. Load 4 byte from memory with the addressing value = R1 into R0, then update R1 = R1 + 4
D. Load 2 byte from memory with the addressing value = R1 + 4 into R0