iasre07 ‘Synchronous & Asynchronous Reset ~ ViSI Pro VUS PROFESSIONAL NETWORK @ Design Synchronous & Asynchronous Reset Reset set is a signal that is used to initialize the hardware, as the design does not have a way to do self That means, reset forces the design to a known state. In simulation, usually itis activated at the beginning, but in real hardware, reset is usually activated to power up the circuits alization. There are two types of resets used in hardware designs. They are synchronous and asynchronous resets. Synchronous reset Synchronous reset means reset is sampled with respect to clock. In other words, when reset is enabled, it will not be effective till the next active clock edge. T module synchronous_reset_test (input logic clk, reset, ini, output logic out) 2 always @(posedge clk) 3 ifCreset) outi <= 1'b0; 4 else outi <= int 5 endnodule In the above example, you can see that out’ will be changed only with the posedge of clk. To get the effect of reset, reset should be wide enough to be captured by the next posedge of clk. Advantages: 1. Gives a completely synchronous circuit 2. Provides filtering for the reset signal, So circuit will not be affected by glitches. (Special case: If glitch happens at the active clock edge, reset signal will be affected.) 3. Will meet reset recovery time, as the deassertion will happen within 1 clock cycle Disadvantages 1. Reset needs to be stretched, ifit is not long enough to be seen at the active clock edge. 2, Requires presence of clock to reset the circu 3. Asynchronous reset may be required if there are internal tri state buffers. 4. tis slow. 5, Synthesis will not be able to easily differentiate reset from other signals. So this has to be taken care while plus proleynchronous-asynehronous-esel! 18iasre07 ‘Synchronous & Asynchronous Reset ~ ViSI Pro doing synthesis. Otherwise it may lead to timing issues. 6. If there are gated clocks for power saving, this type of reset wont be suitable Asynchronous reset In asynchronous reset, reset is sampled independent of clk. That means, when reset is enabled mmediately and will not check or wait for the clock edges it will be effective T nodule asynchronous_reset_test Cinput logic clk, reset, inl, output Logic out); 2 always @(posedge clk or posedge reset) 3 ifCreset) out <= 1'b0; 4 else out <= inl; 5_endnodule Advantages 1. Reset gets t 2. Ibis fast. 3. Does not require presence of clock to reset the circuit, highest priorit Disadvantages 1. Reset line is sensitive to glitches. 2. May have metastability issues Comparison plus proleynchronous-asynehronous-esel! 2sesme017 ‘Syrehvonous & Asynchronous Reset ~ VLSI Pro module test; ogic clk,reset, inl; wire out; comment below code & conment async while simulating sync “test srst(clk,reset,inl,out!) (clk, reset, int, out); asynchronous_reset_test asr: nitial clk < 1'b0; S clk = !clk; uM #8 15 #13 16 #18 7 end 18 initial 9 #75. $finish 20 endnodule 21 22 module synchronous_reset_test Cinput logic clk, reset, int 23 always @(posedge clk) 24 if(reset) outl <- 1'bd: output Logic out) 35 else out 26 encnodute 28 module asynchron input logic ut ric outa 30 ifCre 1 31 else out < int; 32_endnodule Waveforms from the simulation (using abo for synchronous a NOUS circuits are shown tt a plus rolsynchronous-asynehronous-esel! aisiasre07 ‘Synchronous & Asynchronous Reset ~ ViSI Pro In this we can see that, synchronous changes are happening with respect to clock. In asynchronous whenever there is a posedge of clock or posedge of reset out! will be changed Conclusion Both synchronous and asynchronous reset have advantages and disadvantages. These would be used as per the design needs. For example if chip has to be powered up prior to clock, asynchronous reset has to be used Similarly if you want to design a completely synchronous circuit with no metastability issue related to reset, go with synchronous reset Author: Sini Balakrishnan Sini has spent more than a dozen years in the semiconductor industry, focusing mostly on verification, She is an expert on Formal Verification and has written international papers and articles on related topics. 2 Comments Ani 3 years ago Hello Sini, Ihave a query regarding the Async reset Consider, | have 2 modules - M1 and M2. M1 works with clk1, clk M2 works with clk2, clk2_rst_n and clk3, clk3_rst Modle M1 is a main controller which provides sync_reset(so' which is synced to clk1) to M2. Now can | use this sync_reset from M1, as async reset in M2. Can | OR the sync_reset with async_resets of M2 Iwill use reset_synchroniser in M2. No problem, But will this be a problem in reset tree at the backend? john 8 months ago Hello Sini. What are metastability issues? plus roleynchronous-asynehronous-esel! aisiasre0%7 plus proleynchronous-asynehronous-esel! ‘Syrehvonous & Asynchronous Reset ~ VLSI Pro sis