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    Cao Chapter 03 .

    Uploaded by

    Durgesh Dhore

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    © All Rights Reserved
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    The next level in the hierarchy main memory. dynamic using implemented jeally in the forms of Sim components, DIMMs, or RIMMs. « The main memory significantly slowe! a typical computer, called This rather large memory iy memory is much larger than the cache memory, j,, the access time for th, the Ms, but main memory is about ten times longer than the access time for the L1 cache. Magnetic Secondary Memory: * Disk devices provide a huge amount of inexpensive storage. They are very slow compared to the semiconductor devices used to implement the main memory. Video Lectures Computer Architecture & Organi; zation Ww. Code You are One Step Behind For Getting Old University Question Papers KE-Books x MCQ's EVA (Dwivedi | Sa a cracezshnr i ion aa CHAPTER 3 is chapter consists of the Deni unit, which executes machine instructions and coordinates the activities of other units, the, it || is often called the Instruction Set Proce eaor 113°) or simply the processor. We look at its intercl F structure and how it performs the tauke ot | fetching, decoding, and executing instructions of a program. The processing unit is usually called as the central processing unit (CPU), 3.1 Fundamental Concept To execute a program, the processor fetches one instruction at a time and performs the operations specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Program Counter: * Program counter PC helps the processor to keep track of the address of the memory location containing the next instruction to be fetched. After fetching an instruction, the contents of the PC are updated to point to the next instruction in the sequence. A branch instruction may change the content of the PC, “struction Registers: other key register in the processor is the ‘struction register, IR. It contains the address of instruction which is currently being executed. 'PUter Architecture & Organization QF. 3-1 ~ Processing Up, Chapter Three tion comprises 4 by... ich instrus ; Suppose that stored in One memory word, and that it #6 traction, the Processor as © te i teps: eerform the following three step’ a the contents of the memory locatio, ted e PC. The contents of thi, inted to as an instruction to p. pointed to © ted location are inter ey are loaded into the 1p xd. Hens lo exe gy ts en e WHT 88 m € [(PC]] suming that the memory is byte 2. eames increment the contents of the Pc by 4, that is, pc € [pc] + 4 3. Carry out the actions specified by the instruction in the IR. In cases where an instruction occupies more than one word, steps 1 and 2 must be repeated as many times as necessary to fetch the complete instruction. These two steps are usually referred to as the fetch phase,' step 3 constitutes the execution phase. ‘Baya the working of sgl bus ogantzatl diem tetewaeen Draw the Sing (6-16/19, W-16 for 7 marks) the CPU ae how aanation of the datapath of contrat he expaton of a (3) 93 for up aha riarel ‘ ~ G-17 for 8 marks) ‘Computer Arch Necture & Organiaation wre 2 4 ; er Three, Processing Uni gad Internal Organization of Processor zo study these operations in detail, we first need examine the internal organization of the ‘cessor. They can be organized and jnterconnected in a variety of ways, , single Common Bus: Figure 3.1 shows a single bus organization of processor unit. It shows how the arithmetic and logic unit (ALU) and all the registers are organized and interconnected via a single common bus. Data and Address Lines: Figure 3.1 shows the external memory bus connected to memory address register (MAR) and memory data register (MDR). Register MDR has two inputs and two outputs. 3. MDR and MAR: Data may be loaded into MDR either from the memory bus or from the internal processor bus. The data stored in MDR may be placed on cither bus. The input of MAR is connected to the internal bus, and its output is connected to the external bus. |. Control Lines: The control lines of the memory bus are connected to the instruction decoder and control logic block. This unit takes- care of issuing the signals and controlling the operation of all the units inside the processor and for interacting with the memory bus. . Processor Registers: Registers RO through R (0 - 1) are the CPU register. These registers include general purpose registers and special Purpose registers such as stack pointer, index Tegister and pointer. These registers are never Used for storing data generated by one iputer Architecture & Organization Wwe 33 0 Le J Th Processing Unit oe U: ALU selects output of Y when select 7. BLU: © 5 o put is 1 and it selects a constant number Snen select input is O as an input A for the fnultiplexer. The constant number is used to jncrement the content of the program counter. AS instruction execution progresses, Gata are transferred from one register to an- Other, often passing through the ALU to perform some arithmetic or logic operation. g, Instruction Decoder and Control Logic Unit: The instruction decoder and control ogic unit is responsible for implementing the actions specified by the instruction loaded in the IR register. The decoder generates the control signals needed to select the registers involved and direct the transfer of data. ta Path: All registers and the ALU are used for storing and manipulating data - The data fegisters, ALU and the interconnecting bus are called as Data Path. fith few exceptions, an instruction can be executed by performing one or more of the following operations in some specified sequence: * Transfer a word of data from one processor register to another or to the ALU Perform arithmetic or a logic operation and Figure 31 si store the result in a processor's register “Ges Orgaization of the Data Path f° Fetch the contents of a given memory location 6. Mi Processor and load them into a processor's register selects either exe, The multiplexer MUX ff Store a word of data from 2 processor's Constant vale ae Put of register Y oF & Tegister into a given memory location. fe ; an A input for the ALU TUs of the select input. ae ieee we 34 puter Architecture & Organization YYGi a=. to the stat & 35 a shows the data transfer bey, ad common DUS. Ween = Cue Figure le and Output Gating for the __aisters in Figure 3.1 0 . steps in whieh ge? ano} Pater Architect involves a sequence of are transferred from on€ & Organis 6 ation Wye ac, 3 ssterties __—____processing Unit gach register has input and output gating and + these gates are controlled by control signals, || qhese input and output of register are connected to the bus via switches controlled py the control signals Ri in and Ri out respectively. || when Ri in is set to 1, the data on the bus are Joaded into Ri. When Ri out is set to 1, the contents of register Ri are placed on the common data bus. While Ri out is equal to 0, the bus can be used for transferring data from other registers. ‘The signals Ri in and Ri out are called as input enable and output enable signals of registers respectively. Suppose that we wish to transfer the contents of register Ri to register Rs. This can be done as follows: © Enable the output of register Ri by setting Riou=1. This places the contents of Ri on the processor bus. © Enable the input of register R by setting Rs n=1. This loads data from the processor bus into register Rs. l operations and data transfers within the essor take place in synchronization with rocessor clock. puter Architecture & Organization Ye 3-7 Operation « The ALU is @ combinational circuit that o no internal storage. It performs arithmetic and logic operations 7 the two operands applied to its A and'y inputs. In Figures 3.1-and 3.2, ALU has two inputs, and B, and one output. A is obtained from output of the multiplexer MUX and B is obtained directly from the bus. The result produced by the ALU is stored temporarily in register Z. . Therefor, sequence of operations to add the and aus of register R1 to those of register R2 Store the result in register R3 is; 1. Rleat, Yi 2. Rosa, SdlectY, Add, Zia 3, Zou, R3i 1. The con register y,* °! Teeister R1 is loaded in 2. The multi ¥, causing tne S Select signal is set to Select Of register y ig ultiplexer to get the conten'® Computer Architect Put A of the ALU. At th? Te & Organization we # re Processing Unit same time, the content of register R2 is given to input B of ALU. The Add line is set ‘o 1, addition is performed on the two inputs A and B. This sum is loaded into register Z. g, The contents of register Z are transferred to the destination register, R3, ‘Explain timing diagram of Reed operation. (6-15, W-16/19 for 5/6/7 marks) Explain in brief: (W-17/18 for 6/14 marks) i Fetching a-word from memory ii, Storing a word in memory iti, Performing arithmetic or logical operation Draw and explain the timing dlagram of memory rea operation. 3.1.4 Fetching a Word from Memory * To fetch a word of information from memory, the processor gives the address of the memory location where this information is stored on address bus and requests a Read operation. * The processor transfers the required address in ‘MAR, whose output is connected to the address lines of the memory bus. * At°the same time, the processor uses the control lines of the memory bus to indicate that a Read operation is needed. * When the requested data are received from the memory they are stored in MDR, from where they can be transferred to other registers in the processor. Computer Architecture & Organization WYfiso. 3-9 Poet 13g al A © The connection’ iustrated 7D Processin for register MDR 3.4. It hae four cont’ I e MDR in and MDR (out) contro} O) gals to the internal bus, and MOR. Send ‘MDR-(out)-E control the connectig, . the external bus. to circuit in Figure 3.3 is easily moditie, revide the additional connections. A ie . exer can be used, with te rd input multipl emy bus data line connected to the thi, input. “bo Figure 3.3 Input and output gating for one register bit oe but is selected when MDR-(in)-E = 1.4 E can be ie gate, controlled by MDR-(out)- Hipop tothe meneenect the output of Ue Durin 1 the timing wm Read and Write operations, must be coordina Processor operations addressed device (4 With the response of th? vice on the memory bus. Computer Archit. fects ‘ure & Otganization yg ue 3-29 ater Three Processing Unit e processor completes one internal data ‘Tht Fi transfer in one clock cycle. The speed of Feration of the addressed device, on the cher hand, varies with the device. | = oss MOR eat Figure 3.4 Connection and Control Signals for Register MDR ‘Typically,-a cache will respond to a memory read request in one clock cycle. However, when a-cache miss occurs, the request is forwarded to the main memory, which introduces a delay of several clock cycles. Mlustration with Example: * A read or write request may also be intended for a register in a memory-mapped 1/0 device. Such I/O registers are not cached, so their accesses always take a number of clock cycles. To accommodate the variability in response time, the processor waits until it receives an indication that the requested Read operation has been completed. We will assume that 4 Computer Architecture & Organization WYf.c 3-41 Process, Memory. signal, CIN for this pre eh control 4 (MFC) is BSe' for Purpose Complete evice sets this signal ig y : qa 2 sen SSSA c ts of the the content Spe t Neen read and are availabe indicat Jocation have ie memory bus. Sa * eee a | iy % the data lines Figure 35 Timing of a memory Read operation A instruct Of a read operation, consider the Tate Move (R1), R2 are: "MS Needed to execute this instruction 2. MAR

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