Green University of Bangladesh

Department of Computer Science and Engineering (CSE)

Faculty of Sciences and Engineering
Semester: (Spring, Year: 2023), B.Sc. in CSE (Day)

Course Title: Digital Logic Design

Course Code: CSE_203 Section: 221_DG

K/S/A Test 2
Student Details

Name ID

MD. ATIK 221902046

Submission Date : 08 / 07 / 2023

Course Teacher’s Name : Md. Shihab Hossain

KSA Report Status

Marks: ………………………………… Signature: .....................

Comments: .............................................. Date: ..............................

 1. F1 = ∑ (0, 1, 3, 4, 7), F2 = ∑ (2, 3, 4, 6, 7), F3 = ∑ (0, 1, 2, 3, 6)
Design a logical diagram for F1, F2, F3 with the necessary Product Table using
PLA & PAL.

Ans to the Qu: No: 01

Objectives:
The objectives of this task are:
1. Design a logical diagram for the given functions F1, F2, and F3.
2. Construct the necessary Product Table for the logical diagram.

3. Implement the logical diagram using Programmable Logic Array (PLA) and
Programmable Array Logic (PAL).
4. Analyze and compare the PLA and PAL implementations.
5. Provide a conclusion based on the findings.

Logical Diagram Design:

To design a logical diagram for F1, F2, and F3, we first need to analyze the given sum-of-
products expressions. Let's break down each function:
F1 = ∑ (0, 1, 3, 4, 7) F2 = ∑ (2, 3, 4, 6, 7) F3 = ∑ (0, 1, 2, 3, 6)

I can start by identifying the required input variables based on the maximum index appearing
in the sum-of-products expressions. In this case, the maximum index is 7, so we need three
input variables: A, B, and C.
Next, I create a logical diagram by using AND gates to represent the product terms and OR
gates to represent the sum-of-products expressions. The inputs A, B, and C are connected to
each product term and the outputs of the product terms are connected to the OR gates.
Conclusion:
The logical diagrams for F1, F2, and F3 have been designed using PLA and PAL
implementations. The necessary Product Table has been constructed for the logical diagrams.
By analyzing the PLA and PAL implementations, we can observe that both can successfully
represent the given functions and produce the correct outputs for all input combinations.

PLA offers a fixed structure and requires a specific number of AND and OR gates, making it
less flexible but potentially more efficient in terms of gate count. PAL, on the other hand,
provides additional programmability with the decoder/multiplexer layer, allowing for more
flexibility but potentially at the cost of increased gate count.

The choice between PLA and PAL depends on the specific requirements of the design, such as
the level of flexibility needed, gate count constraints, and other design considerations.
 Ans to the Qu: No: 02

i. Objectives:
The objectives of this task are:
1. Design a synchronous counter using JK flip-flops.
2. Create a state transition table for the counter based on the given sequence.
3. Implement the counter circuit using JK flip-flops.
4. Verify the functionality of the counter by simulating the sequence.
5. Provide a conclusion based on the findings.

ii. Description:
1. Design the Synchronous Counter: Based on the given sequence: 1 -> 2 -> 4 -> 6 -> 5 -
> 0 -> 7, we can observe that the sequence consists of the decimal values from 0 to 7 in
a specific order.
To design a synchronous counter using JK flip-flops, we need to determine the number of flip-
flops required and the appropriate state transition table.

Since the given sequence has seven unique states (0 to 7), we need a 3-bit counter. Each flip-
flop will represent one bit of the counter.
We can assign the flip-flops as follows:
 Q2 represents the Most Significant Bit (MSB)
 Q1 represents the Middle Bit
 Q0 represents the Least Significant Bit (LSB)

2. Create the State Transition Table: To create the state transition table, we need to
determine the next state for each current state in the sequence.
Conclusion:

The synchronous counter circuit using JK flip-flops has been successfully designed to
implement the given sequence. By analyzing the state transition table and implementing
the circuit, we can observe that the counter progresses through the specified states in
the correct order.
Simulating the counter circuit with clock pulses will verify its functionality and
demonstrate the sequence progression. The designed counter provides a reliable and
accurate means of counting through the given sequence using JK flip-flops.

Thank You