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Esquemático Pt2257
Esquemático Pt2257
Tel: 886-66296288 Fax: 886-29174598 http://www.princeton.com.tw 2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan
PT2257
BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2257 via the SDA and SCL. The SDA and SCL make up
the BUS Interface. It should be noted that the pull-up resistors must be connected to the positive supply voltage.
DATA VALIDITY
A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW
States of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below.
BYTE FORMAT
Every byte transmitted to the SDA Line consists of 8-bit. Each byte must be followed by an Acknowledge Bit. The MSB is
transmitted first.
ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the SDA Line. The peripheral
(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge Clock Pulse so that
the SDA Line is in a Stable Low State during this Clock Pulse. Please refer to the diagram below.
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte; otherwise, the
SDA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this case, the master transmitter can
generate the STOP Information in order to abort the transfer.
INTERFACE PROTOCOL
The interface protocol consists of the following:
• A Start bit
• A Chip Address byte=88H
• ACK=Acknowledge bit
• A Data byte
• A Stop bit
PT2257 Address
Notes:
1. ACK=Acknowledge
2. Max. clock speed=100K bits/s
SOFTWARE SPECIFICATION
PT2257 ADDRESS
PT2257 Address is shown below:
1 0 0 0 1 0 0 0
MSB LSB
For example, for a Left Channel Attenuation at -33dB, the data byte is as follows:
START 1 0 1 1 0 0 1 1 ACK 1 0 1 0 0 0 1 1 ACK STOP
Vin=2.5Vrms, F=1KHz
Mute attenuation MUTE 90 95 97 dB
Volume Att=0dB, A-weighted
Vin=1Vrms,
Frequency response FR - 1 1.3 MHz
Volume Att=-10dB
Input impedance Rin F=1KHz 15 20 26 K
Output impedance Rout F=1KHz, Vout=100m Vrms - 100 -
Minimum load resistance Rload VDD=9V, Vo=2Vrms,THD<1% 2 - - K
I2
Parameter Symbol Condition Min. Typ. Max. Unit
Bus high input level VIH VDD=9V 0.4 - VDD VDD
Bus low input level VIL VDD=9V 0 - 0.2 VDD
+0
20
-20 5
VCC=3V
-40 1
d No Weighted VCC=5V
B -60
V % 0.1 VCC=9V
-80
A-Weighted
-100 0.01
-120
20 50 100 200 500 1k 2k 5k 20k
0.001
Hz 1m 10m 100m 1 2 4
Vrms
Residual Noise Floor THD vs. Output Level, RL=50K
20
1 10
0.5
0.2 Vo=2.5Vrms
1
0.1
0.05
Vo=1Vrms %
% 0.1
0.02
0.01
Vo=0.2Vrms
0.005 0.01
0.002
0.001 0.001
20 50 100 200 500 1k 2k 5k 20k 1m 2m 10m 100m 500m 1 2 4
Hz Vrms
THD vs. Frequency THD vs. Output Level, RL=5K
20
10
+0 5
-20 2
1
-40
-60
d %
0.1
B -80
-100 0.02
-120 0.01
-140
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.