 8086 INSTRUCTIONS SET – 1 Data transfer

instructions (including I/O transfers), Binary arithmetic

instructions, Decimal (BCD, ASCII) arithmetic
instructions, Logical instructions, Shift and rotate
instructions, Control transfer instructions, PUSHF and
POPF, XLAT instructions.

 8086 PROGRAMMING BASED ON INSTRUCTION

SET - 1: Programs based on data transfer instructions,
binary arithmetic instructions, logical instructions, shift
and rotate instructions, control transfer instructions.

3/9/2022 NMAMIT, Nitte 2021-22 1

8086 Instruction Set - 1
 Data transfer instructions (including I/O
transfers),
 Binary arithmetic instructions,
 Decimal (BCD, ASCII) arithmetic instructions,
 Logical instructions,
 Shift and rotate instructions,
 Control transfer instructions.

3/9/2022 NMAMIT, Nitte 2021-22 2

 Data Transfer Instructions

3/9/2022 NMAMIT, Nitte 2021-22 3

 Data Transfer instructions essentially
copy the data and do not affect any flags
(except of course the POPF instruction
which modifies all the flags as per the
stack top word)

3/9/2022 NMAMIT, Nitte 2021-22 4

Data Transfer instructions

 General purpose byte or word transfer

Instructions
 Simple Input / Output port transfer
Instructions
 Special Address Transfer Instructions
 Flag Transfer Instructions

3/9/2022 NMAMIT, Nitte 2021-22 5

Data Transfer instructions

3/9/2022 NMAMIT, Nitte 2021-22 6

Data Transfer instructions

3/9/2022 NMAMIT, Nitte 2021-22 7

MOV
 Stands for move, it is actually copy, that is, when
data is moved from one register source to a
destination register, source is not destroyed,
only, there will be a copy of this data in the
destination register

3/9/2022 NMAMIT, Nitte 2021-22 8

XCHG
 Exchange instruction exchanges data between
registers or between register and memory

3/9/2022 NMAMIT, Nitte 2021-22 9

PUSH

 Push causes the data in the source register to

be copied on to the stack top

3/9/2022 NMAMIT, Nitte 2021-22 10

3/9/2022 NMAMIT, Nitte 2021-22 11
3/9/2022 NMAMIT, Nitte 2021-22 12
POP
 Pop causes the stack top moved to (that is,
removed from the stack and loaded onto) the
destination register or memory specified by the
instruction

3/9/2022 NMAMIT, Nitte 2021-22 13

3/9/2022 NMAMIT, Nitte 2021-22 14
3/9/2022 NMAMIT, Nitte 2021-22 15
XLAT / XLATB – TRANSLATE A
BYTE IN AL
 The XLATB instruction is used to translate a byte in AL.
 The instruction replaces a byte in AL register with a byte
pointed to by BX in a lookup table in the memory.
 Before the XLATB instruction can be executed, the lookup
table containing the values must be put in memory, and the
offset of the starting address of the lookup table must be
loaded in BX.
 The index of byte to be translated is put in AL.
 The XLATB instruction adds the byte in AL to the offset of the
start of the table in BX. It then copies the byte from the
address pointed to by (BX + AL) back into AL.
 XLATB instruction does not affect any flag.

3/9/2022 NMAMIT, Nitte 2021-22 16

 MOV BX, OFFSET Table
MOV AL,00
XLAT

3/9/2022 NMAMIT, Nitte 2021-22 17

Simple Input / Output port transfer Instructions:
IN: Copy data from a port

 IN accumulator, port
 The IN instruction reads from an input port into
AL or AX (only these two registers), to be
specified in the instruction

 The port address is generally in the register DX

 But if it is 8-bits or less, then it can also be

directly given in the instruction
3/9/2022 NMAMIT, Nitte 2021-22 18
  Ex:
IN AL,0C8H;Input a byte from port address 0C8H to AL
IN AX,34H; Input a word from port address 034H to AX

MOV DX,0FF78H ;Initialize DX to point to port

IN AL, DX ;Input a byte from 8 bit port 0FF78h to AL
IN AX,DX ; Input a word from 16 bit port 0FF78h to AX

3/9/2022 NMAMIT, Nitte 2021-22 19

OUT: output a byte or word to a port
OUT port, accumulator
 The OUT instruction outputs the data in register
AX or AL (only) to be specified in the instruction
to the output port indicated directly in the
instruction if the port address is 8 bits or less, or
in the register DX (for addresses 16 bits or less)
 Example1: MOV DX, 0C8H

OUT DX, AX
Example 2: MOV 0C8H,AL

3/9/2022 NMAMIT, Nitte 2021-22 20

Examples:

out 16h, ax; write to output port at address 16h from reg. ax

out dx, ax; write to output port at address in dx from reg. ax

out 23h, al; write to output port at address 23h from reg al

out dx, al; write to output port at address in dx from reg al

3/9/2022 NMAMIT, Nitte 2021-22 21

 Special Address Transfer Instructions
LEA –
 LEA Register, Source

 This instruction determines the offset of the variable or memory

location named as the source and puts this offset in the indicated
16-bit register.
 LEA does not affect any flag.

 LEA BX, PRICES ;Load BX with offset of PRICE in DS

 LEA BP, SS: STACK_TOP : Load BP with offset of STACK_TOP in SS
 LEA CX, [BX][DI] : Load CX with EA = [BX] + [DI]

3/9/2022 NMAMIT, Nitte 2021-22 22

LDS –
 Syntax:
LDS Register, Memory address of the first word
 This instruction loads new values into the specified register
and into the DS register from four successive memory
locations.
 The word from two memory locations is copied into the
specified register and the word from the next two memory
locations is copied into the DS registers.
 LDS does not affect any flag.
 LDS BX, [4326] : Copy content of memory at displacement 4326H in DS
to BL, content of 4327H to BH. Copy content at displacement of 4328H
and 4329H in DS to DS register.
 LDS SI, SPTR ;Copy content of memory at displacement SPTR and
SPTR + 1 and Contents of SPTR+2 and SPTR + 3 DS to DS register.

3/9/2022 NMAMIT, Nitte 2021-22 23

 LES –
 LES Register, Memory address of the first word
 This instruction loads new values into the specified register
and into the ES register from four successive memory
locations.
 The word from the first two memory locations is copied into
the specified register, and the word from the next two memory
locations is copied into the ES register. LES does not affect
any flag.
 LES BX, [789AH] :Copy content of memory at displacement 789AH in
DS to BL, content of 789BH to BH, content of memory at displacement
789CH and 789DH in DS is copied to ES register.
 LES DI, [BX] :Copy content of memory at offset [BX] and offset [BX] +
1 in DS to DI register. Copy content of memory at offset [BX] + 2 and
[BX] + 3 to ES register.

3/9/2022 NMAMIT, Nitte 2021-22 24

 Flag Transfer Instructions
 LAHF: (COPY LOW BYTE OF FLAG REGISTER TO AH REGISTER)
 The LAHF instruction copies the low-byte of the 8086 flag register to AH register. LAHF
does not affect any flag.

 SAHF: (COPY AH REGISTER TO LOW BYTE OF FLAG REGISTER)

 The SAHF instruction replaces the low-byte of the 8086 flag register with a byte from the
AH register. SAHF changes the flags in lower byte of the flag register.

 PUSHF (PUSH FLAG REGISTER TO STACK)

 The PUSHF instruction copies a word in the flag register to two memory locations in stack
pointed to by the stack pointer and decrements the stack pointer by 2. The stack segment
register is not affected. This instruction does to affect any flag.

 POPF (POP WORD FROM TOP OF STACK TO FLAG REGISTER)

 The POPF instruction copies a word from two memory locations at the top of the stack to
the flag register and increments the stack pointer by 2. The stack segment register and
word on the stack are not affected. This instruction does to affect any flag.

3/9/2022 NMAMIT, Nitte 2021-22 25

 Binary Arithmetic Instructions

3/9/2022 NMAMIT, Nitte 2021-22 26

 All binary arithmetic instructions update
the flag register based on the result of the
operation performed

3/9/2022 NMAMIT, Nitte 2021-22 27

ADDITION
– ADD Destination, Source
– ADC Destination, Source
 These instructions add a number from some source to a
number in some destination and put the result in the specified
destination.
 The ADC also adds the status of the carry flag to the result.
 The source may be an immediate number, a register, or a
memory location. The destination may be a register or a
memory location. The source and the destination in an
instruction cannot both be memory locations.
 The source and the destination must be of the same type
(bytes or words). If you want to add a byte to a word, you
must copy the byte to a word location and fill the upper byte of
the word with 0’s before adding.
 Flags affected: AF, CF, OF, SF, ZF,PF
3/9/2022 NMAMIT, Nitte 2021-22 28
 When an immediate value is used as an operand, it is
sign-extended to the length of the destination operand
format

 The ADD instruction performs integer addition

DEST ← DEST + SRC;

 The OF, SF, ZF, AF, PF, and CF flags are set according
to the result

Examples: ADD AX, BX

ADD [BX + 4], DX
ADD CX, 2[SI]
ADD DX, 123 H
3/9/2022 NMAMIT, Nitte 2021-22 29
ADC
 Adds with carry

 Same as ADD with the following change in the

operation:

DEST ← DEST + SRC + CF;

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result

3/9/2022 NMAMIT, Nitte 2021-22 30

3/9/2022 NMAMIT, Nitte 2021-22 31
Example : ALP to add 2 Number and store in a register…
data1 segment
N1 db 5Bh
N2 db 0A5h Directives: segment,db,dw,ends,assume
sum dw ?
data1 ends
code1 segment
assume cs:code1, ds:data1
start:
mov ax, data1
mov ds, ax
mov al, N1
add al, N2
mov ah, 00h
adc ah, 00h
mov sum, ax
mov ah, 4ch
int 21h
code1 ends
end start

3/9/2022 NMAMIT, Nitte 2021-22 32

SUBTRACTION
– SUB Destination, Source
– SBB Destination, Source

 These instructions subtract the number in source from the

number in destination and put the result in the destination.
 The SBB instruction also subtracts the content of carry flag from
the destination.
 The source may be an immediate number, a register or memory
location. The destination can be a register or a memory location.
However, the source and the destination cannot both be memory
location.
 The source and the destination must both be of the same type
(bytes or words). If you want to subtract a byte from a word, you
must first move the byte to a word location such as a 16-bit
register and fill the upper byte of the word with 0’s.
 Flags affected: AF, CF, OF, PF, SF, ZF.

3/9/2022 NMAMIT, Nitte 2021-22 33

SUB
 Subtraction
 Example: SUB DEST,SRC

 Follows the same rules as ADD with the

following change in the operation:

DEST ← DEST – SRC;

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result
3/9/2022 NMAMIT, Nitte 2021-22 34
SBB
 Subtract with borrow

 Same as SUB with the following change in the

operation:

DEST ← DEST – (SRC + CF);

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result

3/9/2022 NMAMIT, Nitte 2021-22 35

3/9/2022 NMAMIT, Nitte 2021-22 36
 CMP
 This instruction compares a byte / word in the specified
source with a byte / word in the specified destination.

 The source can be an immediate number, a register, or a

memory location. The destination can be a register or a
memory location.

 However, the source and the destination cannot both be

memory locations.

 The comparison is actually done by subtracting the source

byte or word from the destination byte or word. The source
and the destination are not changed, but the flags are set to
indicate the results of the comparison.

3/9/2022 NMAMIT, Nitte 2021-22 37
 AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction.
 For the instruction CMP CX, BX, the values of CF, ZF, and SF will
be as follows

CF ZF SF
 CX = BX 0 1 0 : Result of subtraction is 0
 CX > BX 0 0 0 :No borrow required, so CF = 0
 CX < BX 1 0 1 :Subtraction requires borrow, so CF = 1

3/9/2022 NMAMIT, Nitte 2021-22 38

 When an immediate value is used as an operand, it is
sign extended to the length of the first operand

Operation:

temp ← SRC1 − SRC2;

 In case an immediate value is used, then

temp ← SRC1 − Sign Extend (SRC2);

 The CF, OF, SF, ZF, AF, and PF flags are set
according to the result

3/9/2022 NMAMIT, Nitte 2021-22 39

 Examples:

CMP AX, 24 H; (24 is sign extended to 16 bits before

subtraction, because AX is a 16-bit register)

CMP BYTEPTR[BX], -24 H; (no sign extension done,

data in bytes are being handled)

CMP BX, SI

CMP AL, [BX]; (BX will be taken only as a byte pointer,

as AL is a byte register)

3/9/2022 NMAMIT, Nitte 2021-22 40

 MUL
 This instruction multiplies an unsigned byte in some source with an
unsigned byte in AL register or an unsigned word in some source with
an unsigned word in AX register.
 The source can be a register or a memory location. When a byte is
multiplied by the content of AL, the result (product) is put in AX.
 When a word is multiplied by the content of AX, the result is put in DX
and AX registers.
 If the most significant byte of a 16-bit result or the most significant
word of a 32-bit result is 0, CF and OF will both be 0’s. AF, PF, SF and
ZF are undefined after a MUL instruction.
 If you want to multiply a byte with a word, you must first move the byte
to a word location such as an extended register and fill the upper byte
of the word with all 0’s.
 You cannot use the CBW instruction for this, because the CBW
instruction fills the upper byte with copies of the most significant bit of
the lower byte.
3/9/2022 NMAMIT, Nitte 2021-22 41
 Example :
 The source operand is located in a general-
purpose register or a memory location

Operation:

IF byte operation
THEN
AX ← AL SRC
ELSE (* word operation *)
DX:AX ← AX SRC

3/9/2022 NMAMIT, Nitte 2021-22 42

 Flags Affected

The OF and CF flags are set to 0 if the upper half of

the result is 0; otherwise, they are set to 1

The SF, ZF, AF, and PF flags are undefined

Examples:
MUL BX
MUL WORDPTR [BX + DI]48 H
MUL BYTEPTR [SI]
MUL CL

3/9/2022 NMAMIT, Nitte 2021-22 43

IMUL : multiply signed numbers
IMUL source
 Integer (signed) multiply

 Similar to MUL, except the data are considered

as signed integers

 Flags are also affected similarly as for MUL

3/9/2022 NMAMIT, Nitte 2021-22 44

3/9/2022 NMAMIT, Nitte 2021-22 45
 DIV:
 This instruction is used to divide an unsigned word by a byte
or to divide an unsigned double word (32 bits) by a word.

 To divide a word by a byte, the word must be in the AX

register. The divisor can be in a register or a memory
location. After the division, AL will contain the 8-bit quotient,
and AH will contain the 8-bit remainder.

 To divide a double word by a word, the most significant word

of the double word must be in DX, and the least significant
word of the double word must be in AX. After the division, AX
will contain the 16-bit quotient and DX will contain the 16-bit
remainder.

3/9/2022 NMAMIT, Nitte 2021-22 46
 If an attempt is made to divide by 0 or if the quotient is
too large to fit in the destination (greater than FFH /
FFFFH), the 8086 will generate a type 0 interrupt.

 All flags are undefined after a DIV instruction. If you want

to divide a byte by a byte, you must first put the dividend
byte in AL and fill AH with all 0’s. Likewise, if you want to
divide a word by another word, then put the dividend
word in AX and fill DX with all 0’s.

3/9/2022 NMAMIT, Nitte 2021-22 47

IDIV : devide by signed byte or word
IDIV source

 Integer divide, same as DIV but the data and the

results are considered as signed integers

 The CF, OF, SF, ZF, AF, and PF flags are

undefined, when IDIV is executed

3/9/2022 NMAMIT, Nitte 2021-22 48

CBW (Convert byte to word)
 The source register AL and the destination AX are both
implied and not specifically mentioned in this instruction

 This instruction is used to extend the 8-bit integer (signed

number) in reg. AL to 16- bit integer in AX

 The process is called sign extension

 If the number in AL is positive, AH will be loaded with 00 hex,

else AH will be loaded with FF hex after execution of CBW
instruction

3/9/2022 NMAMIT, Nitte 2021-22 49

CWD (Convert Word to Double Word)

 Convert word in reg. AX (implied and not stated

in the instruction) to double word in regs. DX:AX
(also implied and not stated)

 That is, sign extend from AX into DX:AX

Example: cwd

3/9/2022 NMAMIT, Nitte 2021-22 50

Examples of DIV instruction:

DIV BX;
DIV WORDPTR [DI];
DIV CL;
DIV BYTEPTR [SI];

3/9/2022 NMAMIT, Nitte 2021-22 51

3/9/2022 NMAMIT, Nitte 2021-22 52
 INC
 The INC instruction adds 1 to a specified register or to a
memory location. AF, OF, PF, SF, and ZF are updated, but
CF is not affected. This means that if an 8-bit destination
containing FFH or a 16-bit destination containing FFFFH is
incremented, the result will be all 0’s with no carry.

 Increment register or memory involves only single operand

 Adds 1 to the destination operand, while preserving the

state of the CF flag

 The destination operand can be a register or a memory

location
3/9/2022 NMAMIT, Nitte 2021-22 53
 INC instruction allows a loop counter to be updated
without disturbing the CF flag

Operation:
DEST ← DEST + 1;

 The CF flag is not affected. The OF, SF, ZF, AF,

and PF flags are set according to the result

 If we use an ADD instruction with an immediate

operand of 1 to perform an increment operation that
does update the CF flag

3/9/2022 NMAMIT, Nitte 2021-22 54

Examples

 INC BL : Add 1 to contains of BL register

 INC CX : Add 1 to contains of CX register
 INC BYTE PTR [BX] : Increment byte in data segment at
offset contained in BX.
 INC WORD PTR [BX]: Increment the word at offset of [BX]
and [BX + 1] in the data segment.
 INC TEMP : Increment byte or word named TEMP in the data
segment
 INC PRICES [BX] : Increment element pointed to by [BX] in
array PRICES. Increment a word if PRICES is declared as an
array of words; Increment a byte if PRICES is declared as an
array of bytes.

3/9/2022 NMAMIT, Nitte 2021-22 55

DEC
 This instruction subtracts 1 from the destination word or byte.
The destination can be a register or a memory location. AF,
OF, SF, PF, and ZF are updated, but CF is not affected. This
means that if an 8-bit destination containing 00H or a 16-bit
destination containing 0000H is decremented, the result will
be FFH or FFFFH with no carry (borrow)
 Similar to INC, this instruction does the operation:
DEST ← DEST – 1;

 The CF flag is not affected

 The OF, SF, ZF, AF, and PF flags are set according to the
result
3/9/2022 NMAMIT, Nitte 2021-22 56
 Examples

 DEC CL: Subtract 1 from content of CL register

 DEC BP : Subtract 1 from content of BP register
 DEC BYTE PTR [BX]: Subtract 1 from byte at offset [BX] in DS.
 DEC WORD PTR [BP] : Subtract 1 from a word at offset [BP] in
SS.
 DEC COUNT : Subtract 1 from byte or word named COUNT in
DS. Decrement a byte if COUNT is declared with a DB;
Decrement a word if COUNT is declared with a DW.

3/9/2022 NMAMIT, Nitte 2021-22 57

NEG: Form 2’s complement
NEG destination
 Replaces the value of operand (the destination
operand) with its two’s complement

 This operation is equivalent to subtracting the

operand from 0

 The destination operand is located in a general-

purpose register or a memory location
DEST ← – (DEST)
Example: NEG AL

3/9/2022 NMAMIT, Nitte 2021-22 58

Flags Affected

 The CF flag set to 0 if the source operand is 0;

otherwise it is set to 1

 The OF, SF, ZF, AF, and PF flags are set

according to the result

 Ex: ;AL=0000 0110H=06H

NEG AL ; replace number in AL with its 2’s complement
;RESULT:1111 1010=FAH

3/9/2022 NMAMIT, Nitte 2021-22 59

 Decimal (BCD, ASCII)
Arithmetic Instructions

3/9/2022 NMAMIT, Nitte 2021-22 60

DAA: Decimal adjust accumulator (AL) after BCD
addition
 BCD is numbers 0 through 9 converted to four-digit binary
(nibble).
 Packed BCD typically encodes two digits within a single byte
Where as unpacked BCD encodes one digit in a single byte.

 DAA Instruction adjusts the sum of two packed BCD values to

create a packed BCD result.

 The AL register is the implied source and destination operand

 The DAA instruction is only useful when it follows an ADD

instruction that adds (binary addition) two 2 - digit, packed
BCD values and stores a byte result in the AL register

3/9/2022 NMAMIT, Nitte 2021-22 61

 The DAA instruction then adjusts the contents of
the AL register to contain the correct 2-digit,
packed BCD result

 If a decimal carry is detected, the CF and AF

flags are set accordingly

 If the lower nibble in AL after an addition is

greater than 9 or AF was set by the addition,
then the DAA instruction will add 6 to the lower
nibble in AL

3/9/2022 NMAMIT, Nitte 2021-22 62

 If the result in the upper nibble of AL is now
greater then 9 or if the carry flag was set by the
addition or correction, then DAA instruction will
add 60H to AL

3/9/2022 NMAMIT, Nitte 2021-22 63

Example 1:
; AL = 0101 1001 = 59 BCD
; BL = 0011 0101 = 35 BCD
ADD AL, BL ; AL = 1000 1110 = 8EH AF=0,CF=0
DAA ; Add 0110 Because lower nibble
1110 > 9
; AL = 1001 0100 = 94 BCD

3/9/2022 NMAMIT, Nitte 2021-22 64

Example 2:
; AL = 1000 1000 = 88 BCD
; BL = 0100 1001 = 49 BCD
ADD AL, BL ; AL = 1101 0001=D1h, AF = 1,CF=0
DAA ; Add 0110 because AF=1
; AL = 1101 0111 = D7H
; add 0110 0000 because higher
nibble 1101 > 9
; AL = 0011 0111 = 37 BCD, CF = 1

3/9/2022 NMAMIT, Nitte 2021-22 65

Example 3:
; AL = 1000 1000 = 88 BCD
; BL = 1001 0001 = 91 BCD
ADD AL, BL ; AL = 0001 1001=19h, CF = 1,AF=0
DAA ; Add 0110 0000 because CF=1
; AL = 0111 1001 = 79 BCD,CF=1

3/9/2022 NMAMIT, Nitte 2021-22 66

 Flags affected

 The CF and AF flags are set if the adjustment of

the value results in a decimal carry in either digit
of the result

 The SF, ZF, and PF flags are set according to

the result

 The OF flag is undefined

3/9/2022 NMAMIT, Nitte 2021-22 67

DAS: Decimal adjust after BCD subtraction
 Adjusts the result of the subtraction of two packed
BCD values to create a packed BCD result

 The AL register is the implied source and destination

operand

 The DAS instruction is only useful when it follows a

SUB instruction that subtracts (binary subtraction)
one 2-digit, packed BCD value from another and
stores a byte result in the AL register

3/9/2022 NMAMIT, Nitte 2021-22 68

 The DAS instruction then adjusts the contents of the
AL register to contain the correct 2-digit, packed
BCD result

 If a decimal borrow is detected, the CF and AF flags

are set accordingly

 The CF and AF flags are set if the adjustment of the

value results in a decimal borrow in either digit of the
result

 The SF, ZF, and PF flags are set according to the

result. The OF flag is undefined

3/9/2022 NMAMIT, Nitte 2021-22 69

Examples:
;AL=1000 0110=86 BCD
; BH=0101 0111=57 BCD
SUB AL,BH ;AL=0010 1111=2FH,CF=0
DAS ; subtracts 0000 0110 because Lower nibble of result is 1111>9
to give AL=0010 1001=29 BCD

;AL=0100 1001=49 BCD

;BH=0111 0010=72 BCD
SUB AL,BH ; AL=1101 0111=D7H,CF=1
DAS ; Subtracts 0110 0000(-60H) bcoz 1101 in upper nibble >9
;AL=01110111=77BCD,CF=1
;CF=1 means borrow was needed

3/9/2022 NMAMIT, Nitte 2021-22 70

AAA: ASCII adjust AL after addition
 Adjusts the sum of two unpacked BCD values to
create an unpacked BCD result

 The AAA instruction works only on the AL

register .It is the implied source and destination
operand for this instruction

 The AAA instruction is only useful when it

follows an ADD instruction that adds (binary
addition) two unpacked BCD values and stores a
byte result in the AL register
3/9/2022 NMAMIT, Nitte 2021-22 71
 Numerical data coming into a computer from a terminal
is usually in ASCII code. In this code, the numbers 0 to 9
are represented by the ASCII codes 30H to 39H.

 The 8086 allows you to add the ASCII codes for two
decimal digits without masking off the “3” in the upper
nibble of each.

 After the addition, the AAA instruction is used to make

sure the result is the correct unpacked BCD.

3/9/2022 NMAMIT, Nitte 2021-22 72

 Example:
;assume AL=0011 0101, ASCII 5
BL=0011 1001, ASCII 9
ADD AL,BL Result: AL=0110 1110=6EH,Which is incorrect BCD
AAA ; Changes AL=0000 0100,Unpacked BCD 4.
CF=1 indicates answer is 14 decimal
 AAA instruction does the following changes

IF ((AL AND 0FH) > 9) OR (AF = 1)

THEN
AL ← AL + 6;
AH ← AH + 1;
AF ← 1; CF ← 1;
ELSE
AF ← 0; CF ← 0;
AL ← AL AND 0FH;

3/9/2022 NMAMIT, Nitte 2021-22 73

 The AAA instruction then adjusts the contents of the
AL register to contain the correct 1-digit unpacked
BCD result

 If the addition produces a decimal carry, the AH

register increments by 1, and the CF and AF flags
are set

 If there was no decimal carry, the CF and AF flags

are cleared and the AH register is unchanged

 In either case, bits 4 through 7 of the AL register are

set to 0
3/9/2022 NMAMIT, Nitte 2021-22 74
 The AF and CF flags are set to 1 if the
adjustment results in a decimal carry otherwise
they are set to 0

 The OF, SF, ZF, and PF flags are undefined

3/9/2022 NMAMIT, Nitte 2021-22 75

IF ((AL AND 0FH) > 9) OR (AF = 1)
THEN
AL ← AL + 6;
AH ← AH + 1;
AF ← 1;
CF ← 1;
ELSE
AF ← 0;
CF ← 0;
AL ← AL AND 0FH;

3/9/2022 NMAMIT, Nitte 2021-22 76

AAS: ASCII adjust AL after subtraction
 Adjusts the result of the subtraction of two
unpacked BCD values to create a unpacked BCD
result

 The AL register is the implied source and

destination operand for this instruction

 The AAS instruction is only useful when it follows

a SUB instruction that subtracts (binary
subtraction) one unpacked BCD value from
another and stores a byte result in the AL
3/9/2022 NMAMIT, Nitte 2021-22 77
 The AAA instruction then adjusts the contents of
the AL register to contain the correct 1-digit
unpacked BCD result

 If the subtraction produced a decimal carry, the

AH register decrements by 1, and the CF and
AF flags are set. If no decimal carry occurred,
the CF and AF flags are cleared, and the AH
register is unchanged

 In either case, the AL register is left with its top

nibble set to 0

3/9/2022 NMAMIT, Nitte 2021-22 78

 Example:
;assume BL=0011 1001=39h =ASCII 9
AL=0011 0101=35h =ASCII 5
SUB AL,BL Result: AL=0000 0100=BCD 04 and CF=0
AAS ; result: AL=0000 0100= BCD 04 and CF=0;no borrow required

;assume AL=0011 0101=35h=ASCII5

BL=0011 1001=39h=ASCII 9
SUB AL,BL; Result: AL=1111 1100=-4 in 2’s compliment and
CF=1
AAS; result: AL=0000 0100= BCD 04 and CF=1;
borrow needed

3/9/2022 NMAMIT, Nitte 2021-22 79

IF ((AL AND 0FH) > 9) OR (AF = 1)
THEN
AL ← AL – 6;
AH ← AH – 1;
AF ← 1;
CF ← 1;
ELSE
CF ← 0;
AF ← 0;
AL ← AL AND 0FH;

3/9/2022 NMAMIT, Nitte 2021-22 80

AAM: ASCII adjust AX after multiply
 Adjusts the result of the multiplication of two
unpacked BCD values to create a pair of
unpacked (base 10) BCD values

 AAM works only after the multiplication of two

unpacked BCD bytes and it works only on an
operand in AL.
 The AAM instruction then adjusts the contents of
the AX register to contain the correct 2-digit
unpacked (base 10) BCD result

3/9/2022 NMAMIT, Nitte 2021-22 81

Example:
;AL=0000 0101=unpacked BCD 5
; BH=0000 1001=unpacked BCD 9
MUL BH ;AL x BH; result in AX
;AX=00000000 00101101=002DH
AAM ;AX=00000100 00000101=0405H
;which is unpacked BCD for 45

3/9/2022 NMAMIT, Nitte 2021-22 82

AAD: ASCII adjust AX before division

 AAD converts two unpacked BCD digits in AH and AL to

the equivalent binary number in AL

 Adjusts two unpacked BCD digits (the least significant

digit in the AL register and the most significant digit in
the AH register) so that a division operation performed
on the result will yield a correct unpacked BCD value

 The AAD instruction is only useful when it precedes a

DIV instruction that divides (binary division) the adjusted
value in the AX register by an unpacked BCD value

3/9/2022 NMAMIT, Nitte 2021-22 83

 The AAD instruction sets the value in the AL register
to (AL + (10 * AH)), and then clears the AH register
to 00H

 The value in the AX register is then equal to the

binary equivalent of the original unpacked two digit
(base 10) number in registers AH and AL

3/9/2022 NMAMIT, Nitte 2021-22 84

Example:
;AX =0607H unpacked BCD for 67 decimal
;CH=09H
AAD; result: AX=0043=43H=67 decimal
DIV CH; divide AX by unpacked BCD in CH
;quotient: AL=07 unpacked BCD
;remainder : AH=04 unpacked BCD
;flags undefined after DIV

3/9/2022 NMAMIT, Nitte 2021-22 85

 Logical Instructions

3/9/2022 NMAMIT, Nitte 2021-22 86

AND

 Performs a bitwise AND operation on the

destination (first) and source (second) operands
and stores the result in the destination operand
location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

3/9/2022 NMAMIT, Nitte 2021-22 87

 Each bit of the result is set to 1 if both
corresponding bits of the first and second
operands are 1; otherwise, it is set to 0

Operation:
DEST ← DEST AND SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

3/9/2022 NMAMIT, Nitte 2021-22 88

 Examples
 AND CX, [SI] : AND word in DS at offset [SI] with word in CX
register; Result in CX register

 AND BH, CL : AND byte in CL with byte in BH; Result in BH

 AND BX, 00FFH: 00FFH Masks upper byte, leaves lower byte
unchanged.

3/9/2022 NMAMIT, Nitte 2021-22 89

OR
 Performs a bitwise inclusive OR operation
between the destination (first) and source
(second) operands and stores the result in the
destination operand location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

3/9/2022 NMAMIT, Nitte 2021-22 90

 Each bit of the result of the OR instruction is set
to 0 if both corresponding bits of the first and
second are 0; otherwise it is set to 1

Operation:
DEST ← DEST OR SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

3/9/2022 NMAMIT, Nitte 2021-22 91

 Example:
 OR AH, CL : CL ORed with AH, result in AH, CL not changed

 OR BP, SI : SI ORed with BP, result in BP, SI not changed

 OR SI, BP : BP ORed with SI, result in SI, BP not changed

 OR BL, 80H : BL ORed with immediate number 80H; sets MSB
of BL to 1

 OR AH, 0F H: AH ORed with immediate number 0FH; sets LSB

of AH and MSB is not changed

 OR CX, TABLE [SI] : CX ORed with word from effective

address TABLE [SI]; Content of memory is not changed.

3/9/2022 NMAMIT, Nitte 2021-22 92

XOR

 Performs a bitwise exclusive OR (XOR)

operation on the destination (first) and source
(second) operands and stores the result in the
destination operand location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

3/9/2022 NMAMIT, Nitte 2021-22 93

 Each bit of the result is 1 if the corresponding
bits of the operands are different; each bit is 0 if
the corresponding bits are the same

Operation:
DEST ← DEST XOR SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

3/9/2022 NMAMIT, Nitte 2021-22 94

Examples:
 XOR CL, BH : Byte in BH exclusive-ORed with byte in CL.
Result in CL. BH not changed.

 XOR BP, DI : Word in DI exclusive-ORed with word in BP.

Result in BP. DI not changed.

 XOR WORD PTR [BX], 00FFH : Exclusive-OR

immediate number 00FFH with word at offset [BX] in the data
segment. Result in memory location [BX]

3/9/2022 NMAMIT, Nitte 2021-22 95

NOT

 Performs a bitwise NOT operation (each 1 is set

to 0, and each 0 is set to 1) or does 1’s
complementing on the destination operand and
stores the result in the destination operand
location

 The destination operand can be a register or a

memory location

3/9/2022 NMAMIT, Nitte 2021-22 96

 Operation:
DEST ← NOT DEST;
Flags Affected:
None
 NOT BX : Complement content or BX register
 NOT BYTE PTR [BX] :Complement memory byte at
offset [BX] in data segment

3/9/2022 NMAMIT, Nitte 2021-22 97

TEST
 Bitwise AND the two sources operands, ignore the
outcome, but preserve the nature of the result in
the flag register

 This instruction computes the bit-wise logical AND

of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the
SF, ZF, and PF status flags according to the result

 The result is then discarded

3/9/2022 NMAMIT, Nitte 2021-22 98

 TEST AL, BH : AND BH with AL. No result stored; Update
PF, SF, ZF.

 TEST CX, 0001H : AND CX with immediate number

0001H; No result stored; Update PF, SF, ZF


 TEST BP, [BX][DI] : AND word from offset [BX][DI] in DS

with word in BP. No result stored. Update PF, SF, and ZF

3/9/2022 NMAMIT, Nitte 2021-22 99

 Operation:

TEMP ← SRC1 AND SRC2;

SF ← MSB(TEMP);
IF TEMP = 0
THEN ZF ← 1;
ELSE ZF ← 0;
PF ← Parity of the lower 8-bits of TEMP;
CF ← 0;
OF ← 0;
(*AF is Undefined*)

3/9/2022 NMAMIT, Nitte 2021-22 100

 Shift and Rotate
Instructions

3/9/2022 NMAMIT, Nitte 2021-22 101

Shift and Rotate instructions

 Shift and Rotate instructions shift the data

by one or more bits towards either left or
right, straight or in a circular fashion

 The carry flag is always involved in these

operations

3/9/2022 NMAMIT, Nitte 2021-22 102

Shift Instructions…
 Shift instructions move or Shift numbers to
the left or right within a register or memory
location

 There are two logical shifts and two

arithmetic shifts

 Logical shift operations function with

unsigned numbers, and arithmetic shifts
function with signed numbers
3/9/2022 NMAMIT, Nitte 2021-22 103
Two logical shift instructions are SHL, SHR

 The logical shifts move 0 into the rightmost

bit position for a logical left shift and a 0 into
the leftmost bit position for a logical right shift

3/9/2022 NMAMIT, Nitte 2021-22 104

The arithmetic shift instructions are
SAL, SAR
 The arithmetic and logical left shifts are
identical. That is SAL and SHL are
identical

 The arithmetic and logical right shifts are

different because the arithmetic right shift
copies the sign-bit through the number, while
the logical right shift copies a 0 through the
number
3/9/2022 NMAMIT, Nitte 2021-22 105
 Logical shifts multiply or divide unsigned
data, and arithmetic shifts multiply or divide
signed data

 A shift left always multiplies by 2 for each bit

position shifted, and a shift right always
divides by 2 for each bit position shifted

3/9/2022 NMAMIT, Nitte 2021-22 106

SHL – Shift Operand Bits Left, Put Zero in
LSBs

SHL Destination, Count

SAL Destination, Count

3/9/2022 NMAMIT, Nitte 2021-22 107

 SAL Destination, Count
SHL Destination, Count
 This instruction shifts each bit in the specified destination
some number of bit positions to the left. As a bit is shifted out
of the LSB operation, a 0 is put in the LSB position. The MSB
will be shifted into CF.
 If the desired number of shifts is 1, this can be specified by
putting a 1 in the count position of the instruction

CF  MSB LSB  0
 For shifts of more than 1 bit position, the desired number of
shifts is loaded into the CL register
Example: MOV CL, 05H
SHL AX, CL

3/9/2022 NMAMIT, Nitte 2021-22 108

 The destination operand can be a byte or a word. It can be in a
register or in a memory location
 The flags affected: CF contains the bit most recently shifted out
from MSB.
 For a count of one, OF will be 1 if CF and the current MSB are
not the same. For multiple-bit shifts, OF is undefined.
 SF and ZF will be updated to reflect the condition of the
destination. PF will have meaning only for an operand in AL. AF
is undefined.
 SAL BX, 1 : Shift word in BX 1 bit position left, 0 in LSB
 MOV CL, 02h : Load desired number of shifts in CL
SAL BP, CL: Shift word in BP left CL bit positions, 0 in LSBs
 SAL BYTE PTR [BX], 1 : Shift byte in DS at offset [BX] 1 bit
position left, 0 in LSB

3/9/2022 NMAMIT, Nitte 2021-22 109

SHR – Shift Operand Bits Right, New MSB = 0

SHR Destination, Count

3/9/2022 NMAMIT, Nitte 2021-22 110

SHR Destination, Count

 This instruction shifts each bit in the specified

destination some number of bit positions to
the right. As a bit is shifted out of the MSB
position, a 0 is put in its place. The bit shifted
out of the LSB position goes to CF.

0  MSB LSB  CF

3/9/2022 NMAMIT, Nitte 2021-22 111

 If the desired number of shifts is 1, this can be specified by
putting a 1 in the count position of the instruction

SHR BP, 1: Shift word in BP one bit position right, 0 in MSB

 For shifts of more than 1 bit position, the desired number of

shifts is loaded into the CL register

Example:
MOV CL, 03H
SHR AL,CL: Shift byte in AL 3 bits right; 0’s in 3 MSBs

MOV CL, 03H : Load desired number of shifts into CL

SHR BYTE PTR [BX],CL : Shift byte in DS at offset [BX] 3 bits
right; 0’s 3 MSBs

3/9/2022 NMAMIT, Nitte 2021-22 112

SAR Destination, Count

 This instruction shifts each bit in the specified destination

some number of bit positions to the right. As a bit is shifted
out of the MSB position, a copy of the old MSB is put in the
MSB position. In other words, the sign bit is copied into the
MSB. The LSB will be shifted into CF.

3/9/2022 NMAMIT, Nitte 2021-22 113

 The destination operand can be a byte or a word. It can be in a
register or in a memory location.
 If you want to shift the operand by one bit position, you can
specify this by putting a 1 in the count position of the instruction.
 For shifts of more than 1 bit position, load the desired number of
shifts into the CL register, and put “CL” in the count position of the
instruction.
 The flags are affected as follow: CF contains the bit most recently
shifted in from LSB. Only AF will be undefined after SAR. Other
flags OF,SF,PF changes accordingly
 Examples :
 SAR DI,1: Shift word in DI one bit position right, new MSB = old MSB
 MOV CL, 02H : Load desired number of shifts in CL
 SAR WORD PTR [BP], CL : Shift word at offset [BP] in stack
segment right by two bit positions, the two MSBs are now copies of old
MSB
3/9/2022 NMAMIT, Nitte 2021-22 114
ROL – Rotate All Bits of Operand Left, MSB
to LSB and CF
ROL Destination, Count
 This instruction rotates all the bits in a
specified word or byte to the left some number
of bit positions

CF MSB LSB

3/9/2022 NMAMIT, Nitte 2021-22 115

 If the desired number of shifts is 1, this can be specified
by putting a 1 in the count position of the instruction
 For shifts of more than 1 bit position, the desired number
of shifts is loaded into the CL register.
 The destination can be a register or a memory location.

 ROL affects only CF and OF. OF will be a 1 after a

single bit ROL if the MSB was changed by the rotate.
Example:
ROL AX, 1: Rotate the word in AX 1 bit position left, MSB to LSB
and CF
MOV CL, 04H : Load number of bits to rotate in CL
ROL BL, CL :Rotate BL 4 bit positions
ROL FACTOR [BX], 1 : Rotate the word or byte in DS at EA =
FACTOR [BX] by 1 bit position left MSB to
LSB and into CF

3/9/2022 NMAMIT, Nitte 2021-22 116

ROR – Rotate All Bits of Operand Right,
LSB to MSB and CF
ROR Destination, Count
 This instruction rotates all the bits in a
specified word or byte to the right some
number of bit positions

CF MSB LSB

3/9/2022 NMAMIT, Nitte 2021-22 117

 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of the
instruction
 For shifts of more than 1 bit position, the desired
number of shifts is loaded into the CL register
 ROR affects only CF and OF. OF will be a 1 after a
single bit ROR if the MSB was changed by the rotate.

Example:
ROR BL, 1: Rotate all bits in BL right 1 bit position LSB to MSB
and to CF
MOV CL,08H :Load CL with number of bit positions to be rotated
ROR WORD PTR [BX], CL Rotate word in DS at offset [BX]
8 bit position right

3/9/2022 NMAMIT, Nitte 2021-22 118

 For the ROL and ROR instructions, the original
value of the CF flag is not a part of the result,
but the CF flag receives a copy of the bit that
was shifted from one end to the other

3/9/2022 NMAMIT, Nitte 2021-22 119

RCL (Rotate Left including carry)
 The RCL instruction shifts the CF flag into the least-
significant bit and shifts the most significant bit into the
CF flag

 RCL affects only CF and OF. OF will be a 1 after a single

bit RCL if the MSB was changed by the rotate. OF is
undefined after the multi-bit rotate.

3/9/2022 NMAMIT, Nitte 2021-22 120

Examples:

 RCL DX, 1 : Word in DX 1 bit left, MSB to CF, CF to LSB

 MOV CL, 4 : Load the number of bit positions to rotate into CL

RCL SUM [BX], CL : Rotate byte or word at effective
address SUM [BX] 4 bits left Original bit 4 now in CF, old CF
now in bit 3

3/9/2022 NMAMIT, Nitte 2021-22 121

RCR (Rotate Right including carry)
 The RCR instruction shifts the CF flag into the most-
significant bit and shifts the least- significant bit into the
CF flag

 RCR affects only CF and OF. OF will be a 1 after a

single bit RCR if the MSB was changed by the rotate. OF
is undefined after the multi-bit rotate

3/9/2022 NMAMIT, Nitte 2021-22 122

Examples:

 RCR BX, 1: Word in BX right 1 bit, CF to MSB, LSB to CF 

 MOV CL, 4 : Load CL for rotating 4 bit position

RCR BYTE PTR [BX], 4 : Rotate the byte at offset [BX]
in DS 4 bit positions right CF = original bit 3, Bit 4 – original CF.

3/9/2022 NMAMIT, Nitte 2021-22 123

3/9/2022 NMAMIT, Nitte 2021-22 124
 Control Transfer
Instructions

3/9/2022 NMAMIT, Nitte 2021-22 125

 The intelligence in any program lies in the ability
of the program to follow different courses of
action based on intermediate results produced
during the working of the program; that way, the
program is enabled to perform data sensitive
tasks

 This capability is obtained by context sensitive

jump operations, in contrast to the normal
sequential cyclical operation of fetching the next
instruction and executing it, in the order in which
it is found in the program

3/9/2022 NMAMIT, Nitte 2021-22 126

JMP: Jump instruction

 Transfers program control to a different point in

the instruction stream without recording return
information

 This instruction can be used to execute three

different types of jumps: Near Jump, Short Jump
and Far Jump…

3/9/2022 NMAMIT, Nitte 2021-22 127

 Near jump—A jump to an instruction within the
current code segment (the segment currently
pointed to by the CS register), sometimes referred to
as an intra segment jump or near jump

 Short jump—A near jump where the jump range is

limited to –128 to +127 from the current IP value

 Far jump—A jump to an instruction located in a

different segment than the current code segment, is
sometimes referred to as an inter segment jump or
far jump.

3/9/2022 NMAMIT, Nitte 2021-22 128

Examples
 JMP CONTINUE : This instruction fetches the next instruction
from address at label CONTINUE.
 If the label is in the same segment, an offset coded as part of the
instruction will be added to the instruction pointer to produce the
new fetch address.
 If the label is another segment, then IP and CS will be replaced with
value coded in the instruction. This type of jump is referred to as
direct because the displacement of the destination or the destination
itself is specified directly in the instruction.

 JMP BX : This instruction replaces the content of IP with the

content of BX. BX must first be loaded with the offset of the
destination instruction in CS. This is a near jump. It is also
referred to as an indirect jump because the new value of IP
comes from a register rather than from the instruction itself, as
in a direct jump.
3/9/2022 NMAMIT, Nitte 2021-22 129
 JMP WORD PTR [BX] : This instruction replaces IP with
word from a memory location pointed to by BX in DS.
This is an indirect near jump.

 JMP DWORD PTR [SI] : This instruction replaces IP

with word pointed to by SI in DS. It replaces CS with a
word pointed by SI + 2 in DS. This is an indirect far jump.

3/9/2022 NMAMIT, Nitte 2021-22 130

 Conditional Jump Instructions…

3/9/2022 NMAMIT, Nitte 2021-22 131

 JA / JNBE
JUMP IF ABOVE / JUMP IF NOT BELOW OR EQUAL:
 After a compare or some other instructions, if the zero flag and the carry
flag both are 0, this instruction will cause execution to jump to a label
given in the instruction. If CF and ZF are not both 0, the instruction will
have no effect on program execution.

 Examples:
 CMP AX, 4371H : Compare by subtracting 4371H from AX
JA NEXT : Jump to label NEXT if AX above 4371H

 CMP AX, 4371H : Compare (AX – 4371H)

JNBE NEXT : Jump to label NEXT if AX not below or equal to
4371H

3/9/2022 NMAMIT, Nitte 2021-22 132

JAE / JNB / JNC
JUMP IF ABOVE OR EQUAL / JUMP IF NOT BELOW / JUMP IF NO CARRY
 After a compare or some other instructions, if the carry flag is
0, this instruction will cause execution to jump to a label given
in the instruction. If CF is 1, the instruction will have no effect
on program execution.
 Example:
 CMP AX, 4371H : Compare (AX – 4371H)
JAE NEXT : Jump to label NEXT if AX above 4371H

 CMP AX, 4371H : Compare (AX – 4371H)

 JNB NEXT : Jump to label NEXT if AX not below 4371H

 ADD AL, BL : Add two bytes

 JNC NEXT : If the result with in acceptable range, jump next
3/9/2022 NMAMIT, Nitte 2021-22 133
 JB / JC / JNAE
JUMP IF BELOW / JUMP IF CARRY / JUMP IF NOT ABOVE OR EQUAL
 After a compare or some other instructions, if the carry flag is
1, this instruction will cause execution to jump to a label given in
the instruction. If CF is 0, the instruction will have no effect on
program execution.
 Examples:
 CMP AX, 4371H : Compare (AX – 4371H)
JB DOWN : Jump to label DOWN if AX below 4371H

 ADD BX, CX : Add two words

JC DOWN : Jump to label DOWN if CF = 1

 CMP AX, 4371H : Compare (AX – 4371H)

JNAE NEXT : Jump to label NEXT if AX not above or equal to 4371H
3/9/2022 NMAMIT, Nitte 2021-22 134
JBE / JNA
JUMP IF BELOW OR EQUAL / JUMP IF NOT ABOVE

 After a compare or some other instructions, if either the zero

flag or the carry flag is 1, this instruction will cause execution to
jump to a label given in the instruction. If CF and ZF are both 0,
the instruction will have no effect on program execution.

 Examples:
 CMP AX, 4371H : Compare (AX – 4371H)
JBE NEXT :Jump to label NEXT if AX is below or equal to 4371H

 CMP AX, 4371H : Compare (AX – 4371H)

JNA NEXT : Jump to label NEXT if AX not above 4371H

3/9/2022 NMAMIT, Nitte 2021-22 135

 JG / JNLE
JUMP IF GREATER / JUMP IF NOT LESS THAN OR EQUAL

 The instruction will cause a jump to the label given in the

instruction, after a Compare instruction, if the zero flag is 0
and the carry flag is the same as the overflow flag.

 Examples:
 CMP BL, 39H : Compare by subtracting 39H from BL
JG NEXT : Jump to label NEXT if BL more positive than 39H

 CMP BL, 39H : Compare by subtracting 39H from BL

 JNLE NEXT : Jump to label NEXT if BL is not less than or equal to
39H
3/9/2022 NMAMIT, Nitte 2021-22 136
 JGE / JNL
JUMP IF GREATER THAN OR EQUAL / JUMP IF NOT LESS THAN

 The instruction will cause a jump to the label given in the

instruction, after a Compare instruction. if the sign flag is
equal to the overflow flag.

 Example:
 CMP BL, 39H : Compare by subtracting 39H from BL
JGE NEXT : Jump to label NEXT if BL more positive than or equal to 39H

 CMP BL, 39H : Compare by subtracting 39H from BL

JNL NEXT :Jump to label NEXT if BL not less than 39H

3/9/2022 NMAMIT, Nitte 2021-22 137

JL / JNGE
JUMP IF LESS THAN / JUMP IF NOT GREATER THAN OR EQUAL

 The instruction will cause a jump to the label given in the

instruction, after a Compare instruction, if the sign flag is not
equal to the overflow flag.

 Example:
 CMP BL, 39H : Compare by subtracting 39H from BL
JL AGAIN : Jump to label AGAIN if BL more negative than 39H

 CMP BL, 39H : Compare by subtracting 39H from BL

JNGE AGAIN : Jump to label AGAIN if BL not more positive than or
equal to 39H

3/9/2022 NMAMIT, Nitte 2021-22 138

 JLE / JNG
JUMP IF LESS THAN OR EQUAL / JUMP IF NOT GREATER

 The instruction will cause a jump to the label given in the

instruction, after a Compare instruction, if the zero flag is set, or if
the sign flag not equal to the overflow flag.

 Examples:
 CMP BL, 39H : Compare by subtracting 39H from BL
JLE NEXT : Jump to label NEXT if BL more negative than or equal to 39H

 CMP BL, 39H : Compare by subtracting 39H from BL

JNG NEXT : Jump to label NEXT if BL not more positive than 39H

3/9/2022 NMAMIT, Nitte 2021-22 139

JE / JZ
JUMP IF EQUAL / JUMP IF ZERO
 After a compare or some other instructions, If the zero
flag is set, then this instruction will cause a jump to the
label given in the instruction.

 Example:
 CMP BX, DX : Compare (BX-DX)
JE DONE :Jump to DONE if BX = DX

 IN AL, 8FH : Read data from port 8FH

SUB AL, 30H : Subtract 30H from AL.
JZ START : Jump to label START if the result of subtraction is 0

3/9/2022 NMAMIT, Nitte 2021-22 140

JNE / JNZ
JUMP NOT EQUAL / JUMP IF NOT ZERO
 After a compare or some other instructions, If the zero flag is 0,
then this instruction will cause a jump to the label given in the
instruction.

 Example:
 IN AL, 0F8H : Read data value from port
CMP AL, 72 : Compare (AL –72)
JNE NEXT : Jump to label NEXT if AL is not 72

 ADD AX, 0002H : Add count factor 0002H to AX

DEC BX : Decrement BX
JNZ NEXT :Jump to label NEXT if BX is not 0

3/9/2022 NMAMIT, Nitte 2021-22 141

JS
JUMP IF SIGNED / JUMP IF NEGATIVE

 This instruction will cause a jump to the specified destination

address if the sign flag is set. Since a 1 in the sign flag
indicates a negative signed number, you can think of this
instruction as saying “jump if negative”.

 ADD BL, DH : Add signed byte in DH to signed byte in DL

JS NEXT : Jump to label NEXT if result of addition is negative
number

3/9/2022 NMAMIT, Nitte 2021-22 142

JNS
JUMP IF NOT SIGNED / JUMP IF POSITIVE

 This instruction will cause a jump to the specified destination

address if the sign flag is 0. Since a 0 in the sign flag indicate
a positive signed number, you can think to this instruction as
saying “jump if positive”.

 Example:
 DEC AL : Decrement AL
JNS NEXT : Jump to label NEXT if AL has not decremented to FFH

3/9/2022 NMAMIT, Nitte 2021-22 143

JP / JPE
JUMP IF PARITY / JUMP IF PARITY EVEN

 If the number of 1’s left in the lower 8 bits of a data word after
an instruction which affects the parity flag is even, then the
parity flag will be set. If the parity flag is set, the JP / JPE
instruction will cause a jump to the specified destination
address.

 Example:
 IN AL, 0F8H : Read ASCII character from Port F8H
OR AL, AL : Set flags
JPE ERROR : Odd parity expected, send error message if
parity found even

3/9/2022 NMAMIT, Nitte 2021-22 144

JNP / JPO
JUMP IF NO PARITY / JUMP IF PARITY ODD

 If the number of 1’s left in the lower 8 bits of a data word

after an instruction which affects the parity flag is odd,
then the parity flag is 0. The JNP / JPO instruction will
cause a jump to the specified destination address, if the
parity flag is 0.
 Example:
 IN AL, 0F8H Read ASCII character from Port F8H
OR AL, AL Set flags
JPO ERROR : Even parity expected, send error message if
parity found odd

3/9/2022 NMAMIT, Nitte 2021-22 145

JO (JUMP IF OVERFLOW)

 The overflow flag will be set if the magnitude of the result

produced by some signed arithmetic operation is too
large to fit in the destination register or memory location.
The JO instruction will cause a jump to the destination
given in the instruction, if the overflow flag is set.

 ADD AL, BL : Add signed bytes in AL and BL

 JO ERROR : Jump to label ERROR if overflow from add

3/9/2022 NMAMIT, Nitte 2021-22 146

JNO
(JUMP IF NO OVERFLOW)

 The overflow flag will be set if some signed arithmetic

operation is too large to fit in the destination register or
memory location. The JNO instruction will cause a jump
to the destination given in the instruction, if the overflow
flag is not set.

 ADD AL, BL : Add signed byte in AL and BL

 JNO DONE : Process DONE if no overflow

3/9/2022 NMAMIT, Nitte 2021-22 147

JCXZ
(JUMP IF THE CX REGISTER IS ZERO)

 This instruction will cause a jump to the label to a given

in the instruction, if the CX register contains all 0’s. The
instruction does not look at the zero flag when it decides
whether to jump or not.

 JCXZ SKIP : If CX = 0, skip the process

 SUB [BX], 07H : Subtract 7 from data value
SKIP: ADD BX, DX : Next instruction

3/9/2022 NMAMIT, Nitte 2021-22 148

 MNEMONIC CONDITION TESTED

JA/JNBE(jump if above/jump if not below (CF AND ZF) =0

or equal)

JAE/JNB/JNC(jump if above or CF=0

equal/jump if not below /jump if no carry)

JB/JNAE/JC(jump if below/jump if not CF=1

above or equal/jump if carry)

JBE/JNA(jump if below or equal/jump if (CF OR ZF)=1

not above)

JCXZ(jump if CX register is zero) CX = 0

JE/JZ(jump if equal/jump if zero) ZF = 1

JG/JNLE(jump if greater/jump if not less ((SF XOR OF) OR ZF )

than of equal) =0
3/9/2022 NMAMIT, Nitte 2021-22 149
 MNEMONIC CONDITION TESTED
JGE/JNL(jump if greater than or (SF XOR OF)=0
equal/jump if not less than)

JL/JNGE(jump if less than/jump if (SF XOR OF)=1

not greater than or equal)

JLE/JNG(jump if less than or ((SF XOR OF) OR ZF )=1

equal/jump if not greater)

JNE/JNZ(jump if not equal/jump if ZF=0

not zero)

JNO(jump if no overflow) OF=0 (not overflow)

JNP/JPO(jump if no parity/jump if PF=0 (not parity/parity
parity odd) odd)
JNS(jump if not signed, jump if SF=0 (not sign)
positive)
3/9/2022 NMAMIT, Nitte 2021-22 150
 MNEMONIC CONDITION TESTED

JO(jump if overflow) OF=1 (overflow)

JP/JPE(jump if parity/jump if parity PF (Parity / parity equal)

even)

JS(jump if signed) SF=1 (Sign)

3/9/2022 NMAMIT, Nitte 2021-22 151

LOOP Instruction

 The LOOP instructions are basically conditional

jump instructions which have the format

LOOP LABEL

3/9/2022 NMAMIT, Nitte 2021-22 152

LOOP
JUMP TO SPECIFIED LABEL IF CX != 0 AFTER AUTO DECREMENT

 LOOP instruction combines 2 operations in each

instruction
 The first operation is to decrement the CX register by 1
 The second operation is to check the CX register is zero
by checking zero flag to decide whether to do a jump to
the specified label.

 The destination address for the jump must be in the

range of –128 bytes to +127 bytes from the address of
the instruction after the LOOP instruction.

3/9/2022 NMAMIT, Nitte 2021-22 153

 Example:

 MOV BX, OFFSET PRICES : Point BX at first element in array

MOV CX, 40 : Load CX with number of elements in array
NEXT:MOV AL, [BX] : Get element from array
INC AL : Increment the content of AL
MOV [BX], AL : Put result back in array
INC BX : Increment BX to point to next location
LOOP NEXT : Repeat until all elements adjusted

3/9/2022 NMAMIT, Nitte 2021-22 154

LOOP(jump to specified label if cx≠0 Loop Until CX=0
after auto decrement)

LOOPE / LOOPZ(loop while Loop if zero flag is set and

cx≠0 and zf=1) CX !=0

LOOPNE / LOOPNZ(loop while Loop if zero flag not set and

cx≠0 and zf=0) CX !=0

3/9/2022 NMAMIT, Nitte 2021-22 155

LOOPE / LOOPZ
LOOP WHILE CX != 0 AND ZF = 1
 This instruction is used to repeat a group of instructions some
number of times, or until the zero flag becomes 0. The number
of times the instruction sequence is to be repeated is loaded into
CX.
 Each time the LOOP instruction executes, CX is automatically
decremented by 1. If CX != 0 and ZF = 1, execution will jump to
a destination specified by a label in the instruction.
 If CX = 0, execution simply go on the next instruction after
LOOPE / LOOPZ. In other words, the two ways to exit the loop
are CX = 0 or ZF = 0.
 The destination address for the jump must be in the range of –
128 bytes to +127 bytes from the address of the instruction after
the LOOPE / LOOPZ instruction.

3/9/2022 NMAMIT, Nitte 2021-22 156

Example:

MOV BX, OFFSET ARRAY : Point BX to address of ARRAY

before start of array
DEC BX : Decrement BX
MOV CX, 100 :Put number of array elements in CX
NEXT: INC BX : Point to next element in array
CMP [BX], OFFH : Compare array element with FFH
LOOPE NEXT

3/9/2022 NMAMIT, Nitte 2021-22 157

 LOOPNE / LOOPNZ
LOOP WHILE CX!= 0 AND ZF = 0
 Same as LOOPE instruction except for testing condition
 Each time the LOOPNE / LOOPNZ instruction executes, CX is
automatically decremented by 1. If CX != 0 and ZF = 0, execution
will jump to a destination specified by a label in the instruction. If
CX = 0, after the auto decrement or if ZF = 1, execution simply go
on the next instruction after LOOPNE / LOOPNZ.
 In other words, the two ways to exit the loop are CX = 0 or ZF = 1.

 The destination address for the jump must be in the range of –128
bytes to +127 bytes from the address of the instruction after the
LOOPNE / LOOPZ instruction.

3/9/2022 NMAMIT, Nitte 2021-22 158

Example

MOV BX, OFFSET ARRAY : Point BX to adjust before start of array

DEC BX : Decrement BX
MOV CX, 100 : Put number of array in CX
NEXT: INC BX : Point to next element in array
CMP [BX], ODH : Compare array element with 0DH
LOOPNZ NEXT

3/9/2022 NMAMIT, Nitte 2021-22 159

CALL
 The CALL instruction is used to transfer execution to a
subprogram or a procedure.
 Call instruction is a returnable jump to the destination or the
target address provided in the instruction
 This instruction can be used to execute two different types
of calls:

 Near call — A call to a procedure within the current code

segment (the segment currently pointed to by the CS
register), sometimes referred to as an intra segment call

 Far call — A call to a procedure located in a different

segment than the current code segment, sometimes
referred to as an inter segment call

3/9/2022 NMAMIT, Nitte 2021-22 160

 When executing a near call, the processor
pushes the value of the IP register (which
contains the offset of the instruction following the
CALL instruction) onto the stack (for use later as
a return-instruction pointer)

 The processor then branches to the address in

the current code segment specified with the
target operand

 The CS register is not changed on near calls

3/9/2022 NMAMIT, Nitte 2021-22 161

 When executing a far call, the processor pushes
the current value of both the CS and IP registers
onto the stack for use as a return-instruction
pointer

 The processor then performs a “far branch” to

the code segment and offset specified with the
target operand for the called procedure

3/9/2022 NMAMIT, Nitte 2021-22 162

 Examples
 CALL MULT : This is a direct within segment (near or intra
segment) call. MULT is the name of the procedure. The assembler
determines the displacement of MULT from the instruction after
the CALL and codes this displacement in as part of the instruction.

 CALL BX : This is an indirect within-segment (near or intra-

segment) call. BX contains the offset of the first instruction of the
procedure. It replaces content of IP with content of register BX.

 CALL WORD PTR [BX] :This is an indirect within-segment (near

or intra-segment) call. Offset of the first instruction of the
procedure is in two memory addresses in DS. Replaces content of
IP with content of word memory location in DS pointed to by BX.

3/9/2022 NMAMIT, Nitte 2021-22 163

 CALL DIVIDE: This is a direct call to another segment (far or
inter-segment call). DIVIDE is the name of the procedure. The
procedure must be declared far with DIVIDE PROC FAR at its
start. The assembler will determine the code segment base
for the segment that contains the procedure and the offset of
the start of the procedure. It will put these values in as part of
the instruction code.

 CALL DWORD PTR [BX]: This is an indirect call to another

segment (far or inter-segment call). New values for CS and IP
are fetched from four-memory location in DS. The new value
for CS is fetched from [BX] and [BX + 1]; the new IP is fetched
from [BX + 2] and [BX +3].

3/9/2022 NMAMIT, Nitte 2021-22 164

RET
 The RET (return) instruction returns control back
from the procedure to the program that has
called the procedure

 The control will be returned to the instruction

following the procedure call

 This instruction transfers program control to a

return address located on the top of the stack

3/9/2022 NMAMIT, Nitte 2021-22 165

 The address is usually placed on the stack by a
CALL instruction, and the return is made to the
instruction that follows the CALL instruction

 The optional source operand specifies the

number of stack bytes to be released after the
return address is popped; the default is none
 Examples:
RET
RET 6
RET Near

3/9/2022 NMAMIT, Nitte 2021-22 166

INT –interrupt program execution
INT type
 These instructions are software interrupt procedure
calls

 The type in the instruction format refers to a number

between 0 to 255 which identifies interrupt

3/9/2022 NMAMIT, Nitte 2021-22 167

When an 8086 executes an INT instruction it will

 Decrements the stack pointer by 2 and push the flags

onto the stack

 Decrements the stack pointer by 2 and push the

contents of CS onto stack

 Decrement the stack pointer by 2 and push the offset of

the next instruction(IP) after the INT instruction on the
stack

3/9/2022 NMAMIT, Nitte 2021-22 168

 Get a new value of IP from an absolute memory address
of 4 times the type specified in the instruction
Ex: for INT 8 instruction, a new IP will be read from
address 00020H.

 Get a new value for CS from an absolute memory

address of 4 times the type specified in the instruction
plus 2
Ex: for an INT 8 instruction the new value of CS will be
read from address 00022H

 Reset both IF and TF .other flags are not affected

3/9/2022 NMAMIT, Nitte 2021-22 169

IRET: Return from interrupt

 The IRET instruction performs a far return to the

interrupted program or procedure

 During this operation, the processor pops the

return instruction pointer, return code segment
selector, and FLAGS image from the stack to the
IP, CS, and FLAGS registers, respectively, and
then resumes execution of the interrupted
program or procedure

3/9/2022 NMAMIT, Nitte 2021-22 170

Processor Control Instructions
Flag Manipulation Instructions
 STC : (SET CARRY FLAG) This instruction sets the carry
flag to 1. It does not affect any other flag.
 CLC : (CLEAR CARRY FLAG) This instruction resets the
carry flag to 0. It does not affect any other flag.
 CMC : (COMPLEMENT CARRY FLAG) This instruction
complements the carry flag. It does not affect any other flag.
 STD : (SET DIRECTION FLAG) This instruction sets the
direction flag to 1. It does not affect any other flag.
 CLD : (CLEAR DIRECTION FLAG) This instruction resets the
direction flag to 0. It does not affect any other flag

3/9/2022 NMAMIT, Nitte 2021-22 171

  ST I : (SET INTERRUPT FLAG)
 Setting the interrupt flag to a 1 enables the INTR interrupt input
of the 8086. When the INTR input is enabled, an interrupt signal
on this input will then cause the 8086 to interrupt program
execution, push the return address and flags on the stack, and
execute an interrupt service procedure.

 CLI : (CLEAR INTERRUPT FLAG)

 This instruction resets the interrupt flag to 0. If the interrupt flag is
reset, the 8086 will not respond to an interrupt signal on its INTR
input. The CLI instructions, however, has no effect on the non-
maskable interrupt input, NMI. It does not affect any other flag

3/9/2022 NMAMIT, Nitte 2021-22 172

External Hardware Synchronization
Instructions
 HLT (HALT PROCESSING) The HLT instruction causes the
8086 to stop fetching and executing instructions. The 8086
will enter a halt state. The different ways to get the processor
out of the halt state are with an interrupt signal on the INTR
pin, an interrupt signal on the NMI pin, or a reset signal on the
RESET input.

 ESC (ESCAPE) This instruction is used to pass instructions to

a coprocessor, such as the 8087 Math coprocessor, which
shares the address and data bus with 8086. Instructions for
the coprocessor are represented by a 6-bit code embedded in
the ESC instruction.

3/9/2022 NMAMIT, Nitte 2021-22 173

 WAIT – WAIT FOR SIGNAL OR INTERRUPT SIGNAL When
this instruction is executed, the 8086 enters an idle condition
in which it is doing no processing.
 The 8086 will stay in this idle state until the 8086 test input pin
is made low or until an interrupt signal is received on the INTR
or the NMI interrupt input pins. If a valid interrupt occurs while
the 8086 is in this idle state, the 8086 will return to the idle
state after the interrupt service procedure executes. It returns
to the idle state because the address of the WAIT instruction
is the address pushed on the stack when the 8086 responds
to the interrupt request. WAIT does not affect any flag. The
WAIT instruction is used to synchronize the 8086 with
external hardware such as the 8087 Math coprocessor

3/9/2022 NMAMIT, Nitte 2021-22 174

 LOCK – ASSERT BUS LOCK SIGNAL Many microcomputer
systems contain several microprocessors.
 The LOCK prefix allows a microprocessor to make sure that
another processor does not take control of the system bus
while it is in the middle of a critical instruction, which uses the
system bus.
 The LOCK prefix is put in front of the critical instruction. When
an instruction with a LOCK prefix executes, the 8086 will
assert its external bus controller device, which then prevents
any other processor from taking over the system bus. LOCK
instruction does not affect any flag.
 LOCK XCHG SAMAPHORE, AL The XCHG instruction
requires two bus accesses. The LOCK prefix prevents
another processor from taking control of the system bus
3/9/2022 175
NMAMIT, Nitte 2021-22
between the two accesses
NO OPERATION INSTRUCTION

 NOP (PERFORM NO OPERATION) This

instruction simply uses up three clock cycles
and increments the instruction pointer to point
to the next instruction. The NOP instruction
can be used to increase the delay of a delay
loop. When hand coding, a NOP can also be
used to hold a place in a program for an
instruction that will be added later. NOP does
not affect any flag.

3/9/2022 NMAMIT, Nitte 2021-22 176

Interrupt Instructions:
 INT – INT TYPE The term type in the instruction format refers to a
number between 0 and 255, which identify the interrupt.
 When an 8086 executes an INT instruction, it will
 1. Decrement the stack pointer by 2 and push the flags on to the
stack.
 2. Decrement the stack pointer by 2 and push the content of CS
onto the stack.
 3. Decrement the stack pointer by 2 and push the offset of the next
instruction after the INT number instruction on the stack.
 4. Get a new value for IP from an absolute memory address of 4
times the type specified in the instruction. For an INT 8 instruction,
for example, the new IP will be read from address 00020H.

3/9/2022 NMAMIT, Nitte 2021-22 177

 5. Get a new for value for CS from an absolute memory address of
4 times the type specified in the instruction plus 2, for an INT 8
instruction, for example, the new value of CS will be read from
address 00022H.
 6. Reset both IF and TF. Other flags are not affected.

 INT 35 New IP from 0008CH, new CS from 0008Eh  INT 3 This is

a special form, which has the single-byte code of CCH; Many
systems use this as a break point instruction (Get new IP from
0000CH new CS from 0000EH).

3/9/2022 NMAMIT, Nitte 2021-22 178

 INTO (INTERRUPT ON OVERFLOW) If the overflow flag (OF) is
set, this instruction causes the 8086 to do an indirect far call to a
procedure you write to handle the overflow condition.
 Before doing the call, the 8086 will 1. Decrement the stack pointer
by 2 and push the flags on to the stack. 2. Decrement the stack
pointer by 2 and push CS on to the stack. 3. Decrement the stack
pointer by 2 and push the offset of the next instruction after INTO
instruction onto the stack. Page 25 4. Reset TF and IF. Other flags
are not affected. To do the call, the 8086 will read a new value for IP
from address 00010H and a new value of CS from address 00012H.

3/9/2022 NMAMIT, Nitte 2021-22 179

 IRET (INTERRUPT RETURN) When the 8086 responds to an
interrupt signal or to an interrupt instruction, it pushes the
flags, the current value of CS, and the current value of IP onto
the stack. It then loads CS and IP with the starting address of
the procedure, which you write for the response to that
interrupt. The IRET instruction is used at the end of the
interrupt service procedure to return execution to the
interrupted program. To do this return, the 8086 copies the
saved value of IP from the stack to IP, the stored value of CS
from the stack to CS, and the stored value of the flags back to
the flag register. Flags will have the values they had before
the interrupt, so any flag settings from the procedure will be
lost unless they are specifically saved in some way.

3/9/2022 NMAMIT, Nitte 2021-22 180

read a char form keyboard and display it
data segment
c db ?
msg1 db 0Ah,0Dh, 'Enter the character $'
msg2 db 0Ah,Dh,'The entered character is $'
data ends
code segment
assume cs:code, ds:data
start: mov ax, data ; Initializing data Segment
mov ds, ax

LEA dx, msg1 ; display msg1

mov ah, 09h
int 21h

3/9/2022 NMAMIT, Nitte 2021-22 181

 mov ah, 01h ; read a char into al
int 21h

mov c, al ; store in memory since next instn will update al

LEA dx, msg2 ; display msg2
mov ah, 09h
int 21h
mov dl, c
mov ah, 02h ; display char from dl
int 21h
mov ah, 4ch
int 21h ; terminate
code ends
end start

3/9/2022 NMAMIT, Nitte 2021-22 182

 ; move 5 bytes of data from one location to another

 data segment
array1 db 10h,20h,30h,40h,50h
len db $-array1
array2 db 5 dup(?)
 data ends
 code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov cx, len ; set Counter
lea si, array1
lea di, array2
up: mov al,[si]
mov [di],al
inc si
inc di
loop up ; decrement cx by 1 compare with 0 if false loop up else break
mov ah,4ch ; Terminate the program
int 21h
code ends
end start

3/9/2022 NMAMIT, Nitte 2021-22 183